BR24C02 Rohm, BR24C02 Datasheet
BR24C02
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BR24C02 Summary of contents
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... A (typ.) standby current: 5V • Automatic Word Address Incrementing – Sequential register read • Automatic erase-before-write. • Page write buffer for bytes: BR24C01A / bytes: BR24C02 / bytes: BR24C04 / F • DATA security –Inhibit to write at low • ...
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... Memory ICs • Over view The BR24C01A / AF, BR24C02 / F, and BR24C04 / F are 2-wire serial EEPROMs which are electrically programmable. The configurations are as follows: BR24C01A / AF: 128 8 bit 1K serial EEPROM BR24C02 / F: 256 8 bit 2K serial EEPROM BR24C04 / F: 512 8 bit 4K serial EEPROM • Block diagram BR24C01A / AF ...
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... Output low level voltage V OL Input leakage current I LI Output leakage current I LO Operating current dissipation I CC Standby current I SB SCL frequency f SCL BR24C01A / BR24C01AF / BR24C02 / BR24C02F / Limits – 0 6.5 1 DIP8 pin 500 2 SOP8 pin 350 – 125 – – 0 0.3 CC Limits 2.7 ~ 5.5 (WRITE) 2.7 ~ 5.5 (READ ...
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... Stop condition setup time Bus open time before start of transfer 1 Internal write cycle time 2 Noise erase valid time (SCL / SDA pins 4 2.7 to 4.5V CC Not designed for radiation resistance. 4 BR24C01A / BR24C01AF / BR24C02 / BR24C02F / = 2.7 to 5.5V) CC Symbol Min. Typ. t 4.0 — HIGH t 4.7 — LOW t — ...
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... BUF SDA (output) SCL t : STA SU SDA SCL SDA Write data (n address) BR24C01A / BR24C01AF / BR24C02 / BR24C02F / HD: STA t : DAT STA HD START BIT • Data is read on the rising edge of SCL. • Data is output in synchronization with the falling edge of SCL. Fig.1 Synchronized data input / output timing ...
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... In the WRITE mode, the transferred data is not written to the memory unless the stop bit is executed. (4) Device addressing With the BR24C01A / AF and BR24C02 / F Make sure the slave address is output from the master immediately after the start condition. The upper four bits of the slave address are used to determine the device type. The device code for this IC is fixed at “ ...
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... SDA ( -COM output data) SDA (BR24C01A / AF, BR24C02 / F, BR24C04 / F output data) BR24C01A / BR24C01AF / BR24C02 / BR24C02F / When data is being written to this IC, a LOW acknowl- edge signal (ACK signal) is output after the receipt of each eight bits of data (word address and write data). ...
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... Start condition 1 SCL SDA • Data is written to the address designated by the word address (n address). • After eight bits of data are input, the data is written to the memory cell by issuing the stop bit. 8 BR24C01A / BR24C01AF / BR24C02 / BR24C02F / WA6 1 0 Slave address ...
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... A 16-byte write is possible using this command. • The page write command arbitrarily sets the upper four bits (WA7 to WA4) of the word address. The lower four bits (WA3 to WA0) can write bytes of data with the address being incremented internally. BR24C01A / BR24C01AF / BR24C02 / BR24C02F / WA6 WA0 ...
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... Figures for the sequential read cycles.) • This command is ended by inputting HIGH to the ACK signal after D0 and raising the SDA signal (stop condition) by setting SCL to HIGH. 10 BR24C01A / BR24C01AF / BR24C02 / BR24C02F / ...
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... Figures for the sequential read cycles.) • This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop condition) by raising SCL to HIGH. BR24C01A / BR24C01AF / BR24C02 / BR24C02F / Start condition WA6 WA0 ...
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... This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop condition) using the SCL signal HIGH. • Sequential reading can also be done with a random read. 12 BR24C01A / BR24C01AF / BR24C02 / BR24C02F / ...
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... • External dimensions (Units: mm) 9.3 0 7.62 2.54 0.5 0 DIP8 BR24C01A / BR24C01AF / BR24C02 / BR24C02F / OFF -I features, which have been appended as measuring data 0 – 40 Note: All memory array data are set to “FF” status at time of shipping. ...