S3C24A0 Samsung, S3C24A0 Datasheet

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S3C24A0

Manufacturer Part Number
S3C24A0
Description
Manufacturer
Samsung
Datasheet

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BSW rv0.1-0417-N01
S3C24A0 RISC MICROPROCESSOR
PRELIMINARY PRODUCT OVERVIEW
PRODUCT OVERVIEW
S3C24A0
AN APPLICATION PROCESSOR FOR
2.5G/3G MOBILE PHONES
SOC R&D CENTER
SAMSUNG ELECTRONICS CORP.
1-1
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.

Related parts for S3C24A0

S3C24A0 Summary of contents

Page 1

... S3C24A0 RISC MICROPROCESSOR PRODUCT OVERVIEW AN APPLICATION PROCESSOR FOR 2.5G/3G MOBILE PHONES SOC R&D CENTER SAMSUNG ELECTRONICS CORP. Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. ...

Page 2

... CH33. CLOCK & POWER CH34. MECHANICAL DATA 1-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR ...

Page 3

... SDRAM controller, 2-ch UART, 4-ch DMA, 4-ch Timers, General I/O Ports, IIC-BUS interface, USB Host, SD Host & Multi-Media Card Interface, Memory Stick Interface, PLL for clock generation & etc. The S3C24A0 can be used as a most powerful Application Processor for mobiles phones. For this application, the S3C24A0 has a Modem Interface to communicate with various Modem Chips ...

Page 4

... Dead-zone generation. - Support external clock source. 1-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR ...

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... S3C24A0 RISC MICROPROCESSOR 16-bit Watchdog Timer Interrupt request or system reset at time-out. 4-ch DMA controller Support memory to memory memory, memory to IO, and Burst transfer mode to enhance the transfer rate. RTC (Real Time Clock Full clock feature: msec, sec, min, hour, day, date, week, month, year. ...

Page 6

... Wide horizontal line buffer (maximum 2048 pixel) 1-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR ...

Page 7

... S3C24A0 RISC MICROPROCESSOR - pixel resolution support for scaled image (image preview or motion video capturing) and 16M pixel for unscaled image (JPEG) - Format conversion from YCrCb 4:2:2 to 4:2:0 for codec, and to RGB 4:4:4 for preview Hardware Accelerated MPEG4 Video Encoding/Decoding AHB Interface - Realtime MPEG-4 Video Encoding & Decoding ...

Page 8

... Dual buffer - 1-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR ...

Page 9

... S3C24A0 RISC MICROPROCESSOR 1.2.8 Input Devices Keypad Interface N - Provides internal debouncing filter - 5-input, 5-output pins for key scan in/out A/D Converter and Touch Screen Interface N 8-ch multiplexed ADC - - Max. 500K samples/sec and 10-bit resolution 1.2.9 Storage Devices SD Host N Compatible with SD Memory Card Protocol version 1 Compatible with SDIO Card Protocol version 1.0 ...

Page 10

... FBGA (0.5mm pitch, 13mm x 13mm) N 1-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR ...

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... S3C24A0 RISC MICROPROCESSOR Figure Overall Block Diagram of the S3C24A0 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. PRELIMINARY PRODUCT OVERVIEW ...

Page 12

... Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR 337-Pin FBGA Pin Assignment BSW rv0.1-0417-N01 #A1 INDEX MARK ...

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... S3C24A0 RISC MICROPROCESSOR Table 1-1. 337-Pin FBGA Pin Assignments – Pin Number Order Pin Pin Name Number A01 XCIYDATA[4] A02 VSS_B A03 XCICDATA[0] A04 XCIYDATA[7] A05 XCIPCLK A06 XVVD[5] A07 XVVD[7] A08 XVVCLK A09 XVDEN A10 XCICDATA[7] A11 XRDATA[0] A12 XRDATA[5] A13 ...

Page 14

... VSS_D L20 XPDATA[14] L21 XPDATA[12] L22 XPDATA[13] L23 XPADDR[0] M01 XGPIO[0] M02 XGPIO[6] M03 VDD_B M04 XGPIO[19] BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Pin Pin Name M09 VSS_B M10 VDD_F M11 VSS M12 VSS M13 VSS M14 VDD_A M15 VSS_D M20 ...

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... S3C24A0 RISC MICROPROCESSOR Table 1-1. 337-Pin FBGA Pin Assignments – Pin Number Order Pin Pin Pin Name Number Number P20 XRCSN[0] V03 P21 XPDATA[16] V04 P22 XPADDR[7] V20 P23 XPDATA[18] V21 R01 XGTMODE[2] V22 R02 XURXD V23 R03 XGPIO[2] W01 R04 XGPIO[15] ...

Page 16

... XADCAIN[3] AC18 AC05 XADCAIN[1] AC19 AC06 XSMPLLCAP AC20 AC07 GND14 AC21 AC08 XGMONHCLK AC22 AC09 XSXTIN AC23 AC10 XUSDN[1] AC11 XMSSCLKO BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Pin Name XSDDAT[2] XSDDAT[0] XMIADR[9] XMIADR[5] XMIDATA[5] XMIDATA[3] XMIDATA[1] XMIADR[3] XPADDR[14] XPADDR[12] XPADDR[10] XPADDR[9] ...

Page 17

... S3C24A0 RISC MICROPROCESSOR Table 1-2. 337-Pin FBGA Pin Assignments Pin Name Default Function I/O Number AA7 VSSadc VSSadc AB7 VSSMpll VSSMpll AC7 VSSUpll VSSUpll AB13 VSSpadUSB VSSpadUSB AC1 VSSrtc VSSrtc AA18 VDDlogic VDDlogic J21 VDDlogic VDDlogic M14 VDDlogic VDDlogic N9 VDDlogic VDDlogic R11 VDDlogic ...

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... L/L Hi I/O H/L L/L Hi L/L Hi L/L Hi Ain I Ain I Ain I BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O I/O Cell Type State@STOP (24A0A) mode ...

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... S3C24A0 RISC MICROPROCESSOR Table 1-2. 337-Pin FBGA Pin Assignments Pin Default Name Number Function XadcAIN[3] XadcAIN[3] AC4 XadcAIN[4] XadcAIN[4] AC3 XadcAIN[5] XadcAIN[5] AA4 XadcAIN[6] XadcAIN[6] AC2 XadcAIN[7] XadcAIN[7] AB2 XadcAVREF XadcAVREF AA5 XciCDATA[0] XciCDATA[0] A3 XciCDATA[1] XciCDATA[1] C4 XciCDATA[2] XciCDATA[2] B5 XciCDATA[3] XciCDATA[3] B6 XciCDATA[4] XciCDATA[4] ...

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... Hi XgpIO[0] I/O I/H/L XgpIO[1] I/O I/H/L XgpIO[10] I/O I/H/L XgpIO[11] I/O I/H/L XgpIO[12] I/O I/H/L XgpIO[13] I/O I/H/L XgpIO[14] I/O I/H/L XgpIO[15] I/O I/H/L XgpIO[16] I/O I/H/L XgpIO[17] I/O I/H/L XgpIO[18] I/O I/H/L XgpIO[19] I/O I/H/L XgpIO[2] I/O I/H/L XgpIO[20] I/O I/H/L XgpIO[21] I/O I/H/L BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O I/O Cell Type State@STOP (24A0A) mode mode - - phis - - phis - - phis - - phis - - phisu - - phisu - - phis L phot8 phbsu100ct8s phbsu100ct8s ...

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... S3C24A0 RISC MICROPROCESSOR Table 1-2. 337-Pin FBGA Pin Assignments Pin Name Number XgpIO[22]/PWM_TOUT2/XkpROW4 H3 XgpIO[23]/PWM_TOUT3/XkpCOL0 H2 XgpIO[24]/EXTDMA_REQ0/ XkpCOL1 G1 XgpIO[25]/EXTDMA_REQ1/ XkpCOL2 J3 XgpIO[26]/EXTDMA_ACK0/ XkpCOL3 G2 XgpIO[27]/EXTDMA_ACK1/XkpCOL4 G3 XgpIO[28]/XuCTSn1/RTC_ALMINT F1 XgpIO[29]/XuRTSn1/IrDA_SDBW F2 XgpIO[3]/EINT3/PWM_TOUT1 Y7 XgpIO[30]/XuTXD1/IrDA_TXD F3 XgpIO[31]/XuRXD1/ IrDA_RXD E1 XgpIO[4]/EINT4/PWM_TOUT2 N3 XgpIO[5]/EINT5/ PWM_TOUT3 ...

Page 22

... XmiDATA[7] AB16 1-22 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR I/O state@ Reset mode I/O (Data/En/PullupEn) I/O State@SLEEP En(L)=>output mode PullupEn(L)=> ...

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... S3C24A0 RISC MICROPROCESSOR Table 1-2. 337-Pin FBGA Pin Assignments Pin Default Name Number Function XmiIRQn XmiIRQn AB18 XmiOEn XmiOEn AB14 XmiWEn XmiWEn AA14 XmsBS XmsBS AA13 XmsPI XmsPI Y14 XmsSCLKO XmsSCLKO AC11 XmsSDIO XmsSDIO Y13 XpADDR[0] XpADDR[0] L23 XpADDR[1] XpADDR[1] M22 XpADDR[10] ...

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... I/O I/H I/O I/H I/O I/H I/O I/H I/O I/H I/O I/H I/O I/H I/O I/H BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O Cell Type State@STOP (24A0A) mode H phot12sm H phot12sm phbsu100ct12s - m phbsu100ct12s - m phbsu100ct12s - m phbsu100ct12s - m phbsu100ct12s - m phbsu100ct12s ...

Page 25

... S3C24A0 RISC MICROPROCESSOR Table 1-2. 337-Pin FBGA Pin Assignments Pin Name Default Function I/O Number XpDATA[28] XpDATA[28] AA23 XpDATA[29] XpDATA[29] V21 XpDATA[3] XpDATA[3] F23 XpDATA[30] XpDATA[30] AB22 XpDATA[31] XpDATA[31] AA22 XpDATA[4] XpDATA[4] H20 XpDATA[5] XpDATA[5] G21 XpDATA[6] XpDATA[6] F22 XpDATA[7] XpDATA[7] G23 XpDATA[8] ...

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... XrCSn[0] P20 1-26 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR I/O state@ Reset mode I/O (Data/En/PullupEn) State@SLEEP En(L)=>output mode PullupEn(L)=> ...

Page 27

... S3C24A0 RISC MICROPROCESSOR Table 1-2. 337-Pin FBGA Pin Assignments Pin Default Name Number Function XrCSn[1] XrCSn[1] C17 XrCSn[2] XrCSn[2] B17 XrDATA[0] XrDATA[0] A11 XrDATA[1] XrDATA[1] B11 XrDATA[10] XrDATA[10] C18 XrDATA[11] XrDATA[11] K20 XrDATA[12] XrDATA[12] C19 XrDATA[13] XrDATA[13] A17 XrDATA[14] XrDATA[14] B18 XrDATA[15] ...

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... I I H BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O Cell Type State@STOP (24A0A) mode - rtc_osc - rtc_osc - phis H phot8 - phbsu100ct12sm - phbsu100ct12sm - phbsu100ct12sm - phbsu100ct12sm - phis - phob1_abb - phtbsu100ct8sm H ...

Page 29

... S3C24A0 RISC MICROPROCESSOR Table 1-2. 337-Pin FBGA Pin Assignments Pin Default Name Number Function XusDN[1] XusDN[1] AC10 XusDP[0] XusDP[0] AA11 XusDP[1] XusDP[1] AB10 XuTXD XuTXD U3 XvDEN XvDEN A9 XvHSYNC XvHSYNC C9 XvVCLK XvVCLK A8 XvVD[6] XvVD[6] J4 XvVD[7] XvVD[7] B7 XvVD[8] XvVD[8] K4 XvVD[9] XvVD[9] D7 XvVD[10] XvVD[10] D8 XvVD[11] ...

Page 30

... I/O State@SLEEP En(L)=>output mode PullupEn(L)=>PullUp L/L Hi Descriptions BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR I/O Cell Type State@STOP (24A0A) mode Pre phot12sm Pre phot12sm Pre phot12sm Pre phot12sm L phot8 ...

Page 31

... S3C24A0 RISC MICROPROCESSOR phbst12sm Bi-directional pad, LVCMOS schmitt-trigger, pull-up resistor with control, tri-state, Io=12mA pbusb1 USB pad Rtc-osc rtc X-tal phob1-abb Analog pad phiar10_abb Analog input pad with 10-ohm resistor phia_abb Analog input pad phsoscm26_shmitt Oscillator cell with enable and feedback resistor ...

Page 32

... SDRAM bank 0 Data bus 1-32 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR Description Description BSW rv0.1-0417-N01 ...

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... S3C24A0 RISC MICROPROCESSOR 1.3.1.2 Serial Communication UART N Signal I/O XuCLK I UART 0 clock signal XuRXD0 I UART 0 receives data input XuCTSn0 I UART 0 clear to send input signal XuTXD0 O UART 0 transmits data output XuRTSn0 O UART 0 request to send output signal IIC Bus N Signal I/O X2cSDA IO IIC-bus data X2cSCL IO IIC-bus clock ...

Page 34

... Software Reset to the Camera processor 1-34 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR Description Description Description Description Description BSW rv0 ...

Page 35

... S3C24A0 RISC MICROPROCESSOR 1.3.1.5 Display Control TFT LCD Display Interface N Signal I/O XvVD[17:0] O LCD pixel data output ports XvVCLK O Pixel clock signal XvVSYNC O Vertical synchronous signal XvHSYNC O Horizontal synchronous signal XvDEN O Data enable signal 1.3.1.6 Input Devices Analog-to-Digital Converter and Touch Screen Interface ...

Page 36

... I/O XsRESETn I XsRESETn suspends any operation in progress and places S3C24A0 into a known reset state. For a reset, XsRESETn must be held to L level for at least 4 External clock after the processor power has been stabilized. System Warm Reset. Reset the whole system while preserves the SDRAM contents ...

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... Signal I/O XxVDDlogic P Core logic VDD (1.2V) for internal logic XxVDDalive P S3C24A0 reset block and port status register VDD (1.2V). It should be always supplied whether in normal mode or in Stop and Sleep mode. XxVDDarm P Core logic VDD (1.2V) for CPU XxVDDMpll P S3C24A0 MPLL analog and digital VDD (1.2 V). ...

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... PRELIMINARY PRODUCT OVERVIEW VSS N Signal I/O Core logic VSS for internal logic VSS for S3C24A0 reset block and port status register VSS P Core logic VSS for CPU S3C24A0 I/O port VSS XxVSSpadSDRAM P S3C24A0 SDRAM memory IO VSS XxVSSpadFlash P S3C24A0 Flash memory IO VSS XxVSSpadUSB P S3C24A0 USB IO VSS ...

Page 39

... S3C24A0 RISC MICROPROCESSOR 1.4 Address MAP 1.4.1 Address Space Assignment Overview SROM_BW[ TMODE[2:0] = 000 0xFFFF_FFFF Reserved 0x5000_0000 AHB_I SFRs 0x4800_0000 APB SFRs 0x4400_0000 AHB_S SFRs 0x4000_0000 Reserved 0x2000_0000 SDRAM (XpCSn1) 0x1800_0000 SDRAM (XpCSn0) 0x1000_0000 Stepping stone (4KB, No CS) 0x0c00_0000 SROM (XrCSn2) 0x0800_0000 SROM ...

Page 40

... APB 1-40 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR Device Note SystemCtrl Reserved INTC Reserved DMA 0 ...

Page 41

... S3C24A0 RISC MICROPROCESSOR AHB_I (the AHB Bus for the Image Subsystem) Devices: Base = 0x4000_0000 N Offset (Hex) Size (MB) Group 0x80_0_0000 4 AHB_I 0x84_0_0000 4 AHB_I 0x88_0_0000 4 AHB_I 0x8C_0_0000 4 AHB_I 0x90_0_0000 4 AHB_I 0x94_0_0000 12 AHB_I 0xA0_0_0000 1 AHB_I 0xA1_0_0000 1 AHB_I 0xA2_0_0000 4 AHB_I 0xA4_0_0000 10 AHB_I 0xB0_0_0000 16 AHB_I 0xC0_0_0000 ...

Page 42

... SDRAM Refresh Control Acc. Read/ Unit Write W R/W Priority Control for SROMC/NFLASHC Priority Control for SDRAMC Acc. Read/ Unit Write W R/W Interrupt Request Status Interrupt Mode Control Interrupt Mask Control IRQ Priority Control BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Function Function Function Function ...

Page 43

... S3C24A0 RISC MICROPROCESSOR INTPND 0x020_0010 INTOFFSET 0x020_0014 SUBSRCPND 0x020_0018 INTSUBMSK 0x020_001C VECINTMOD 0x020_0020 VECADDR 0x020_0024 NVECADDR 0x020_0028 VAR 0x020_002C Timer with PWM (Pulse Width Modulation) N Register Offset Name TCFG0 0x400_0000 TCFG1 0x400_0004 TCON 0x400_0008 TCNTB0 0x400_000C TCMPB0 0x400_0010 TCNTO0 0x400_0014 TCNTB1 ...

Page 44

... DMA 2 Current Source DMA 2 Current Destination R/W DMA 2 Mask Trigger W R/W DMA 3 Initial Source DMA 3 Initial Source Control DMA 3 Initial Destination DMA 3 Initial Destination Control DMA 3 Control R DMA 3 Count DMA 3 Current Source DMA 3 Current Destination R/W DMA 3 Mask Trigger BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Function ...

Page 45

... S3C24A0 RISC MICROPROCESSOR RTC (Real Time Clock) N Register Offset Name RTCCON 0x420_0040 TICINT 0x420_0044 RTCALM 0x420_0050 ALMSEC 0x420_0054 ALMMIN 0x420_0058 ALMHOUR 0x420_005C ALMDATE 0x420_0060 ALMMON 0x420_0064 ALMYEAR 0x420_0068 RTCRST 0x420_006C BCDSEC 0x420_0070 BCDMIN 0x420_0074 BCDHOUR 0x420_0078 BCDDATE 0x420_007C BCDDAY 0x420_0080 BCDMON ...

Page 46

... Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR UART 1 Control UART 1 FIFO Control UART 1 Modem Control R ...

Page 47

... S3C24A0 RISC MICROPROCESSOR SPCON1 0x450_0020 SPSTA1 0x450_0024 SPPIN1 0x450_0028 SPPRE1 0x450_002C SPTDAT1 0x450_0030 SPRDAT1 0x450_0034 AC97 Audio-CODEC Interface N Register Offset Name AC_GLBCTRL 0x500_0000 AC_GLBSTAT 0x500_0004 AC_CODEC_CMD 0x500_0008 AC_CODEC_STAT 0x500_000C AC_PCM_ADDR 0x500_0010 AC_MICADDR 0x500_0014 AC_PCMDATA 0x500_0018 AC_MICDATA 0x500_001C USB Host N Register Name ...

Page 48

... EP1_DMA_TTC_L 0x4A0_020C 1-48 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR Root Hub Group Acc. Read/ Function Unit ...

Page 49

... S3C24A0 RISC MICROPROCESSOR EP1_DMA_TTC_M 0x4A0_0210 EP1_DMA_TTC_H 0x4A0_0214 EP2_DMA_CON 0x4A0_0218 EP2_DMA_UNIT 0x4A0_021C EP2_DMA_FIFO 0x4A0_0220 EP2_DMA_TTC_L 0x4A0_0224 EP2_DMA_TTC_M 0x4A0_0228 EP2_DMA_TTC_H 0x4A0_022C EP3_DMA_CON 0x4A0_0240 EP3_DMA_UNIT 0x4A0_0244 EP3_DMA_FIFO 0x4A0_0248 EP3_DMA_TTC_L 0x4A0_024C EP3_DMA_TTC_M 0x4A0_0250 EP3_DMA_TTC_H 0x4A0_0254 EP4_DMA_CON 0x4A0_0258 EP4_DMA_UNIT 0x4A0_025C EP4_DMA_FIFO 0x4A0_0260 EP4_DMA_TTC_L 0x4A0_0264 EP4_DMA_TTC_M 0x4A0_0268 ...

Page 50

... Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR IrDA Transmit Frame-Length Register High IrDA Receive Frame-Length Register Low IrDA Receive Frame-Length Register High Acc ...

Page 51

... S3C24A0 RISC MICROPROCESSOR PERIPU_SLEEP 0x480_0064 RSTCNT 0x480_0068 GPRAM0~15 0x480_0080 ~0x480_00BC 1.4.3.5 Image/Video Processing Camera Interface N Register Offset Name CISRCFMT 0x800_0000 CIWDOFST 0x800_0004 CIGCTRL 0x800_0008 CICOYSA1 0x800_0018 CICOYSA2 0x800_001C CICOYSA3 0x800_0020 CICOYSA4 0x800_0024 CICOCBSA1 0x800_0028 CICOCBSA2 0x800_002C CICOCBSA3 0x800_0030 CICOCBSA4 0x800_0034 CICOCRSA1 0x800_0038 ...

Page 52

... DMA End address for RGB component Offset of Y component for fetching source image Offset of Cb component for fetching source image Offset of Cr component for fetching source image Offset of RGB component for restoring destination image BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Function ...

Page 53

... S3C24A0 RISC MICROPROCESSOR ME Register Offset Name ME_CFSA 0x880_0000 ME_PFSA 0x880_0004 ME_MVSA 0x880_0008 ME_CMND 0x880_000C ME_STAT_SWR 0x880_0010 ME_CNFG 0x880_0014 ME_IMGFMT 0x880_0018 MC N Register Offset Name MC_PFYSA_ENC 0x8C0_0000 MC_CFYSA_ENC 0x8C0_0004 MC_PFYSA_DEC 0x8C0_0008 MC_CFYSA_DEC 0x8C0_000C MC_PFCbSA_ENC 0x8C0_0010 MC_PFCrSA_ENC 0x8C0_0014 MC_CFCbSA_ENC 0x8C0_0018 MC_CFCrSA_ENC 0x8C0_001C MC_PFCbSA_DEC ...

Page 54

... Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR Motion Vector Start Address Register for the Decoder Command Register Status & ...

Page 55

... S3C24A0 RISC MICROPROCESSOR VLC_CON3 0x940_0018 VLC_CON4 0x940_001C VLD_CON1 0x940_0020 VLD_CON2 0x940_0024 VLD_CON3 0x940_0028 VLX_OUT1 0x940_002C VLX_OUT2 0x940_0030 1.4.3.6 Display Control TFT LCD Controller N Register Offset LCDCON1 0xA00_0000 LCDCON2 0xA00_0004 LCDTCON1 0xA00_0008 LCDTCON2 0xA00_000C LCDTCON3 0xA00_0010 LCDOSD1 0xA00_0014 LCDOSD2 0xA00_0018 LCDOSD3 0xA00_001C LCDSADDRB1 ...

Page 56

... ADC Conversion Data Register Y Acc. Read/ Unit Write W R/W SDI Control SDI Buad Rate Prescaler SDI Command Argument SDI Command Control R/(C) SDI Command Status R SDI Response SDI Response SDI Response SDI Response R/W SDI Data / Busy Timer BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Function Function Function ...

Page 57

... S3C24A0 RISC MICROPROCESSOR SDIBSIZE 0x600_0028 SDIDCON 0x600_002C SDIDCNT 0x600_0030 SDIDSTA 0x600_0034 SDIFSTA 0x600_0038 SDIIMSK 0x600_003C SDIDAT0 0x600_0040 SDIDAT1 0x600_0044 SDIDAT2 0x600_0048 SDIDAT3 0x600_004C Memory Stick N Register Name Offset MSPRE 0x610_0000 MSFINTCON 0x610_0004 TP_CMD 0x610_8000 CTRL_STA 0x610_8004 DAT_FIFO 0x610_8008 INTCTRL_STA 0x610_800C INS_CON ...

Page 58

... PRELIMINARY PRODUCT OVERVIEW IMPORTANT NOTES ABOUT S3C24A0 SPECIAL REGISTERS 1. The special registers have to be accessed by the recommended access unit. 2. All registers except ADC registers, RTC registers and UART registers must be read/written in word unit (32bit) at little/big endian very important that the ADC registers, RTC registers and UART registers be read/written by the specified access unit and the specified address ...

Page 59

... S3C24A0 RISC MICROPROCESSOR SROM CONTROLLER(Preliminary) OVERVIEW S3C24A0 support external 16-bit bus for NAND Flash/ NOR Flash/ PROM/ SRAM external memory. It’s not shared with SDRAM bus and support Bank for one controller. From now on, we call this controller as SROM Controller. ...

Page 60

... Figure 2-2 SROM Controller Block Diagram 2-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR SFR SROM I/F SINGAL GENERATO N CONTROL & ...

Page 61

... S3C24A0 RISC MICROPROCESSOR FUNCTION DESCRIPTION SROM Controller support SROM interface for Bank0 to Bank2. In case of NAND boot, SROM controller can’t control Bank0 because of its mastership is on NAND Flash Controller. In case of ROM boot mentioned before possible that Bank2’s master is NAND Flash Controller by setting of users. ...

Page 62

... Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Tacc=4 Tcos Figure 2-4 XrWAITn pin operation BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Delayed Sampling XrWAITn ...

Page 63

... S3C24A0 RISC MICROPROCESSOR PROGRAMMABLE ACCESS CYCLE WRITE TO READ WAVEFORM HCLK XrADDR [25:0] XrCSn Tacs [2:0] Tcos XrOEn XrWEn XrnWBE [1:0] XrDATA [15:0] (R) XrDATA [15:0] (W) Tacs = 1 cycle Tcos = 1 cycle Tacc = 2 cycles Figure 2-4 Programmable access cycle Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. ...

Page 64

... Specifications and information herein are subject to change without notice. Description SROM Bus width & wait control Description 1 : WAIT enable 1 : 16-bit 1 : WAIT enable 1 : 16-bit 1 : WAIT enable 1 : 16-bit BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x000x Initial State 0x00 0x00 ...

Page 65

... S3C24A0 RISC MICROPROCESSOR SROM BANK CONTROL REGISTER (SROM_BC : XrCSn0 ~ XrCSn2) Register Address R/W SROM_BC0 0x40C20004 R/W SROM_BC1 0x40C20008 R/W SROM_BC2 0x40C2000C R/W SROM_BCn Bit Tacs [15:14] [13:12] Tcos Reserved [11] Tacc [10:8] [7:6] Tcoh Tcah [5:4] Reserved [3:0] Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. ...

Page 66

... S3C24A0 RISC MICROPROCESSOR 3 SDRAM CONTROLLER (Preliminary) OVERVIEW The S3C24A0 SDRAM Controller has the following features: SDRAM N  Supports 16-bit or 32-bit data bus Supports 2 banks: XpCSN[1: 16-bit Refresh Timer  Self Refresh Mode  Programmable CAS Latency  Provide Write buffer (4word size x2)  Provide long burst(INCR8,16 & WRAP8,16) transfer ...

Page 67

... SELF REFRESH The S3C24A0 provides the auto refresh and self refresh command to sustain the contents of SDRAM. The auto refresh is issued to SDRAM periodically when refresh timer is expired. The self refresh is entered and exited by request of on-chip power manager. 3-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available ...

Page 68

... S3C24A0 RISC MICROPROCESSOR SDRAM INITIALIZATION SEQUENCE On power-on reset, software must initialize the memory controller and each of the SDRAM connected to the controller. Refer to the SDRAM data sheet for the start up procedure, and examples sequence is given below: 1. Wait 200us to allow SDRAM power and clock stabilize. ...

Page 69

... XpDATA14 XpADDR14 BA1 XpDATA15 XpDQM2 LDQM XpDQM3 UDQM XpCSN0 XpRASn XpCKE SCKE XpCASn XpSCLK SCLK nWE XpWEn BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR DQ0 XpDATA16 DQ1 XpDATA17 DQ2 XpDATA18 DQ3 XpDATA19 DQ4 XpDATA20 DQ5 XpDATA21 DQ6 XpDATA22 DQ7 XpDATA23 DQ8 XpDATA24 ...

Page 70

... S3C24A0 RISC MICROPROCESSOR SCLK SCKE ...

Page 71

... C TCSR bit fields are only for mobile SDRAM. 001 = 2banks 100 = Reserved 111 = Reserved PASR bit fields are only for mobile SDRAM 2-clock 10 = 3-clock BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x9f0c Initial State 00 b 00b 010 = 00b 101 = 0 ...

Page 72

... S3C24A0 RISC MICROPROCESSOR Row pre-charge time Trp [9: 1-clock SDRAM base component density of bank 16Mbit DENSITY1 [7: 128Mbit SDRAM base component density of bank 0 DENSITY0 [5: 16Mbit 10 = 128Mbit CAS latency CL [3: Reserved 01 = 1-clock Auto pre-charge control AP [ enable auto pre-charge Determine data bus width ...

Page 73

... Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Description -6 6 REFCYC = 15 1029 NOTES BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Initial State 100000b ...

Page 74

... NAND flash and execute the main code on an SDRAM. S3C24A0 boot code can be executed on an external NAND flash memory. In order to support NAND flash boot loader, the S3C24A0 is equipped with an internal SRAM buffer called ‘Steppingstone’. When booting, the first 4 KBytes of the NAND flash memory will be loaded into Steppingstone and the boot code loaded into Steppingstone will be executed ...

Page 75

... NAND FLASH CONTROLLER PIN CONFIGURATION Here is a configuration of NAND Flash Controller of S3C24A0. Users can select configuration of NAND Flash Memory according to the table below. There is some differences between conventional NAND Flash Memory and New Advance Flash Memory. So users have to select the configuration properly. ...

Page 76

... S3C24A0 RISC MICROPROCESSOR BLOCK DIAGRAM AHB Slave I/F Figure 4-1 NAND Flash Controller Block Diagram BOOT LOADER FUNCTION When power-on or system reset is occurred, the NAND Flash controller loads automatically the 4-KBytes boot loader codes. After loading the boot loader codes, the boot loader code is executed on the steppingstone. ...

Page 77

... Figure 4-4 Auto Mode Timing Diagram (TACLS = 1, TWRPH0 = 0, TWRPH1 = 0) 4-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR AUTO LOAD/STORE MODE NAND FLASH CONTROLLER S/W MODE ...

Page 78

... S3C24A0 RISC MICROPROCESSOR AUTO LOAD MODE Auto load function supports automatically load the page(s) of the NAND Flash Memory to steppingstone up to 4KBytes. You can specify the load start address of the steppingstone and how many pages are loaded. AUTO LOAD PROGRAMMING GUIDE 1) Set command (read command), address (of the page you read), and configuration and control value. ...

Page 79

... Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. TWRPH0 TWRPH0 TWRPH1 2nd DATA N-1th DATA BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR TWRPH0 TWRPH1 Nth DATA ...

Page 80

... S3C24A0 RISC MICROPROCESSOR STEPPING STONE (4K-Byte SRAM) The NAND Flash controller uses Steppingstone as the buffer in the auto load and store mode. Also you can use this area for another purpose, if you don’t use auto load and store function. For the best performance, if you need to move the content of the NAND Flash Memory to SDRAM, We recommend that you use DMA burst transfer(source address : Steppingstone, destination address : SDRAM) ...

Page 81

... Figure 4-7 8-bit NAND Flash Memory Interface 4-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR R/ B I/O7 DATA[7] RE I/O6 ...

Page 82

... S3C24A0 RISC MICROPROCESSOR RnB0 R/ B I/O7 nFRE RE I/O6 nFCE CE I/O5 CLE CLE I/O4 ALE ALE I/O3 nFWE WE I/O2 I/O1 I/O0 Figure 4-8 Two 8-bit NAND Flash Memory Interface RnB0 nFRE nFCE CLE ALE nFWE Figure 4-9 16-bit NAND Flash Memory Interface Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. ...

Page 83

... RnB1) Auto Load Page Size of NAND Flash Memory 0 : 256/1K Bytes 512/2K Bytes, Address Cycle of NAND Flash Memory 0 : 3/4 address cycle 1 : 4/5 address cycle BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x00XF100X Initial State 00 H/W Set 0x3F 0 001 ...

Page 84

... S3C24A0 RISC MICROPROCESSOR CONTROL REGISTER Register Address R/W NFCONT 0x40C00004 R/W NFCONT Bit LdStrAddr [27:16] EnbIllegalAccINT [15] EnbLoadINT [14] EnbStoreINT [13] EnbRnBINT [12] RnB_TransMode [11] SpareECCLock [10] MainECCLock [9] InitECC [8] Reg_nCE [7] LoadPageSize [6:4] Lock-tight [3] Lock [2] Mode [1:0] Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. ...

Page 85

... NAND Flash read/program data value for I/O[15:8] NAND Flash read/program data value for I/O[7:0] In case of write: Programming data In case of read: Reading data. These values are only used in Software mode. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x00 Initial State - 0x00 Reset Value ...

Page 86

... S3C24A0 RISC MICROPROCESSOR MAIN DATA AREA ECC0 REGISTER Register Address NFMECCDATA0 0x40C00014 NFMECCDATA0 Bit ECCData0_1 [15:8] ECCData0_0 [7:0] MAIN DATA AREA ECC1 REGISTER Register Address NFMECCDATA1 0x40C00018 NFMECCDATA1 Bit ECCData1_1 [15:8] ECCData1_0 [7:0] MAIN DATA AREA ECC2 REGISTER Register Address R/W NFMECCDATA2 0x40C0001C R/W NAND Flash ECC register for main data read ...

Page 87

... ECC for I/O[15: ECC for I/O[ 7:0] NOTE: In Software mode, Read this register when you nd need to read 2 ECC value from NAND flash memory BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x00000000 Initial State 0x00 0x00 Reset Value 0x00000000 Initial State 0x00 0x00 ...

Page 88

... S3C24A0 RISC MICROPROCESSOR NF_CONF STATUS REGISTER Register Address R/W NFSTAT 0x40C0002C R/W NAND Flash operation status register NFSTAT Bit IllegalAccess [16] AutoLoadDone [15] AutoStoreDone [14] RnB_TransDetect [13] Flash_nCE [12] Flash_RnB1 [11] Flash_RnB0 [10] STON_A2 [9:0] Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. ...

Page 89

... No Error 01 : 1-bit error(correctable Multiple error 11 : ECC area error Indicates whether main data area bit fail error occurred Error 01 : 1-bit error(correctable Multiple error 11 : ECC area error BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x00000000 Initial State 00 000 0x00 000 00 00 ...

Page 90

... S3C24A0 RISC MICROPROCESSOR MAIN DATA AREA ECC0 STATUS REGISTER Register Address R/W NFMECC0 0x40C00038 R NFMECC0 Bit MECC0_3 [31:24] MECC0_2 [23:16] MECC0_1 [15:8] MECC0_0 [7:0] MAIN DATA AREA ECC1 STATUS REGISTER Register Address R/W NFMECC1 0x40C0003C R NFMECC1 Bit MECC1_3 [31:24] MECC1_2 [23:16] MECC1_1 [15:8] MECC1_0 [7:0] SPARE AREA ECC STATUS REGISTER Register ...

Page 91

... NAND Flash programmable end block address Description rd block address of the block erase operation nd block address of the block erase operation st block address of the block erase operation BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x000000 Initial State 0x00 0x00 0x00 . Reset Value ...

Page 92

... S3C24A0 RISC MICROPROCESSOR Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. NAND FLASH CONTROLLER NOTES BSW rv0.1-0417-N01 4-19 ...

Page 93

... SRAM, Flash Memory, ROM etc) from different AHB bus (one is for system and the other is for image) at the same time. S3C24A0 have two MATRIX cores because it has two memory ports, and each MATRIX can select the priority between rotation type and fixed type. ...

Page 94

... Fixed priority 5-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR Description Description 1: Rotating priority Description Description 1: Rotating priority BSW rv0 ...

Page 95

... INTERRUPT CONTROLLER OVERVIEW The interrupt controller in S3C24A0 receives the requests for interrupt services from 61 interrupt sources. These interrupt sources are provided by internal peripherals such as a DMA controller, UART and IIC, etc. Among these interrupt sources, the UART0 and UART1 error interrupts are 'OR'ed to the interrupt controller. And, two interrupts from a Display/Post processor , two interrupts from Timer3/Timer4, and four interrupts from DMA controller are individually ‘ ...

Page 96

... INTERRUPT CONTROLLER INTERRUPT PENDING REGISTER S3C24A0 has two interrupt pending resisters. The one is source pending register(SRCPND), the other is interrupt pending register(INTPND). These pending registers indicate whether or not an interrupt request is pending. When the interrupt sources request interrupt service the corresponding bits of SRCPND register are set the same time the only one bit of INTPND register is set to 1 automatically after arbitration process ...

Page 97

... S3C24A0 RISC MICROPROCESSOR INTERRUPT SOURCES Interrupt controller supports 61 interrupt sources as shown in below table. Among the 32 interrupt sources, each interrupt source corresponding to INT_ADC, INT_PCM_MSTICK, INT_AC97_NFLASH, INT_DMA_PBUS, INT_DMA_GBUS, INT_DMA_MBUS, INT_UART0, INT_UART1, and INT_CAMPRO is an ‘OR’ed interrupt which combines multiple subinterrupt sources connected to the corresponding interrupt sources, and provides a single interrupt source to interrupt controller ...

Page 98

... ARBITER6 ARM IRQ 6-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR REQ1/EINT0_2 REQ2/EINT3_6 ARBITER0 REQ3/EINT7_10 REQ4/EINT11_14 REQ1/EINT15_18 ...

Page 99

... If REQ4 is serviced, ARB_SEL bits are changed to 00b. VECTORED INTERRUPT MODE (ONLY FOR IRQ) S3C24A0 has a vectored interrupt mode, to reduce the interrupt latency time. If ARM926EJ receives the IRQ interrupt request from the interrupt controller, it executes an instruction at 0x00000018. The LDR instruction which loads to PC the address written in Vector Address Register, one of special function registers in Interrupt controller, is located at 0x00000018 ...

Page 100

... EINT7_10 EINT11_14 EINT15_18 INT_TICK INT_DCTQ INT_MC INT_ME INT_KEYPAD INT_TIMER0 INT_TIMER1 INT_TIMER2 INT_TIMER3,4 INT_LCD_POST INT_WDT_BATFLT INT_UART0 INT_MODEM INT_DMA BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR 0x0000_0020 0x0000_0024 0x0000_0028 0x0000_002c 0x0000_0030 0x0000_0034 0x0000_0038 0x0000_003c 0x0000_0040 0x0000_0044 0x0000_0048 0x0000_004c 0x0000_0050 0x0000_0054 0x0000_0058 0x0000_005c 0x0000_0060 0x0000_0064 ...

Page 101

... S3C24A0 RISC MICROPROCESSOR INT_ADC_PENUP_DOWN SPECIAL FUNCTION REGISTERS There are five control registers in the interrupt controller: source pending register, interrupt mode register, mask register, priority register, and interrupt pending register. All the interrupt requests from the interrupt sources are first registered in the source pending register. They are divided into two groups based on the interrupt mode register, i ...

Page 102

... Specifications and information herein are subject to change without notice. Description Indicates the interrupt request status The interrupt has not been requested 1 = The interrupt source has asserted the interrupt request BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x00000000 ...

Page 103

... S3C24A0 RISC MICROPROCESSOR SRCPND Bit [31] INT_ADC_PENUP_DOW N [30] INT_RTC [29] INT_VLX_SPI1 [28] INT_IrDA_MSTICK [27] INT_IIC [26] INT_USBH [25] INT_USBD [24] INT_AC97_NFLASH [23] INT_UART1 [22] INT_SPI0 [21] INT_SDI [20] INT_DMA [19] INT_MODEM [18] INT_CAMIF_PREVIEW [17] INT_UART0 [16] INT_WDT_BATFLT [15] INT_CAMIF_CODEC [14] INT_LCD_POST [13] INT_TIMER3,4 [12] INT_TIMER2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. ...

Page 104

... EINT0_2 6-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR 0 = Not requested Requested 0 = Not requested Requested 0 = Not requested, ...

Page 105

... S3C24A0 RISC MICROPROCESSOR INTERRUPT MODE REGISTER (INTMOD) This register is composed of 32 bits each of which is related to an interrupt source specific bit is set to 1, the corresponding interrupt is processed in the FIQ (fast interrupt) mode. Otherwise processed in the IRQ mode (normal interrupt). Note that at most only one interrupt source can be serviced in the FIQ mode in the interrupt controller. (You should use the FIQ mode only for the urgent interrupt ...

Page 106

... EINT3_6 [0] EINT0_2 6-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR 0 = IRQ FIQ 0 = IRQ FIQ 0 = IRQ FIQ 0 = IRQ, ...

Page 107

... S3C24A0 RISC MICROPROCESSOR INTERRUPT MASK REGISTER (INTMSK) Each of the 32 bits in the interrupt mask register is related to an interrupt source. If you set a specific bit to 1, the interrupt request from the corresponding interrupt source is not serviced by the CPU. (Note that even in such a case, the corresponding bit of SRCPND register is set to 1). If the mask bit is 0, the interrupt request can be serviced ...

Page 108

... EINT0_2 6-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR 0 = Service available Masked 0 = Service available Masked 0 = Service available, ...

Page 109

... S3C24A0 RISC MICROPROCESSOR PRIORITY REGISTER (PRIORITY) Register Address R/W PRIORITY 0X4020000C R/W PRIORITY Bit Description ARB_SEL6 [20:19] Arbiter 6 group priority order set 00 = REQ 0-1-2-3-4 REQ 0-3-4-1-2-5 ARB_SEL5 [18:17] Arbiter 5 group priority order set 00 = REQ 1-2-3 REQ 3-4-1-2 ARB_SEL4 [16:15] Arbiter 4 group priority order set 00 = REQ 0-1-2-3-4 REQ 0-3-4-1-2-5 ARB_SEL3 [14:13] Arbiter 3 group priority order set ...

Page 110

... Priority does not rotate, 6-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR Priority rotate enable Priority rotate enable ...

Page 111

... S3C24A0 RISC MICROPROCESSOR INTERRUPT PENDING REGISTER (INTIPND) Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request is the highest priority one that is unmasked and waits for the interrupt to be serviced. Since INTPND is located after the priority logic, only one bit can be set most, and that is the very interrupt request generating IRQ to CPU. In interrupt service routine for IRQ, you can read this register to determine the interrupt source to be serviced among 32 sources ...

Page 112

... EINT0_2 6-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR 0 = Not requested Requested 0 = Not requested Requested 0 = Not requested, ...

Page 113

... S3C24A0 RISC MICROPROCESSOR INTERRUPT OFFSET REGISTER (INTOFFSET) The number in the interrupt offset register shows which interrupt request of IRQ mode is in the INTPND register. This bit can be cleared automatically by clearing SRCPND and INTPND. Register Address INTOFFSET 0X40200014 INT Source The OFFSET value ...

Page 114

... Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR R/W Description R/W Indicates the interrupt request status The interrupt has not been requested ...

Page 115

... S3C24A0 RISC MICROPROCESSOR INT_TIMER4 [12] INT_TIMER3 [11] Reserved [10:8] INT_MSTICK [7] INT_IrDA [6] INT_ERR1 [5] INT_TXD1 [4] INT_RXD1 [3] INT_ERR0 [2] INT_TXD0 [1] INT_RXD0 [0] Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. ...

Page 116

... Service available Masked 0 = Service available Masked 0 = Service available Masked 0 = Service available Masked 0 = Service available Masked 0 = Service available Masked 0 = Service available Masked 0 = Service available Masked BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x1fffffff Initial State - ...

Page 117

... S3C24A0 RISC MICROPROCESSOR INT_WDT [13] INT_TIMER4 [12] INT_TIMER3 [11] Reserved [10:8] INT_MSTICK [7] INT_IrDA [6] INT_ERR1 [5] INT_TXD1 [4] INT_RXD1 [3] INT_ERR0 [2] INT_TXD0 [1] INT_RXD0 [0] Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. ...

Page 118

... Nonvectored interrupt mode 1 = Vectored interrupt mode Description - 0 = vectored interrupt mode disable 1 = vectored interrupt mode enable R/W Description R Provides the interrupt vector address Description Provides the interrupt vector address BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x00000000 Initial State - 0 Reset Value - Initial State - ...

Page 119

... S3C24A0 RISC MOCROPROCESSOR PWM TIMER(Preliminary) OVERVIEW The S3C24A0 has five 16-bit timers. The timer have PWM function(Pulse Width Modulation). Timer 4 has an internal timer only with no output pins. Timer 0 has a dead-zone generator, which is used with a large current device. Timer 0 and timer 1 share an 8-bit prescaler, timers 2, 3 and 4 share the other 8-bit prescaler. Each timer has a clock-divider which has 4 different divided signals (1/2, 1/4, 1/8, 1/16) ...

Page 120

... Specifications and information herein are subject to change without notice. TCMPB0 TCNTB0 Control Logic0 TCMPB1 TCNTB1 Control Logic1 TCMPB2 TCNTB2 Control Logic2 TCMPB3 TCNTB3 Control Logic3 TCNTB4 Control Logic4 BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR TOUT0 Dead Zone Generator Dead Zone TOUT1 Dead Zone TOUT2 TOUT3 No Pin ...

Page 121

... S3C24A0 RISC MOCROPROCESSOR PRESCALER & DIVIDER An 8-bit prescaler and 4-bit divider make the following output frequencies: 4-bit divider settings minimum resolution (prescaler = 0) 1/2 ( PCLK = 55 MHz ) 0.0363 us (27.5000 MHz ) 1/4 ( PCLK = 55 MHz ) 0.0727 us (13.7500 MHz ) 1/8 ( PCLK = 55 MHz ) 0.1454us ( 6.8750 MHz ) 1/16 ( PCLK = 55 MHz ) 0.2909 us ( 3.4375MHz ) ...

Page 122

... PWM TIMER AUTO-RELOAD & DOUBLE BUFFERING S3C24A0 PWM Timers have a double buffering feature, which can change the reload value for the next timer operation without stopping the current timer operation. So, although the new timer value is set, a current timer operation is completed successfully. ...

Page 123

... S3C24A0 RISC MOCROPROCESSOR TIMER INITIALIZation using Manual UpdatE BIT and Inverter BIt Because an auto-reload operation of the timer occurs when the down counter reaches starting value of the TCNTn has to be defined by the user at first. In this case, the starting value has to be loaded by the manual update bit. The sequence of starting a timer is as follows ...

Page 124

... Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice 110 BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR ...

Page 125

... S3C24A0 RISC MOCROPROCESSOR PWM (Pulse Width Modulation) 60 Write TCMPBn = 60 Write TCMPBn = 50 PWM feature can be implemented by using the TCMPBn. PWM frequency is determined by TCNTBn. A PWM value is determined by TCMPBn in Figure 7-5. For a higher PWM value, decrease the TCMPBn value. For a lower PWM value, increase the TCMPBn value output inverter is enabled, the increment/decrement may be reversed ...

Page 126

... Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR Period 1 Period 2 Figure 7-6. Inverter On/Off BSW rv0.1-0417-N01 ...

Page 127

... S3C24A0 RISC MOCROPROCESSOR DEAD ZONE GENERATOR The dead zone is for the PWM control in a power device. This feature is used to insert the time gap between a turn-off of a switching device and a turn on of another switching device. This time gap prohibits the two switching devices turning on simultaneously, even for a very short time ...

Page 128

... Specifications and information herein are subject to change without notice. Dma request mode Timer0 INT Timer1 INT Timer2 INT OFF OFF OFF BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Timer3 INT Timer4 INT OFF ON ON OFF ON ON ...

Page 129

... S3C24A0 RISC MOCROPROCESSOR TIMER CONFIGURATION REGISTER0 (TCFG0) Timer input clock Frequency = PCLK / {prescaler value+1} / {divider value} {prescaler value} = 0~255 {divider value Register Address R/W TCFG0 0x44000000 R/W TCFG0 Bit Reserved [31:24] Dead zone length [23:16] These 8 bits determine the dead zone length. The 1 unit time of the dead zone length is equal to the 1 unit time of timer 0 ...

Page 130

... Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR Description 5-MUX & DMA mode selecton register Description 0011 = Timer2 ...

Page 131

... S3C24A0 RISC MOCROPROCESSOR TIMER CONTROL REGISTER (TCON) Register Address TCON 0x44000008 TCON Bit Timer 4 auto reload on/off [22] (note) [21] Timer 4 manual update Timer 4 start/stop [20] Timer 3 auto reload on/off [19] Timer 3 output inverter on/off [18] (note) [17] Timer 3 manual update Timer 3 start/stop [16] Timer 2 auto reload on/off ...

Page 132

... This bit determines the output inverter on/off for Timer Inverter off 1 = Inverter on for TOUT0 This bit determines the manual update for Timer operation 1 = Update TCNTB0, TCMPB0 This bit determines start/stop for Timer Stop 1 = Start for Timer 0 BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR initial state ...

Page 133

... S3C24A0 RISC MOCROPROCESSOR Timer 0 Count Buffer Register & Compare Buffer Register (TCNTB0, TCMPB0) Register Address TCNTB0 0x4400000C TCMPB0 0x44000010 TCMPB0 Timer 0 compare buffer register TCNTB0 Timer 0 count buffer register TIMER 0 COUNT OBSERVATION REGISTER (TCNTO0) Register Address TCNTO0 0x44000014 TCNTO0 Timer 0 observation register Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available ...

Page 134

... Setting count buffer value for Timer 1 R/W Description R Timer 1 count observation register Bit Description Setting count observation value for Timer 1 BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x00000000 0x00000000 Initial State 0x00000000 Initial State 0x00000000 Reset Value 0x00000000 initial state ...

Page 135

... S3C24A0 RISC MOCROPROCESSOR TIMER 2 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB2, TCMPB2) Register Address TCNTB2 0x44000024 TCMPB2 0x44000028 TCMPB2 Timer 2 compare buffer register TCNTB2 Timer 2 count buffer register TIMER 2 COUNT OBSERVATION REGISTER (TCNTO2) Register Address TCNTO2 0x4400002C TCNTO2 Timer 2 observation register ...

Page 136

... Setting count buffer value for Timer 3 R/W Description R Timer 3 count observation register Bit Description Setting count observation value for Timer 3 BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x00000000 0x00000000 Initial State 0x00000000 Initial State 0x00000000 Reset Value 0x00000000 Initial State ...

Page 137

... S3C24A0 RISC MOCROPROCESSOR TIMER 4 COUNT BUFFER REGISTER (TCNTB4) Register Address TCNTB4 0x4400003C TCNTB4 Timer 4 count buffer register TIMER 4 COUNT OBSERVATION REGISTER (TCNTO4) Register Address TCNTO4 0x44000040 TCNTO4 Timer 4 observation register [15:0] Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. ...

Page 138

... PWM TIMER 7-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR NOTES BSW rv0.1-0417-N01 ...

Page 139

... WATCHDOG TIMER(Preliminary) OVERVIEW The S3C24A0 watchdog timer is used to resume the controller operation when it had been disturbed by malfunctions such as noise and system errors. It can be used as a normal 16-bit interval timer to request interrupt service. The watchdog timer generates the reset signal for 128 PCLK cycles. ...

Page 140

... WTCNT, before the watchdog timer starts. CONSIDERATION OF DEBUGGING ENVIRONMENT When S3C24A0 is in debug mode using Embedded ICE, the watchdog timer must not operate. The watchdog timer can determine whether or not the current mode is the debug mode from the CPU core signal (DBGACK signal) ...

Page 141

... Using the Watchdog Timer Control register, WTCON, you can enable/disable the watchdog timer, select the clock signal from 4 different sources, enable/disable interrupts, and enable/disable the watchdog timer output. The Watchdog timer is used to resume the S3C24A0 restart on mal-function after power-on; if controller restart is not desired, the Watchdog timer should be disabled. ...

Page 142

... Specifications and information herein are subject to change without notice. R/W Description R/W Watchdog timer data Register Description Watchdog timer count value for reload. R/W Description R/W Watchdog timer count Register Description BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x8000 Initial State 0x8000 Reset Value 0x8000 Initial State 0x8000 ...

Page 143

... DMA (Preliminary) OVERVIEW S3C24A0 supports four-channel DMA( Bridge DMA or peripheral DMA) controller that is located between the system bus and the peripheral bus. Each channel of DMA controller can perform data movements between devices in the system bus and/or peripheral bus with no restrictions. In other words, each channel can handle the ...

Page 144

... Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR Source3 Source4 Source5 USB device PWM Timer ...

Page 145

... Basic DMA Timing The DMA service means paired Reads and Writes cycles during DMA operation, which is one DMA operation. The Fig. 9-1 shows the basic Timing in the DMA operation of the S3C24A0. - The setup time and the delay time of XnXDREQ and XnXDACK are same in all the modes. ...

Page 146

... Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR – Related to the Protocol between XnXDREQ and XnXDACK 2cycles ...

Page 147

... S3C24A0 RISC MICROPROCESSOR Transfer Size - There are two different transfer sizes; single and Burst 4. - DMA holds the bus firmly during the transfer of these chunk of data, thus other bus masters can not get the bus. Burst 4 Transfer Size 4 sequential Reads and 4 sequential Writes are performed in the Burst 4 Transfer. ...

Page 148

... Figure 9-6. Whole service, Handshake Mode, Single Transfer Size 9-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR Read Write Read Write ...

Page 149

... S3C24A0 RISC MICROPROCESSOR DMA SPECIAL REGISTERS There are seven control registers for each DMA channel. (Since there are four channels, the total number of control registers is 28.) Four of them are to control the DMA transfer, and other three are to see the status of DMA controller ...

Page 150

... Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR Description DMA0 Initial Destination Register DMA1 Initial Destination Register ...

Page 151

... S3C24A0 RISC MICROPROCESSOR DMA CONTROL REGISTER (DCON) Register Address R/W DCON0 0x40400010 R/W DCON1 0x40500010 R/W DCON2 0x40600010 R/W DCON3 0x40700010 R/W DCONn Bit DMD_HS [31] Select one between demand mode and handshake mode demand mode is selected 1 : handshake mode is selected. In both modes, DMA controller starts its transfer and asserts DACK for a given asserted DREQ ...

Page 152

... DMA operation 9-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR Description Sourc Source Source1 ...

Page 153

... S3C24A0 RISC MICROPROCESSOR DSZ [21:20] Data size to be transferred Byte 10 = Word TC [19:0] Initial transfer count (or transfer beat). Note that the actual number of bytes that are transferred is computed by the following equation: DSZ x TSZ x TC, where DSZ, TSZ, and TC represent data size (DCONn[21:20]), transfer size (DCONn[28]), and initial transfer count, respectively ...

Page 154

... Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR Description DMA0 Current Source Register DMA1 Current Source Register ...

Page 155

... S3C24A0 RISC MICROPROCESSOR DMA MASK TRIGGER REGISTER (DMASKTRIG) Register Address R/W DMASKTRIG0 0x40400020 R/W DMASKTRIG1 0x40500020 R/W DMASKTRIG2 0x40600020 R/W DMASKTRIG3 0x40700020 R/W DMASKTRIGn Bit STOP [2] Stop the DMA operation. 1: DMA stops as soon as the current atomic transfer ends. If there is no current running atomic transfer, DMA stops immediately ...

Page 156

... S3C24A0 RISC MICROPROCESSOR RTC (REAL TIME CLOCK)(Preliminary) OVERVIEW The RTC (Real Time Clock) unit can be operated by the backup battery while the system power is off. The RTC can transmit 8-bit data to CPU as BCD (Binary Coded Decimal) values using the STRB/LDRB ARM operation. ...

Page 157

... BCD digits cannot decide whether 00 year is a leap year or not. For example, it can not discriminate between 1900 and 2000. To solve this problem, the RTC block in S3C24A0 has hard-wired logic to support the leap year in 2000. Please note 1900 is not leap year while 2000 is leap year. Therefore, two digits S3C24A0 denote 2000, not 1900 ...

Page 158

... S3C24A0 RISC MICROPROCESSOR ALARM FUNCTION The RTC generates an alarm signal at a specified time in the power down mode or normal operation mode. In normal operation mode, the alarm interrupt (ALMINT) is activated. In the power down mode the power management wakeup (PMWKUP) signal is activated as well as the ALMINT. The RTC alarm register, RTCALM, determines the alarm enable/disable and the condition of the alarm time setting ...

Page 159

... Specifications and information herein are subject to change without notice. R/W Description R/W RTC control Register (by byte) Description 1 = Reset R/W Description R/W Tick time count Register (by byte) Description 1 = Enable BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x0 Initial State Reset Value 0x0 Initial State 0 000000 ...

Page 160

... S3C24A0 RISC MICROPROCESSOR RTC ALARM CONTROL REGISTER (RTCALM) RTCALM register determines the alarm enable and the alarm time. Note that the RTCALM register generates the alarm signal through both ALMINT and PMWKUP in power down mode, but only through ALMINT in the normal operation mode ...

Page 161

... Alarm second data Register Description R/W Description R/W Alarm minute data Register (by byte) Description R/W Description R/W Alarm hour data Register Description BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x0 Initial State 0 000 0000 Reset Value 0x00 Initial State 0 000 0000 Reset Value 0x0 ...

Page 162

... S3C24A0 RISC MICROPROCESSOR ALARM DATE DATA REGISTER (ALMDATE) Register Address ALMDATE 0x44200060 ALMDATE Bit Reserved [7:6] Reserved DATEDATA [5:4] BCD value for alarm date, from 0 to 28, 29, 30, 31 from [3:0] from ALARM MON DATA REGISTER (ALMMON) Register Address ALMMON 0x44200064 ALMMON Bit ...

Page 163

... RTC round reset Register (by byte) Description 1 = Enable R/W Description R/W BCD second Register (by byte) Description R/W Description R/W BCD minute Register (by byte) Description BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x0 Initial State 0 000 Reset Value Undefined Initial State - - Reset Value Undefined Initial State - - ...

Page 164

... S3C24A0 RISC MICROPROCESSOR BCD HOUR REGISTER (BCDHOUR) Register Address BCDHOUR 0x44200078 BCDHOUR Bit Reserved [7:6] HOURDATA [5:4] [3:0] BCD DATE REGISTER (BCDDATE) Register Address BCDDATE 0x4420007C BCDDATE Bit Reserved [7:6] Reserved DATEDATA [5:4] BCD value for date from [3:0] from BCD DAY REGISTER (BCDDAY) Register ...

Page 165

... Bit YEARDATA [7:0] 10-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR R/W Description R/W BCD month Register (by byte) Description Reserved ...

Page 166

... UART can operates at more higher speed. Each UART channel contains two 64-byte FIFOs for receiver and transmitter. The S3C24A0 UART includes programmable baud-rates, infrared (IR) transmit/receive, one or two stop bit insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking. Each UART contains a baud-rate generator, transmitter, receiver and control unit, as shown in Figure11-1. The baud-rate generator can be clocked by PCLK ...

Page 167

... Receive Holding Register (Non-FIFO mode only) Receive Buffer Register(64 Byte) Receive FIFO Register (FIFO mode) BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR TXDn Clock Source RXDn ...

Page 168

... Word Length bit) and the Rx FIFO is not empty in the FIFO mode. Auto Flow Control(AFC) S3C24A0's UART 0 and UART 1 support auto flow control with nRTS and nCTS signals, in case, it would have to connect UART to UART. If users connect UART to a Modem, disable auto flow control bit in UMCONn register and control the signal of nRTS by software ...

Page 169

... Check the value of UMSTATn[0]. If the value is '1'(nCTS is activated), users write the data to Tx FIFO register. 11-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR 32, users have to set the value to ...

Page 170

... In this case, users control these signals with general I/O ports by S/W because the AFC does not support the RS-232C interface. Interrupt/DMA Request Generation Each UART of S3C24A0 has four status (Tx/Rx/Error) signals: buffer empty, and Transmit shifter empty, all of which are indicated by the corresponding UART status register (UTRSTATn/UERSTATn) ...

Page 171

... Figure 11-3. Example showing UART Receiving 5 Characters with 2 Errors 11-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR Error Interrupt - - The frame error (in B) interrupt occurs. ...

Page 172

... UART error of 1.69%. Loop-back Mode The S3C24A0 UART provides a test mode referred to as the loopback mode, to aid in isolating faults in the communication link. In this mode, the transmitted data is immediately received. This feature allows the processor to verify the internal transmit and to receive the data path of each SIO channel. This mode can be selected by setting the loopback-bit in the UART control register (UCONn) ...

Page 173

... UART IR (Infrared) Mode The S3C24A0 UART block supports infrared (IR) transmission and reception, which can be selected by setting the infrared-mode bit in the UART line control register (ULCONn). The implementation of the mode is shown in Figure 11- transmit mode, the transmit period is pulsed at a rate of 3/16, the normal serial transmit rate (when the transmit data bit is zero) ...

Page 174

... S3C24A0 RISC MICROPROCESSOR Start Bit 0 1 Figure 11-4. Serial I/O Frame Timing Diagram (Normal UART) Start Bit Bit Time Figure 11-5. Infrared Transmit Mode Frame Timing Diagram Start Bit 0 1 Figure 11-6. Infrared Receive Mode Frame Timing Diagram Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available ...

Page 175

... Specifications and information herein are subject to change without notice. R/W Description R/W UART channel 0 line control register R/W UART channel 1 line control register Description 01 = 6-bits 11 = 8-bits BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x00 0x00 Initial State 0 0 000 0 00 ...

Page 176

... S3C24A0 RISC MICROPROCESSOR UART CONTROL REGISTER There are two UART control registers, UCON0 and UCON1 in the UART block. Register Address UCON0 0x44400004 UCON1 0x44404004 UCONn Bit Clock selection [10] Select PCLK or UARTCLK for the UART baud rate. 0=PCLK 1= UARTCLK : UBRDIVn = (int)( UARTCLK / (bps x 16 ...

Page 177

... FIFO, the Rx interrupt will be generated (receive time out), and the users should check the FIFO status and read out the rest. 11-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR 00 00 ...

Page 178

... S3C24A0 RISC MICROPROCESSOR UART FIFO CONTROL REGISTER There are two UART FIFO control registers, UFCON0 and UFCON1 in the UART block. Register Address UFCON0 0x44400008 UFCON1 0x44404008 UFCONn Bit Tx FIFO Trigger Level [7:6] These two bits determine the trigger level of transmit FIFO Empty ...

Page 179

... These bits must be 0's Request to Send [0] If AFC bit is enabled, this value will be ignored. In this case the S3C24A0 will control nRTS automatically. If AFC bit is disabled, nRTS must be controlled by S/ 'H' level(Inactivate nRTS) 11-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. ...

Page 180

... S3C24A0 RISC MICROPROCESSOR UART TX/RX STATUS REGISTER There are two UART Tx/Rx status registers, UTRSTAT0 and UTRSTAT1 in the UART block. Register Address UTRSTAT0 0x44400010 UTRSTAT1 0x44404010 UTRSTATn Bit Transmitter empty [2] This bit is automatically set to 1 when the transmit buffer register has no valid data to transmit and the transmit shift register is empty ...

Page 181

... Specifications and information herein are subject to change without notice. R/W Description R UART channel 0 Rx error status register R UART channel 1 Rx error status register Description BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x0 0x0 Initial State 0 ...

Page 182

... S3C24A0 RISC MICROPROCESSOR UART FIFO STATUS REGISTER There are two UART FIFO status registers, UFSTAT0 and UFSTAT1 in the UART block. Register Address UFSTAT0 0x44400018 UFSTAT1 0x44404018 UFSTATn Bit Reserved [15] Tx FIFO Full [14] Tx FIFO Count [13:8] Reserved [7] Rx FIFO Full [6] Rx FIFO Count ...

Page 183

... UMSTAT1 0x4440401C UMSTAT0 Bit Reserved [7:5] DCTS [4] Delta CTS This bit indicates that the nCTS input to S3C24A0 has changed state since the last time it was read by CPU. (Refer to Figure 11- Has not changed 1 = Has changed Reserved [3:1] Clear to Send [ CTS signal is not activated(nCTS pin is high) ...

Page 184

... S3C24A0 RISC MICROPROCESSOR UART TRANSMIT BUFFER REGISTER(HOLDING REGISTER & FIFO REGISTER) There are two UART transmit buffer registers, UTXH0 and UTXH1 in the UART block. UTXHn has an 8-bit data for transmission data. Register Address UTXH0 0x44400020 (by byte) UTXH1 0x44404020 (by byte) UTXHn Bit ...

Page 185

... Specifications and information herein are subject to change without notice. 16 -1) and UARTCLK should be smaller than PCLK. R/W Description R/W Baud rate divisior register 0 R/W Baud rate divisior register 1 Description BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value - - Initial State - ...

Page 186

... S3C24A0 RISC MICROPROCESSOR IRDA CONTROLLER(Preliminary) OVERVIEW The Samsung IrDA Core is a wireless serial communication controller. Supporting two different types of IrDA speed(MIR, FIR), this core can transmit Ir(Infrared) pulses Mbps speed. To lessen the CPU burden, it has configurable FIFO feature. This makes it easy to adjust the internal FIFO sizes. ...

Page 187

... IrDA Transceiver control (Shutdown, Bandwidth) (output) 12-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR MASTER_Control Iinterrupt Control and payload length store ...

Page 188

... S3C24A0 RISC MICROPROCESSOR FUNCTION DESCRIPTION Fast-Speed Infrared (FIR) Mode (IrDA 1.1) In this FIR mode, data communicates at the baud rate speed of 4 Mbps. In the data transmission mode, the core encodes the payload data into the 4PPM format and attaches the Preamble, Start Flag, CRC-32, and Stop flag on the encoded payload and shifts them out serially ...

Page 189

... CRC crc 3 6 pay_end CRC Transmit 4 crc_end Stop 2u sip Flag Pulse Transmit transmit 5 7 stp_end & ena pul_end & ena stp_end & ~ena pul_end & ~ena Figure 12-2. Fir modulation process BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR ~abort ...

Page 190

... S3C24A0 RISC MICROPROCESSOR Figure 12-3 shows FIR demodulation state machine. The state machine starts when ACR register bit 6 is set to logic high. The incoming data will be depacketized by removing preamble and start flag and stop flag . Also, 4PPM decoding and CRC decoding is carried out. ...

Page 191

... Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR Link layer frame (Payload) CRC16 BSW rv0.1-0417-N01 STO ...

Page 192

... S3C24A0 RISC MICROPROCESSOR Figure 12-5 shows MIR modulation state machine. This machine works very similarly with FIR modulation state machine. The major difference is that the MIR data transmission needs bit stuffing. After the every 5 consecutive ones, a zero data should be stuffed in MIR payload data. The state machine for this bit-stuffing is not presented here ...

Page 193

... MIR demodulation is simplified to start flag detection state. 12-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S3C24A0 RISC MICROPROCESSOR ~(ena&flagbyte) Rx Enable 0 ena & ...

Page 194

... S3C24A0 RISC MICROPROCESSOR CORE INITIALIZATION PROCEDURE MIR/FIR Mode Initialization Operation 1) Program the MDR register to select the MIR/FIR mode. Program the ACR register to select the transceiver type For the Temic-IBM type transceiver, program twice in ACR[0] = 1’b0 and ACR[0] = 1’b1. - For the HP type transceiver, program just once in ACR[0] = 1’b0 to FIR/MIR mode. ...

Page 195

... TX FIFO and reset this bit by writing a ‘0’ to bit ‘1’ before next frame can be transmitted. This signal controls IrDA_SDBW output signal used for controlling mode (shutdown, band width) of IrDA transceiver. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x00 Initial State 0 0 ...

Page 196

... S3C24A0 RISC MICROPROCESSOR IrDA MODE DEFINITION REGISTER(IrDA_MDR) Register Address R/W IrDA_MDR 0x41800004 R/W IrDA _MDR Bit Reserved [7:5] SIP Select [4] Temic select [3] [2:0] Mode select IrDA INTERRUPT / DMA CONFIGURATION REGISTER(IrDA_CNF) Register Address R/W IrDA_CNF 0x41800008 R/W IrDA _CNF Bit [7:4] Reserved [3] DMA Enable [2] DMA Mode [1] Reserved Interrupt Enable ...

Page 197

... TX FIFO is over the threshold level. Bit 0 enables received data in RX FIFO over threshold level interrupt when the RX FIFO is equal to or above the threshold level. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x00 Initial State 0 0 ...

Page 198

... S3C24A0 RISC MICROPROCESSOR IrDA INTERUPT IDENTIFICATION REGISTER(IrDA_IIR) Register Address R/W IrDA _IIR 0x41800010 R IrDA _IIR Bit Last byte to Rx FIFO [7] Error indication [6] Tx Underrun [5] [4] Last byte detect [3] Rx overrun [2] Last byte read from Rx FIFO [1] Tx FIFO below threshold Rx FIFO over [0] threshold Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available ...

Page 199

... LSR register. Reserved RX FIFO empty. It indicates that the RX FIFO is empty. When the state of RX FIFO turns into empty set to ‘1’. When the RX FIFO is not empty set to ‘0’. BSW rv0.1-0417-N01 S3C24A0 RISC MICROPROCESSOR Reset Value 0x03 Initial State 1 0 ...

Page 200

... S3C24A0 RISC MICROPROCESSOR IrDA FIFO CONTROL REGISTER(IrDA_FCR) Register Address R/W IrDA _FCR 0x41800018 R/W IrDA _FCR Bit Rx FIFO Trigger level [7:6] select [5] FIFO size select [4] TX FIFO Clear Notification RX FIFO Clear [3] Notification Tx FIFO reset [2] Rx FIFO reset [1] [0] FIFO enable Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available ...

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