AT45DB081B-RU ATMEL Corporation, AT45DB081B-RU Datasheet

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AT45DB081B-RU

Manufacturer Part Number
AT45DB081B-RU
Description
Manufacturer
ATMEL Corporation
Datasheet

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Features
Description
The AT45DB081B is a 2.5-volt or 2.7-volt only, serial interface Flash memory ideally
suited for a wide variety of digital voice-, image-, program code- and data-storage
applications. Its 8,650,752 bits of memory are organized as 4096 pages of 264 bytes
each. In addition to the main memory, the AT45DB081B also contains two SRAM
main memory is being reprogrammed, as well as writing a continuous data stream.
Pin Configurations
data buffers of 264 bytes each. The buffers allow receiving of data while a page in the
Pin Name
CS
SCK
SI
SO
WP
RESET
RDY/BUSY
Single 2.5V - 3.6V or 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
20 MHz Max Clock Frequency
Page Program Operation
Supports Page and Block Erase Operations
Two 264-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming of Nonvolatile Memory
Continuous Read Capability through Entire Array
Low Power Dissipation
Hardware Data Protection Feature
100% Compatible to AT45DB081 and AT45DB081A
5.0V-tolerant Inputs: SI, SCK, CS, RESET and WP Pins
Commercial and Industrial Temperature Ranges
Green (Pb/Halide-free) Packaging Options
– Single Cycle Reprogram (Erase and Program)
– 4096 Pages (264 Bytes/Page) Main Memory
– Ideal for Code Shadowing Applications
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
Top View through Package
RESET
SCK
CS
SI
1
2
3
4
CASON
Function
Chip Select
Serial Clock
Serial Input
Serial Output
Hardware Page Write
Protect Pin
Chip Reset
Ready/Busy
8
7
6
5
SO
GND
VCC
WP
RDY/BUSY
GND
RESET
SCK
NC
NC
CS
SO
NC
NC
NC
NC
NC
NC
NC
GND
SI
VCC
SCK
WP
NC
NC
NC
NC
NC
CS
SO
SI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
NC
NC
WP
RESET
RDY/BUSY
NC
NC
NC
NC
NC
NC
NC
NC
TSOP Top View
Type 1
through Package
CBGA Top View
C
D
A
B
E
SCK
CS
SO
NC
1
RDY/BSY
GND
NC
NC
SI
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RESET
VCC
NC
WP
NC
3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
8-megabit
2.5-volt Only or
2.7-volt Only
DataFlash
AT45DB081B
For New
Designs Use
AT45DB081D
Rev. 2225J–DFLSH–2/08
®

Related parts for AT45DB081B-RU

AT45DB081B-RU Summary of contents

Page 1

... Green (Pb/Halide-free) Packaging Options Description The AT45DB081B is a 2.5-volt or 2.7-volt only, serial interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. Its 8,650,752 bits of memory are organized as 4096 pages of 264 bytes each. In addition to the main memory, the AT45DB081B also contains two SRAM data buffers of 264 bytes each ...

Page 2

... VCC GND RDY/BUSY To provide optimal flexibility, the memory array of the AT45DB081B is divided into three levels of granularity comprising of sectors, blocks, and pages. The Memory Architecture Diagram illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page-by-page basis ...

Page 3

... SECTOR 0 BLOCK 0 BLOCK 1 BLOCK 2 BLOCK 30 BLOCK 31 BLOCK 32 BLOCK 33 BLOCK 62 BLOCK 63 BLOCK 64 BLOCK 65 BLOCK 510 BLOCK 511 Block = 2112 bytes (2K + 64) AT45DB081B PAGE ARCHITECTURE 8 Pages PAGE 0 PAGE 1 PAGE 6 PAGE 7 PAGE 8 PAGE 9 PAGE 14 PAGE 15 PAGE 16 PAGE 17 PAGE 18 PAGE 4093 PAGE 4094 PAGE 4095 ...

Page 4

... After bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as CS remains AT45DB081B 4 CAR ...

Page 5

... The device density is indicated using bits and 2 of the status register. For the AT45DB081B, the four bits are and 1. The decimal value of these four binary bits does not equate to the device density; the three bits represent a combinational code relating to differ- ing densities of Serial DataFlash devices, allowing a total of sixteen different density configurations ...

Page 6

... Both the erase and the programming of the page are internally self-timed and AT45DB081B 6 . During this time, the status register will indicate that the part is ...

Page 7

... The operation is inter- nally self-timed and should take place in a maximum time of t status register will indicate that the part is busy. AT45DB081B . During this time, the status register will indi- EP XFR ...

Page 8

... CHIP SELECT (CS): The DataFlash is selected when the CS pin is low. When the device is not selected, data will not be accepted on the SI pin, and the SO pin will remain in a high-impedance state. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition on the CS pin is required to end an operation. AT45DB081B 8 2225J–DFLSH–2/08 ...

Page 9

... CS pin will be required to start a valid instruction. The SPI mode will be automatically selected on every falling edge sampling the inactive clock state. After power is applied and V before an operational mode is started. 2225J–DFLSH–2/ the minimum datasheet value, the system should wait AT45DB081B 9 ...

Page 10

... Auto Page Rewrite through Buffer 2 Note: In Tables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock Polarity Low, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3). AT45DB081B 10 SCK Mode Inactive Clock Polarity Low or High ...

Page 11

... N/A N AT45DB081B Address Byte ...

Page 12

... Output High Voltage OH Note during a buffer read is 20mA maximum. cc1 AT45DB081B 12 *NOTICE: + 0.6V CC AT45DB081B (2.5V Version) 0° 70° C – 2. the minimum specified datasheet value, the system should wait 20 ms before an opera- CC Condition CS, RESET all inputs CC at CMOS levels MHz ...

Page 13

... Page Programming Time P t Page Erase Time PE t Block Erase Time BE t RESET Pulse Width RST t RESET Recovery Time REC 2225J–DFLSH–2/08 AT45DB081B AT45DB081B (2.5V Version) AT45DB081B Min Max Min Max 250 250 250 250 250 250 ...

Page 14

... SPI Mode 3. Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0 CS SCK HIGH IMPEDANCE SO SI Waveform 2 – Inactive Clock Polarity High and SPI Mode CSS SCK HIGH AT45DB081B 14 2. 2.0 DRIVING MEASUREMENT 0.8 LEVELS LEVEL 0.45V DEVICE UNDER TEST ...

Page 15

... For densities larger than 8M bits, the “r” bits become the most significant Page Address bit for the appropriate density. 2225J–DFLSH–2/08 SI CMD 8 bits 8 bits Page Address (PA11-PA0) (BA8-BA0/BFA8-BFA0) AT45DB081B t t REC CSS t RST HIGH IMPEDANCE 8 bits LSB Byte/Buffer Address ...

Page 16

... PA11-7 Buffer Write CS SI CMD Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page Each transition represents 8 bits and 8 clock cycles AT45DB081B 16 FLASH MEMORY ARRAY PAGE PROGRAM THROUGH BUFFER 2 PAGE PROGRAM THROUGH BUFFER 1 I/O INTERFACE SI PA6-0, BFA8 ...

Page 17

... MAIN MEMORY PAGE READ I/O INTERFACE SO PA6-0, BA8 BA7-0 X Starts reading page data into buffer CMD PA11-7 PA6-0, X X···X, BFA8 CMD X BFA7-0 AT45DB081B MAIN MEMORY PAGE TO BUFFER 2 BUFFER 2 (264 BYTES) BUFFER 2 READ n 1st byte read ...

Page 18

... Detailed Bit-level Read Timing – Inactive Clock Polarity Low Continuous Array Read (Opcode: 68H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: 52H) CS SCK COMMAND OPCODE AT45DB081B DATA OUT ...

Page 19

... HIGH-IMPEDANCE SO 2225J–DFLSH–2/ HIGH-IMPEDANCE AT45DB081B DATA OUT MSB STATUS REGISTER OUTPUT MSB ...

Page 20

... Detailed Bit-level Read Timing – Inactive Clock Polarity High Continuous Array Read (Opcode: 68H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: 52H) CS SCK COMMAND OPCODE AT45DB081B DATA OUT HIGH-IMPEDANCE ...

Page 21

... COMMAND OPCODE HIGH-IMPEDANCE SO 2225J–DFLSH–2/ HIGH-IMPEDANCE AT45DB081B DATA OUT MSB STATUS REGISTER OUTPUT MSB LSB ...

Page 22

... Detailed Bit-level Read Timing – SPI Mode 0 Continuous Array Read (Opcode: E8H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: D2H) CS SCK COMMAND OPCODE AT45DB081B DATA OUT ...

Page 23

... HIGH-IMPEDANCE SO 2225J–DFLSH–2/ HIGH-IMPEDANCE AT45DB081B DATA OUT MSB STATUS REGISTER OUTPUT MSB D 4 ...

Page 24

... Detailed Bit-level Read Timing – SPI Mode 3 Continuous Array Read (Opcode: E8H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: D2H) CS SCK COMMAND OPCODE AT45DB081B DATA OUT HIGH-IMPEDANCE ...

Page 25

... COMMAND OPCODE HIGH-IMPEDANCE SO 2225J–DFLSH–2/ HIGH-IMPEDANCE AT45DB081B DATA OUT MSB STATUS REGISTER OUTPUT MSB LSB ...

Page 26

... A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. AT45DB081B 26 START provide address ...

Page 27

... X • • • • • • • • • AT45DB081B If planning to modify multiple bytes currently stored within a page of the Flash array PA5 PA4 PA3 PA2 - PA0 • • • ...

Page 28

... AT45DB081B 28 Ordering Code AT45DB081B-CC AT45DB081B-CNC AT45DB081B-RC AT45DB081B-TC AT45DB081B-CI AT45DB081B-CNI AT45DB081B-RI AT45DB081B-TI AT45DB081B-CC-2.5 AT45DB081B-CNC-2.5 AT45DB081B-RC-2.5 AT45DB081B-TC-2.5 Ordering Code AT45DB081B-CNU AT45DB081B-RU AT45DB081B-TU AT45DB081B-CU Package Type Package Operation Range 14C1 Commercial 8CN3 (0° 70° C) 28R 28T 14C1 Industrial 8CN3 (-40° 85° C) 28R ...

Page 29

... MAX 2.0 (0.079 4.0 (0.157 0.46 (0.018) 1.00 (0.0394) BSC DIA BALL TYP BOTTOM VIEW TITLE 14C1, 14-ball ( Array), 4 1.4 mm Body, 1.0 mm Ball Pitch Chip-scale Ball Grid Array Package (CBGA) AT45DB081B SIDE VIEW 0.30 (0.012)MIN 1.50 (0.059) REF DRAWING NO. 04/11/01 REV. 14C1 A 29 ...

Page 30

... All dimensions and tolerance conform to ASME Y 14.5M, 1994. 2. The surface finish of the package shall be EDM Charmille #24-27. 3. Unless otherwise specified tolerance: Decimal ±0.05, Angular ±2 4. Metal Pad Dimensions. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB081B 30 D Top View Side View Pin1 Pad Corner L1 ...

Page 31

... Mold Flash or protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 2225J–DFLSH–2/ TITLE 28R, 28-lead, 0.330" Body Width, Plastic Gull Wing Small Outline (SOIC) AT45DB081B COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 2.39 – 2.79 A1 0.050 – 0.356 D 18 ...

Page 32

... This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion 0.15 mm per side and 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB081B 32 PIN SEATING PLANE ...

Page 33

... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel tered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...

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