K6T0808C1D-TF70 Samsung, K6T0808C1D-TF70 Datasheet
K6T0808C1D-TF70
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K6T0808C1D-TF70 Summary of contents
Page 1
... K6T0808C1D Family Document Title 32Kx8 bit Low Power CMOS Static RAM Revision History Revision No History 0.0 Initial draft 0.1 First revision - M62256DL/DLI I = 100 K SB1 KM62256DL SB1 KM62256DLI SB1 - 8pF KM62256D-4/5/7 Family tOH = 5 10ns - KM62256DL/DLI KM62256DL-L/DLI ...
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... SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. GENERAL DESCRIPTION The K6T0808C1D families are fabricated by SAMSUNG s advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The fami- lies also support low data retention voltage for battery back- up operation with low data retention current ...
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... Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Industrial Temperature Products(-40~85 C) Part Name K6T0808C1D-GP70 K6T0808C1D-GF70 K6T0808C1D-TP70 K6T0808C1D-TF70 K6T0808C1D-RP70 K6T0808C1D-RF70 WE I ...
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... K6T0808C1D Family RECOMMENDED DC OPERATING CONDITIONS Item Supply voltage Ground Input high voltage Input low voltage Note: 1. Commercial Product : otherwise specified A Industrial Product : T =- otherwise specified A 2. Overshoot : V +3.0V in case of pulse width 30ns CC 3. Undershoot : -3.0V in case of pulse width 30ns 4 ...
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... DATA RETENTION CHARACTERISTICS Item Symbol Vcc for data retention V DR Data retention current I DR Data retention set-up time t SDR Recovery time t RDR Including scope and jig capacitance = K6T0808C1D-P Family:T A Symbol 1) 55 Min ...
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... K6T0808C1D Family TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address Data Out Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) Address CS OE High-Z Data out NOTES (READ CYCLE and are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage ...
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... K6T0808C1D Family TIMING WAVEFORM OF WRITE CYCLE(1) Address CS WE Data in Data Undefined Data out TIMING WAVEFORM OF WRITE CYCLE(2) Address CS WE Data in Data out NOTES (WRITE CYCLE write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high the end of write ...
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... K6T0808C1D Family PACKAGE DIMENSIONS 28 PIN DUAL INLINE PACKAGE(600mil) #28 13.60 0.20 0.535 0.008 #1 1. 0.065 28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil) #28 #1 18.69 0.736 18.29 0.720 0.89 0.41 0. 0.035 0.016 0.004 #15 #14 36.72 MAX 1.446 36.32 0.20 1.430 0.008 0.46 0.10 0.018 0.004 2.54 1.52 0.10 0.100 0.060 0.004 #15 11.81 0.30 0.465 0.012 #14 2.59 0.20 MAX 0.102 0.008 3.00 0.118 0.20 0.008 1.27 0.05 MIN 0.050 ...
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... K6T0808C1D Family PACKAGE DIMENSIONS 28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4F) +0.10 0.20 -0.05 +0.004 0.008 -0.002 #1 0.55 #14 0.0217 0.25 TYP 0.010 0~8 0.45 ~0.75 0.018 ~0.030 28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4R) +0.10 0.20 -0.05 +0.004 0.008 -0.002 #14 0.55 0.0217 #1 0.25 TYP 0.010 0~8 0.45 ~0.75 0.018 ~0.030 13.40 0.20 0.528 0.008 #28 #15 11.80 0.10 +0.10 0.15 0.465 0.004 -0.05 +0.004 ...