W83697UF Winbond, W83697UF Datasheet
W83697UF
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W83697UF Summary of contents
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... WINBOND LPC I/O W83697UF W83697UG Date: May 26, 2005 Revision W83697UF/W83697UG Publication Release Date: May 26, 2005 Revision A1 ...
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... Table of Contents- 1. GENERAL DESCRIPTION ............................................................................................................. 4 2. FEATURES..................................................................................................................................... 5 3. BLOCK DIAGRAM FOR W83697UF.............................................................................................. 7 4. PIN CONFIGURATION FOR W83697UF ...................................................................................... 8 5. PIN DESCRIPTION ........................................................................................................................ 9 5.1 LPC Interface...................................................................................................................... 10 5.2 FDC Interface ..................................................................................................................... 11 5.3 Multi-Mode Parallel Port ..................................................................................................... 12 5.4 Serial Port Interface ............................................................................................................ 17 5.5 Infrared Port........................................................................................................................ 18 5.6 Flash ROM Interface .......................................................................................................... 19 5.7 General Purpose I/O Port ................................................................................................... 19 5.8 Smart Card Interface .......................................................................................................... 20 5.9 PWM & General Purpose I/O Port 8................................................................................... 21 5.10 Game Port & ...
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... DC CHARACTERISTICS ................................................................................................... 50 8. APPLICATION CIRCUITS ............................................................................................................ 58 8.1 Parallel Port Extension FDD............................................................................................... 58 8.2 Parallel Port Extension 2FDD............................................................................................. 59 8.3 Four FDD Mode .................................................................................................................. 59 9. ORDERING INSTRUCTION......................................................................................................... 60 10. HOW TO READ THE TOP MARKING ......................................................................................... 60 11. PACKAGE DIMENSIONS............................................................................................................. 61 12. APPENDIX A: DEMO CIRCUIT.................................................................................................... 62 13. REVISION HISTORY.................................................................................................................... 67 W83697UF/W83697UG Publication Release Date: May 26, 2005 - 3 - Revision A1 ...
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... Windows 95/98 The W83697UF provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function. General Purpose Port 1 is designed to be functional even in power down mode (VCC is off) ...
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... Fully programmable serial-interface characteristics: --- 8-bit characters --- Even, odd or no parity bit generation/detection --- 1, 1 stop bits generation • Internal diagnostic capabilities: --- Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation W83697UF/W83697UG Publication Release Date: May 26, 2005 - 5 - Revision A1 ...
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... General purpose I/O ports can serve as simple I/O ports, watch dog timer output, power LED output, infrared I/O pins, suspend LED output, Beep output • Functional in power down mode Smart Card Reader Interface • ISO7816 protocol compliant • PC/SC T=0 , T=1 compliant Package • 128-pin PQFP W83697UF/W83697UG - -1) ...
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... BLOCK DIAGRAM FOR W83697UF LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ Joystick interface signals MSI MSO General-purpose I/O pins Smart Card interface signals Flash ROM interface signals W83697UF/W83697UG LPC Interface Game URA, Port MIDI FDC GPIO IR SC CIR Flash PRT ROM ACPI ...
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... PIN CONFIGURATION FOR W83697UF SINC/GP63 SINC/GP63 103 103 SOUTC/GP62 SOUTC/GP62 104 104 DCDC#/GP61 DCDC#/GP61 105 105 RIC#/GP60 RIC#/GP60 106 106 SCPSNT/CTSD#/GP77 SCPSNT/CTSD#/GP77 107 107 SCIO/DSRD#/GP76 SCIO/DSRD#/GP76 108 108 SCCLK/RTSD#/GP75 SCCLK/RTSD#/GP75 109 ...
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... Output pin with 8 mA source-sink capability O 12 Output pin with 12 mA source-sink capability O 16 Output pin with 16 mA source-sink capability O 24 Output pin with 24 mA source-sink capability O 12p3 3.3V output pin with 12 mA source-sink capability W83697UF/W83697UG PIN DESCRIPTION Publication Release Date: May 26, 2005 - 9 - Revision A1 ...
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... IN LFRAME# 27 tsp3 IN LRESET# 28 tsp3 W83697UF/W83697UG PIN DESCRIPTION FUNCTION System clock input. According to the input frequency 24MHz or 48MHz selectable through register. Default is 24MHz input. Generated PME event. PCI clock input. Encoded DMA Request signal. Serial IRQ input/Output. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral ...
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... OD 24 DSKCHG csu W83697UF/W83697UG FUNCTION Drive Density Select bit 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally KΩ resistor. The resistor can be disabled by bit 7 of L0- CRF0 (FIPURDWN) ...
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... EXTENSION FDD MODE: MOB2# 12 This pin is for Extension FDD B; its function is the same as the MOB# pin of FDC. EXTENSION 2FDD MODE: MOB2# This pin is for Extension FDD A and B; its function is the same as the MOB# pin of FDC W83697UF/W83697UG FUNCTION Refer to the This pin is pulled high ...
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... This pin is for Extension FDD B; its function is the same as the STEP# pin of FDC. EXTENSION 2FDD MODE: STEP2# This pin is for Extension FDD A and B; its function is the same as the STEP# pin of FDC W83697UF/W83697UG FUNCTION This pin is pulled high This pin is Publication Release Date: May 26, 2005 Revision A1 ...
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... This pin is for Extension FDD B; its function is the same as the INDEX# pin of FDC pulled high internally. EXTENSION 2FDD MODE: INDEX2# This pin is for Extension FDD A and B; its function is the same as the INDEX# pin of FDC pulled high internally W83697UF/W83697UG FUNCTION Refer to the ...
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... This pin is for Extension FDD B; its function is the same as the RDATA# pin of FDC pulled high internally. EXTENSION 2FDD MODE: RDATA2# This pin is for Extension FDD A and B; its function is the same as the RDATA# pin of FDC pulled high internally W83697UF/W83697UG FUNCTION Publication Release Date: May 26, 2005 Revision A1 ...
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... ECP and EPP mode. - EXTENSION FDD MODE: This pin is a tri-state output. 12 EXTENSION 2FDD MODE: DSA2# This pin is for Extension FDD A; its function is the same as the DSA# pin of FDC W83697UF/W83697UG FUNCTION It is pulled high Refer to the description of the ...
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... RIA RIB# 63 W83697UF/W83697UG FUNCTION Clear To Send the modem control input. The function of these pins can be tested by reading bit 4 of the handshake status register. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART ...
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... IRRX ts 64 IRTX W83697UF/W83697UG FUNCTION Clear To Send the modem control input. General purpose I/O port 6 bit7. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. General purpose I/O port 6 bit6. ...
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... SIND IN t I/OD GP80 12t 118 WDTO OD 12 W83697UF/W83697UG Flash ROM interface Address[18:16] General purpose I/O port 5 bit7-5 12t Flash ROM interface Address[15:10] General purpose I/O port 4 bit7-2 12t Flash ROM interface Address[9:8] General purpose I/O port 4 bit1-0 12t Flash ROM interface Address[7:0] General purpose I/O port 3 bit7-0 ...
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... RID 114 I/OD GP70 24t W83697UF/W83697UG FUNCTION Smart card present detection Schmitt-trigger input. Clear To Send the modem control. General purpose I/O port 7 bit7. Smart card data I/O channel. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART ...
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... Joystick II timer pin. this pin connect to X positioning variable 24a resistors for the Josystick. (Default) General purpose I/O port 1 bit 3. 24cs Joystick I timer pin. this pin connect to X positioning variable 24a resistors for the Josystick. (Default) General purpose I/O port 1 bit 2. 24cs - 21 - W83697UF/W83697UG FUNCTION FUNCTION Publication Release Date: May 26, 2005 Revision A1 ...
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... CONFIGURATION REGISTER 6.1 Plug and Play Configuration The W83697UF uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. Device 0 to Logical Device B with the exception of logical device 4 for backward compatibility) which correspond to eleven individual functions: FDC (logical device 0), PRT (logical device 1), UART1 ...
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... Extended Functions Enable Registers (EFERs) After a power-on reset, the W83697UF enters the default operating mode. Before the W83697UF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers ...
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... Enter the extended function mode, interruptible double-write ;----------------------------------------------------------------------------------- MOV DX,2EH MOV AL,87H OUT DX,AL OUT DX,AL ;----------------------------------------------------------------------------- ; Configurate logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------- MOV DX,2EH MOV AL,07H OUT DX,AL ; point to Logical Device Number Reg. MOV DX,2FH MOV AL,01H OUT DX,AL ; select logical device 1 ; MOV DX,2EH W83697UF/W83697UG | - 24 - ...
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... SWRST --> Soft Reset. CR07 Bit [7:0]: LDNB7 - LDNB0 --> Logical Device Number Bit CR20 (read only) DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 Bit [7:0 (for W83697UF) CR21 (read only) DEVREVB7 - DEBREVB0 --> Device Rev = 0x1X (for W83697UF) Bit [7:0 Version change number. (Bit [3:0]) --> begin from 1 ...
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... Flash ROM I/F Address Segment (000F0000h ~ 000FFFFFh) enable/disable 0 Enable 1 Disable Bit 6: CLKSEL(Enable 48Mhz) 0 The clock input on Pin 1 should be 24 MHz. The clock input on Pin 1 should be 48 MHz. 1 The corresponding power-on setting pin is SOUTB (pin 61). Bit [5:4]: ROM size select Reserved W83697UF/W83697UG - 26 - ...
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... Select four FDD mode. HEFRAS These two bits define how to enable Configuration mode. The corresponding power-on Bit 6: setting pin is RTSA #(pin 49). HEFRAS Address and Value 0 Write 87h to the location 2E twice. 1 Write 87h to the location 4E twice. W83697UF/W83697UG Publication Release Date: May 26, 2005 - 27 - Revision A1 ...
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... Disable UART B/D legacy mode IRQ selecting, then HCR bit 3 is not effective on 1 selecting IRQ CR28 (Default 0x00) Bit [7:4]: Reserved. Bit [3]: Flash ROM I/F Address Segment (FFE80000h ~ FFEFFFFFh) enable/disable 0 Disable 1 Enable Bit [2:0]: PRTMODS2 - PRTMODS0 0xx Parallel Port Mode 100 Reserved 101 External FDC Mode 110 Reserved 111 External two FDC Mode W83697UF/W83697UG - 28 - ...
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... GPIO 3 1 Flash IF (XA7 ~ XA0) Bit 5: (PIN & 76 ~77) 0 GPIO 4 1 Flash IF (XA15 ~ XA10 & XA9 ~ A8) Bit 4: (PIN & 97) 0 GPIO 5(GP52 ~ 57) 1 Flash IF(XA18 ~ XA16 , ROMCS#, MEMR #, MEMW#) Bit [3:0]: Reserved W83697UF/W83697UG Publication Release Date: May 26, 2005 - 29 - Revision A1 ...
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... Pin104) 0 URC(SINC, SOUTC) 1 GPIO6(GP63, GP62) CR2C(SC & URD & GPIO7 Select. Default 0x30) Bit [7:6]: (Pin107, Pin108, Pin109, Pin110, Pin113) 00 SC(SCPSNT, SCIO,SCCLK, SCRST, SCPWR) 01 URD(NCTSD,NDSRD, NRTSD, NDTRD, NDCDD) 10 Reserved 11 GPIO7(GP77, GP76, GP75, GP74, GP71) Bit [5:4]: (Pin111) 00 Reserved 01 SIND 10 Reserved 11 GP73 W83697UF/W83697UG - 30 - ...
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... Bit [3:0]: These bits select IRQ resource for FDC. CR74 (Default 0x02 if PNPCSV = 0 during POR, default 0x04 otherwise) Bit [7:3]: Reserved. Bit [2:0]: These bits select DRQ resource for FDC. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04 - 0x07 No DMA active W83697UF/W83697UG Publication Release Date: May 26, 2005 - 31 - Revision A1 ...
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... Non-Burst Mode (Default) Bit 0: Floppy Mode 0 Normal Floppy Mode (Default) 1 Enhanced 3-mode FDD CRF1 (Default 0x00) Bit Boot Floppy 00 FDD A 01 FDD B 10 FDD C 11 FDD D Bit [5:4]: Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6. W83697UF/W83697UG - 32 - ...
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... Bit 5: Reserved. Bit DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A). 00 Select Regular drives and 2.88 format 01 3-mode drive 10 2 Meg Tape 11 Reserved Bit 2: Reserved. Bit [1:0]: DTYPE0, DTYPE1: Drive Type select (Refer to TABLE B). W83697UF/W83697UG Publication Release Date: May 26, 2005 - 33 - Revision A1 ...
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... Logical Device 1 (Parallel Port) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:1]: Reserved. Bit 0: 1 Activates the logical device. 0 Logical device is inactive. W83697UF/W83697UG TABLE A DATA RATE SELECTED DATA RATE DRATE1 DRATE0 ...
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... Bit [7:1]: Reserved. Bit 0: 1 Activates the logical device. 0 Logical device is inactive. CR60, CR61 (Default 0x03, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 1 I/O base address [0x100:0xFF8 byte boundary. W83697UF/W83697UG Publication Release Date: May 26, 2005 - 35 - Revision A1 ...
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... Reserved. Bit 6: 1 Activates the logical device IRQ sharing function. 0 Logical device IRQ sharing is inactive. Bit [5:4]: Reserved. Bit 3: RXW4C 0 No reception delay when SIR is changed from TX mode to RX mode. Reception delays 4 characters-time (40 bit-time) when SIR is changed from TX mode mode. W83697UF/W83697UG - 36 - ...
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... ASK-IR Note: The notation is normal mode in the IR function. Bit 2: HDUPLX. IR half/full duplex function select. 0 The IR function is Full Duplex. 1 The IR function is Half Duplex. W83697UF/W83697UG IRTX tri-state Active pulse 1.6 μ S Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & ...
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... When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. 6.10 Logical Device 8 (MIDI Port and GPIO Port 5) CR30 (MIDI Port Default 0x00) Bit [7:1]: Reserved. Bit 0: 1 MIDI/GP5 port is activate 0 MIDI/GP5 port is inactive. W83697UF/W83697UG - 38 - ...
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... Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value to Watch Dog Counter and start counting down. Reading this register returns current value in Watch Dog Counter instead of Watch Dog Timer Time-out value. W83697UF/W83697UG Publication Release Date: May 26, 2005 - 39 - ...
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... These two registers select the GP2,3,4 base address(0x100:FFF bytes boundary. IO address: CRF1 base address IO address + 1 : CRF4 base address IO address + 2 : CRF7 base address CRF0 (GP2 I/O selection register. Default 0xFF ) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. W83697UF/W83697UG - 40 - ...
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... When set to a '0', the incoming/outgoing port value is the same as in data register. 6.12 Logical Device A (ACPI) CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: 1 Activates the logical device. 0 Logical device is inactive. CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resources for W83697UF/W83697UG PME SMI / Publication Release Date: May 26, 2005 - 41 - Revision A1 ...
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... Bit 6: Reserved. (Return zero when read) Bit 5: MIDI’s trap status. Bit 4: Reserved. (Return zero when read) Bit 3: PRT’s trap status. Bit 2: FDC’s trap status. Bit 1: URA’s trap status. Bit 0:. URB’s trap status W83697UF/W83697UG - 42 - ...
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... PRTIRQSTS) or (FDCIRQEN and FDCIRQSTS) or (URAIRQEN and URAIRQSTS) or (URBIRQEN and URBIRQSTS) or (URCIRQEN and URCIRQSTS) or (WDTIRQEN and WDTIRQSTS) or (URDIRQEN and URDIRQEN) or (MIDIIRQEN and MIDIIRQEN) or (SCIRQEN and SCIRQEN) W83697UF/W83697UG PME interrupt due to any IRQ of the devices. Publication Release Date: May 26, 2005 - 43 - ...
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... WDTIRQEN. 0 disable the generation of an SMI / 1 enable the generation of an SMI / SMI interrupt due to watch dog timer's IRQ. Bit 1: Reserved. (Return zero when read) W83697UF/W83697UG PME interrupt due to URD's IRQ. PME interrupt due to URD's IRQ. PME interrupt due to URC's IRQ. PME interrupt due to URC's IRQ ...
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... Bit 0: URCPME. UART C auto power management enable. 0 disable the auto power management functions. 1 enable the auto power management functions. W83697UF/W83697UG PME interrupt due to MIDI's IRQ. PME interrupt due to MIDI's IRQ. PME output enable bit. PME will be generated ...
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... CR30 (Default 0x00) Bit [7:2]: Reserved. Bit 1: 1 Activate GPIO6. 0 GPIO6 is inactive Bit 0: 1 Activate URC. 0 URC is inactive. CR60, CR61 (Default 0x03, 0xE8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select the Serial Port 3 I/O base address [0x100:0xFF8] on 8yte boundary. W83697UF/W83697UG - 46 - ...
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... When set to a '0', the incoming/outgoing port value is the same as in data register. CRF4 (GP6 output style register. Default 0x00 ) When set to a '1', the outgoing port is pulse mode. When set to a '0', the outgoing port is level mode. W83697UF/W83697UG Publication Release Date: May 26, 2005 - 47 - Revision A1 ...
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... If a port is programmed output port, then its respective bit can be read/written port is programmed input port, then its respective bit can only be read. CRF3 (GP7 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. W83697UF/W83697UG - 48 - ...
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... PARAMETER Power Supply Voltage (5V) Input Voltage RTC Battery Voltage V BAT Operating Temperature Storage Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. W83697UF/W83697UG RATING -0.5 to 7.0 -0 +0.5 DD 2 +70 -55 to +150 ...
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... Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage I/O – 3.3V TTL level bi-directional pin with 12mA source-sink capability 12tp3 Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage W83697UF/W83697UG = 0V) SS SYM. MIN. TYP. MAX. I 2.4 BAT I 2 ...
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... +10 LIH I -10 LIL V 0.5 0.8 1 1.6 2.0 2 0 +10 LIH I -10 LIL - 51 - W83697UF/W83697UG UNIT CONDITIONS μ 3.3V IN μ = - μ μ = ...
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... LIH -10 LIL 1.5 IL 3.5 IH 0.4 OL +10 LIH -10 LIL 0.4 OL +10 LIH -10 LIL V 0.5 0.8 1.1 t- 1.6 2.0 2.4 t+ 0.5 1.2 TH 0.4 OL +10 LIH -10 LIL - 52 - W83697UF/W83697UG UNIT CONDITIONS μ μ μ μ μ μ ...
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... VTH Output Low Voltage VOL Input High Leakage ILIH Input Low Leakage ILIL I/OD24cs - CMOS level Schmitt-trigger bi-directional pin and open drain output with 24mA sink capability Input Low Threshold Vt- Voltage Input High Threshold Vt+ Voltage W83697UF/W83697UG MIN. TYP. MAX. V 0.5 0.8 1.1 t- 1.6 2.0 2.4 0.5 1.2 0.4 +10 -10 1.3 1.5 1 ...
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... O4 - Output pin with 4mA source-sink capability Output Low Voltage Output High Voltage O8 - Output pin with 8mA source-sink capability Output Low Voltage Output High Voltage O12 - Output pin with 12mA source-sink capability Output Low Voltage Output High Voltage W83697UF/W83697UG SYM. MIN. TYP. MAX ...
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... MIN. TYP. MAX +10 LIH I -10 LIL +10 LIH I -10 LIL +10 LIH - 55 - W83697UF/W83697UG UNIT CONDITIONS - - ...
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... Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INcu - CMOS level input pin with internal pull up resistor Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage W83697UF/W83697UG SYM. MIN. TYP. MAX. I -10 LIL V 0 ...
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... Input High Leakage Input Low Leakage IN - CMOS level Schmitt-trigger input pin with internal pull up resistor csu Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage W83697UF/W83697UG SYM. MIN. TYP. MAX +10 LIH I -10 ...
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... DCH2/PD4 18 RDD2/PD3 5 17 STEP2/SLIN 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram JP13 - 58 - W83697UF/W83697UG JP 13A DCH2 34 33 HEAD2 32 31 RDD2 30 29 WP2 28 27 TRK02 26 25 WE2 24 23 WD2 22 21 STEP2 20 19 DIR2 ...
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... STEP2/SLIN 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension 2FDD Connection Diagram 8.3 Four FDD Mode W83977F DSA DSB MOA MOB W83697UF/W83697UG JP13 74LS139 G1 1Y0 A1 1Y1 B1 1Y2 1Y3 2Y0 2Y1 G2 2Y2 2Y3 13A DCH2 34 33 HEAD2 ...
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... W83697UG 121G5BCV012345BA 1st line: Winbond logo 2nd line: the type number: W83697UF, W83697UG 3th line: the tracking code 121 CV012345BA 121 : packages made in 2001, week assembly house ID; A means ASE, S means SPIL, G means GR, .... etc Winbond internal use. ...
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... PACKAGE DIMENSIONS (128-pin PQFP 102 65 103 128 See Detail F y Seating Plane W83697UF/W83697UG Detail Dimension in mm Dimension in inch Symbol Min Nom Max Min Nom A 0.25 0.35 0.45 0.010 0.014 1 A 2.57 2.72 2.87 0.101 0.107 2 b 0.004 ...
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... XA11 XA12 XA13 VCC XA14 XA15 XA16 XA17 XA18 W83697UF C2 0.1u C3 0.1u R1 4.7K VCC3V LAD3 VCC3V LAD2 R2 4.7K LAD[0..3] LAD1 LAD0 R3 4.7K VCC - 62 - W83697UF/W83697UG XD0 XD1 XD2 XD3 XD[0..7] XD[0..7] XD4 XD5 XD6 XD7 XA0 XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XA9 XA[0..18] XA[0..18] IRTX U1 IR & ...
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... PD5 3 4 PD6 5 6 PD7 ERR# ACK# BUSY PE SLCT 180 180 180 C13 C14 180 180 W83697UF/W83697UG +12V VCC +12V +12V VCC +12V 5 NRTSB 16 5 NRTSC DY1 RTSC# DA1 DY1 6 NDTRB 15 6 NDTRC DY2 DTRC# DA2 ...
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... XA4 8 A4 XA3 9 A3 XA2 10 A2 R22 R23 R24 XA1 11 A1 4.7K 4.7K 4.7K XA0 VCC 31 MEMW# WE MEMR# OE# GND 22 ROMCS# CE# W29C020/40 W83697UF/W83697UG VCC VCC VCC VCC VCC R10 R7 INDUCTOR 2.2K 2.2K 2.2K 2. PRT C26 C27 C28 C29 0 ...
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... ISA ROM value Interface be IO clk Using Enable Using 24M OFF 2E default ISA ROM value Interface be IO clk W83697UF/W83697UG VCC - 65 - Winbond Electronic Corp. Title W83697SF Size Document Number B 697SD4.SCH Date: Thursday, August 30, 2001 Sheet 5 of Publication Release Date: May 26, 2005 ...
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... DEMO CIRCUIT VERSION CHANG NOTICE 2/26/2001 FIRST RELEASED W83697UF/W83697UG WINBOND ELECTRONICS CORP. Title Size B Date W83697SF Document Number Rev 697SD5.SCH 0.2 Thursday, August 30, 2001 Sheet ...
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... Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83697UF/W83697UG PAGE n.a. First Published New update ...