AT17LV512 ATMEL Corporation, AT17LV512 Datasheet
AT17LV512
Available stocks
Related parts for AT17LV512
AT17LV512 Summary of contents
Page 1
... Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable. ® ® ™ FLEX , APEX ® ® , Virtex FPGAs Table 1-1. The AT17LV series FPGA Configuration EEPROM Memory AT17LV65 AT17LV128 AT17LV256 AT17LV512 AT17LV010 AT17LV002 AT17LV040 3.3V and 5V System Support 2321I–CNFG–2/08 ...
Page 2
... The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-lead SOIC package is not available for the AT17LV512/010/002 devices possible to use an 8-lead LAP package instead. 2. The pinout for the AT17LV65/128/256 devices is not pin-for-pin compatible with the AT17LV512/010/002 devices ...
Page 3
... PLCC CLK 4 (2) (WP1 ) NC 5 (1) (WP ) RESET/OE 6 (2) (WP2 ) This pin is only available on AT17LV65/128/256 devices. 2. This pin is only available on AT17LV512/010/002 devices. 3. The CEO feature is not available on the AT17LV65 device. (1) 20-lead SOIC NC 1 DATA CLK RESET/ ...
Page 4
... AT17LV65/128/256/512/010/002/040 4 (1) 20-lead SOIC DATA CLK RESET/ This pinout only applies to AT17LV512/010/002 devices. 2. The CEO feature is not available on the AT17LV65 device. 44 TQFP (1) (WP1 ) ...
Page 5
... Figure 2-8. Block Diagram SER_EN (2) WP1 (2) WP2 POWER ON RESET Notes: 1. This pin is only available on AT17LV65/128/256 devices. 2. This pin is only available on AT17LV512/010/002 devices. 3. The CEO feature is not available on the AT17LV65 device. 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 (2) (1) READY 5 ...
Page 6
... GND 5 10 CEO READY O – – SER_EN Note: 1. The CEO feature is not available on the AT17LV65 device. AT17LV65/128/256/512/010/002/040 6 AT17LV512/ AT17LV010 8 20 DIP SOIC LAP PLCC SOIC – – 5 – – ...
Page 7
... WP2 WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations. This pin is only available on AT17LV512/010 devices. 4.7 CE Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver ...
Page 8
A2 Device selection input, A2. This is used to enable (or select) the device during programming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor. 4.11 READY Open collector reset state indicator. Driven Low during power-up reset, ...
Page 9
... The AT17LV series configurators enter a low-power standby mode whenever CE is asserted High. In this mode, the AT17LV65/128/256 configurator consumes less than 50 µA of current at 3.3V (100 µA for the AT17LV512/010 and 200 µA for the AT17LV002/040). The output remains in a high-impedance state regardless of the state of the OE input. ...
Page 10
Absolute Maximum Ratings* Operating Temperature................................... -40° +85° C Storage Temperature .................................... -65° +150° C Voltage on Any Pin with Respect to Ground ..............................-0. Supply Voltage (V ) .........................................-0.5V to +7.0V CC Maximum Soldering ...
Page 11
... IN CC Commercial Industrial AT17LV512/ AT17LV002/ AT17LV010 AT17LV040 Max Min Max Min V 2 0.8 0 0.8 0 2.4 2.4 0.4 0.4 2.4 2.4 0.4 0 -10 10 -10 50 100 100 100 AT17LV512/ AT17LV002/ AT17LV010 AT17LV040 Max Min Max Min V 2 0.8 0 0.8 0 3.86 3.86 0.32 0.32 3.76 3.76 0.37 0. -10 10 -10 75 200 150 200 Max Units ...
Page 12
AC Waveforms CE RESET/OE CLK T CE DATA 16. AC Waveforms when Cascading RESET/OE CE CLK T DATA LAST BIT T CEO AT17LV65/128/256/512/010/002/040 12 T SCE CAC CDF T OCK OCE T ...
Page 13
... Min Max Min AT17LV65/128/256 AT17LV512/010/002/040 Commercial Industrial Commercial Min Max Min Max Min Industrial Max Min Max Units ...
Page 14
... Max Min Max Min 12.5 12.5 AT17LV65/128/256 AT17LV512/010/002/040 Commercial Industrial Commercial Min Max Min Max Min Industrial Max Min Max Units ...
Page 15
... Thin Plastic Quad Flat 44A Package (TQFP) Notes: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site. 2. Airflow = 0 ft/min. 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 (1) AT17LV65/ AT17LV128/ AT17LV512/ AT17LV256 AT17LV010 θ [° C/ θ JA 115.71 (2) [° C/W] θ ...
Page 16
Figure 21-1. Ordering Code Voltage Size (Bits) 3.0V to 5.5V 65 128 256 512 010 002 040 8CN4 8-lead mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOID Packages 8P3 8-lead, 0.300" ...
Page 17
... AT17LV128-10NC AT17LV128-10JC AT17LV128-10SC AT17LV128-10PI AT17LV128-10NI AT17LV128-10JI AT17LV128-10SI AT17LV256-10PC AT17LV256-10NC AT17LV256-10JC AT17LV256-10SC AT17LV256-10PI AT17LV256-10NI AT17LV256-10JI AT17LV256-10SI AT17LV512-10PC AT17LV512-10JC AT17LV512-10PI AT17LV512-10JI AT17LV010-10PC AT17LV010-10JC AT17LV010-10PI AT17LV010-10JI AT17LV002-10JC AT17LV002-10JI (2)(3) Package Operation Range 8P3 Commercial 8S1 (0° 70° C) 20J 8P3 Industrial 8S1 (-40° 85° C) ...
Page 18
... AT17LV002-10TQU (1) 4-Mbit AT17LV040-10TQU Note: 1. For operating 5V operating voltage, please refer to the corresponding AC and DC Characteristics. AT17LV65/128/256/512/010/002/040 18 Ordering Code AT17LV256-10CU AT17LV256-10JU AT17LV256-10NU AT17LV256-10PU AT17LV256-10SU AT17LV512-10CU AT17LV512-10JU AT17LV010-10CU AT17LV010-10JU AT17LV010-10PU AT17LV002-10CU AT17LV002-10JU AT17LV002-10SU Package Operation Range 8CN4 20J 8S1 8P3 20S2 8CN4 20J ...
Page 19
Packaging Information 23.1 8CN4 – LAP Marked Pin1 Indentifier E Top View 0.10 mm TYP Bottom View Note: 1. Metal Pad Dimensions. 2. All exposed metal area shall have the following finished platings. ...
Page 20
PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with ...
Page 21
SOIC TOP VIEW e e SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 ...
Page 22
PLCC 1.14(0.045) X 45˚ B 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...
Page 23
SOIC 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 23 ...
Page 24
TQFP PIN 1 PIN 1 IDENTIFIER e C 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per ...
Page 25
Revision History Revision Level – Release Date H – March 2006 I – February 2008 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 History Added last-time buy for AT17LVXXX-10CC and AT17LVXXX-10CI. Removed -10SC, 10SI, -10TQC, -10TQI, -10BJC and -10BJI devices from ordering information. 25 ...
Page 26
... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...