W83977ATF-A Winbond, W83977ATF-A Datasheet
W83977ATF-A
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W83977ATF-A Summary of contents
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... W83977ATF WINBOND I/O ...
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... PS/2 mouse support, OnNow keyboard wake-up, OnNow mouse wake-up, and OnNow CIR wake-up. W83977ATF provides IR functions: IrDA 1.1 (MIR for 1.152M bps or FIR for 4M bps) and TV remote IR (Consumer IR, supporting NEC, RC-5, extended RC-5, and RECS-80 protocols). The disk drive adapter functions of W83977ATF include a floppy disk drive controller compatible with the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic ...
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... Programmable baud generator allows division of 1.8461 Mhz and 24 Mhz Maximum baud rate up to 921k bps for 14.769 Mhz and 1.5M bps for 24 Mhz SCI signal issued from any of the 13 IQRs pins or GPIO xx -2- W83977ATF PRELIMINARY 16 -1) Publication Release Date: April 1998 ...
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... General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watching dog timer output, power LED output, infrared I/O pins, general purpose address decoder, KBC control I/O pins Compatible with IEEE 1284 specification Compatible with IEEE 1284 specification TM -2, Phoenix MultiKey/42 1 dedicate, 22 optional Publication Release Date: April 1998 -3 - W83977ATF PRELIMINARY TM or customer code Revision 0.52 ...
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... OnNow Funtions Keyboard wake-up by programmable keys (patent pending) Mouse wake-up by programmable buttons (patent pending) CIR wake-up by programmable keys (patent pending) Package 128-pin PQFP W83977ATF Publication Release Date: April 1998 -4- PRELIMINARY Revision 0.52 ...
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... W83977ATF PRELIMINARY / / ...
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... System data bus bits 6-7. CPU I/O read signal. CPU I/O write signal. System address bus enable. In EPP Mode, this pin is the IO Channel Ready output to extend the host read/write cycle. Master Reset; Active high low during normal operations. -6- W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
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... Interrupt request 4. (Logical device 9, CRF1 bit General purpose I/O port 3 bit 2. (Logical device 9, CRF1 bit Interrupt request 5. (Logical device 9, CRF1 bit General purpose I/O port 3 bit 3. (Logical device 9, CRF1 bit W83977ATF PRELIMINARY SCI is driven low by the Publication Release Date: April 1998 Revision 0.52 ...
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... Alternate Function 1 from GP15: General purpose address write enable output. Alternate Function 2 from GP15: KBC P12 I/O port. Watch-Dog timer output. (CR2C bit 3_2 = 10 MHz clock input, selectable through CR24 bit 6. -8- W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
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... Consumer IR receiving input. (CR2A bit 5_4 = 00) General purpose I/O port 2 bit 5. (CR2A bit 3_2 = 10) Alternate Function from GP25: GATE A20. (KBC P21) FIR receiving input. (CR2A bit 3_2 = 00) IR module select 0. (CR2A bit 3_2 = 01 W83977ATF PRELIMINARY is driven low by (CR2A bit 5_4 = 01) Publication Release Date: April 1998 ...
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... Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. -10- W83977ATF PRELIMINARY is recommended if intends to is recommended if intends to resistor is recommended if resistor is Publication Release Date: April 1998 Revision 0 ...
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... EXTENSION FDD MODE: WD2 This pin is for Extension FDD B; its function is the same as the WD pin of FDC. EXTENSION 2FDD MODE: WD2 This pin is for Extension FDD A and B; its function is the same as the WD pin of FDC. -11 - W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
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... EXTENSION FDD MODE: HEAD2 This pin is for Extension FDD B; its function is the same as the HEADpin of FDC. EXTENSION 2FDD MODE: HEAD2 This pin is for Extension FDD A and B; its function is the same as the HEAD pin of FDC. -12- W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
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... This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output. -13 - W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
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... This pin is for Extension FDD B; its function is the same as the RDATA pin of FDC pulled high internally. EXTENSION 2FDD MODE: RDATA2 This pin is for Extension FDD A and B; its function is the same as the RDATA pin of FDC pulled high internally. -14- W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
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... ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: DSA2 This pin is for Extension FDD A; its function is the same as the DSA pin of FDC. -15 - W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
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... Diskette change. This signal is active low at power on and whenever the diskette is removed. This input pin is pulled up internally resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). -16- W83977ATF PRELIMINARY SCI is driven low by the Publication Release Date: April 1998 Revision 0.52 ...
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... General purpose I/O port 1 bit 2. (CR2A bit Alternate Function 1 from GP12 : Watchdog timer output. W83C45 KINH (P17) Input. (CR2B bit default) General purpose I/O port 1 bit 3. (CR2B bit -17 - W83977ATF PRELIMINARY resistor. The resistor can be resistor. The Publication Release Date: April 1998 ...
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... SYMBOL PIN I/O VBAT 64 NA XTAL1 XTAL2 FUNCTION +5V power supply for the digital circuitry. +5V stand-by power supply for the digital circuitry. Ground. FUNCTION Battery voltage input. 32.768Khz Clock Input. 32.768Khz Clock Output. -18- W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
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... FDC FUNCTIONAL DESCRIPTION 2.1 W83977ATF FDC The floppy disk controller of the W83977ATF integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports bits/sec data rate. ...
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... A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk. W83977ATF disabled, and command parameters must be sent ...
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... FDC Core The W83977ATF FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result. Command The microprocessor issues all required information to the controller to perform a specific operation. ...
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... HDS DS1 DS0 -22- W83977ATF PRELIMINARY D0 REMARKS 0 Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: April 1998 ...
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... HDS DS1 DS0 -23 - W83977ATF PRELIMINARY REMARKS 0 Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: April 1998 ...
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... HDS DS1 DS0 -24- W83977ATF PRELIMINARY REMARKS Command codes Sector ID information prior to command execution Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT Status information after command execution Sector ID information after ...
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... HDS DS1 DS0 HDS DS1 DS0 -25 - W83977ATF PRELIMINARY D0 REMARKS 0 Command codes The first correct ID information on the cylinder is stored in Data Register Status information after command execution Disk status after the command has been completed D0 REMARKS 0 Command codes ...
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... HDS DS1 DS0 -26- W83977ATF PRELIMINARY D0 REMARKS 0 Command code 0 Enhanced controller D0 REMARKS 1 Command codes Sector ID information prior to Command execution Data transfer between the FDD and system Status information after Command execution Sector ID information after ...
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... HDS DS1 DS0 -27 - W83977ATF PRELIMINARY REMARKS Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: April 1998 Revision 0.52 ...
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... DS1 DS0 -28- W83977ATF PRELIMINARY D0 REMARKS 1 Command codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters Status information after command execution D0 REMARKS 1 Command codes Head retracted to Track 0 Interrupt D0 REMARKS 0 Command code Status information at the end ...
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... HDS DS1 DS0 -29 - W83977ATF PRELIMINARY D0 REMARKS 1 Command codes D0 REMARKS 1 Command codes Head positioned over proper cylinder on diskette D0 REMARKS 1 Configure information 0 Internal registers written D0 REMARKS 1 Command codes Publication Release Date: April 1998 ...
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... LOCK HDS DS1 DS0 -30- W83977ATF PRELIMINARY D0 REMARKS 0 Registers placed in FIFO WG D0 REMARKS 0 Command Code D0 REMARKS 0 Command Code 0 D0 REMARKS 0 Command Code Status information about disk drive D0 REMARKS Invalid codes (no operation- FDC goes to ...
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... Register Descriptions There are several status, data, and control registers in W83977ATF. These registers are defined below: ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 7 2.2.1 Status Register A (SA Register) (Read base address + 0) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 ...
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... This bit indicates the value of DRQ output pin. STEP F/F (Bit 5): This bit indicates the complement of latched STEP output. TRAK0 (Bit 4): This bit indicates the complement of TRAK0 input DIR WP INDEX HEAD TRAK0 STEP F/F DRQ INIT PENDING -32- W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
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... This bit changes state at every rising edge of the RDATA output pin. WE (Bit 2): This bit indicates the complement of the WE output pin MOT EN A MOT RDATA Toggle WDATA Toggle Drive SEL0 -33 - W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
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... DSD (Bit 1): 0 Drive D has been selected 1 Drive D has not been selected DSC (Bit 0): 0 Drive C has been selected 1 Drive C has not been selected DSC DSD WE F/F RDATA F/F WD F/F DSA DSB -34- W83977ATF PRELIMINARY DRV2 Publication Release Date: April 1998 Revision 0.52 ...
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... Tape sel 0 Tape sel Tape Sel 0 Tape Sel 1 Floppy boot drive 0 Floppy boot drive 1 Drive type ID0 Drive type ID1 Media ID0 Media ID1 -35 - W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
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... DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor. -36- W83977ATF PRELIMINARY None 1 ...
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... S/W RESET PRECOMPENSATION DELAY 250K - 1 Mbps Default Delays 41.67 nS 83.34 nS 125.00 nS 166.67 nS 208.33 nS 250.00 nS 0.00 nS (disabled) DEFAULT PRECOMPENSATION DELAYS 125 nS 125 nS 125 nS 41.67nS 20.8 nS -37 - W83977ATF PRELIMINARY 2 Mbps Tape drive Default Delays 20.8 nS 41.17 nS 62.5nS 83.3 nS 104.2 nS 125.00 nS 0.00 nS (disabled) Publication Release Date: April 1998 Revision 0.52 ...
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... This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83977ATF, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. ...
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... During execution of the read data or scan command 0 No error Not used. This bit is always US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 WP Write Protected FT Fault -39 - W83977ATF PRELIMINARY RY Ready Publication Release Date: April 1998 Revision 0.52 ...
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... Reserved for the hard disk controller x During a read of this register, these bits are in tri-state DSKCHG -40- W83977ATF PRELIMINARY HIGH DENS DRATE0 DRATE1 DSKCHG DRATE0 DRATE1 NOPREC DMAEN DSKCHG Publication Release Date: April 1998 Revision 0.52 ...
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... This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC Reserved -41 - W83977ATF PRELIMINARY 0 DRATE0 DRATE1 DRATE0 DRATE1 NOPREC Publication Release Date: April 1998 Revision 0.52 ...
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... W83977ATF Data Sheet Revision History Pages 1 n.a. 53,54,58,63,64,65, 2 69,138.1,139 1,2,3,20,45,53,63, 3 65,99,103,150 4 112 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. ...
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... GENERAL PURPOSE I/O PORT...............................................................................................................9 1.3 SERIAL PORT INTERFACE...................................................................................................................10 1.4 INFRARED INTERFACE........................................................................................................................11 1.5 MULTI-MODE PARALLEL PORT .........................................................................................................11 1.6 FDC INTERFACE ...................................................................................................................................16 1.7 KBC INTERFACE...................................................................................................................................17 1.8 POWER PINS ..........................................................................................................................................18 1.9 ACPI INTERFACE..................................................................................................................................18 2.0 FDC FUNCTIONAL DESCRIPTION........................................................................19 2.1 W83977ATF FDC....................................................................................................................................19 2.1.1 AT interface.......................................................................................................................................19 2.1.2 FIFO (Data) ......................................................................................................................................19 2.1.3 Data Separator..................................................................................................................................20 2.1.4 Write Precompensation......................................................................................................................20 2.1.5 Perpendicular Recording Mode .........................................................................................................20 2.1.6 FDC Core..........................................................................................................................................21 2.1.7 FDC Commands ................................................................................................................................21 W83977ATF WINBOND I/O ...
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... Set0.Reg1 - Interrupt Control Register (ICR).....................................................................................53 4.2.3 Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR).......................................54 4.2.4 Set0.Reg3 - IR Control Register/Set Select Register (UCR/SSR): .......................................................57 4.2.5 Set0.Reg4 - Handshake Control Register (HCR) ................................................................................58 4.2.6 Set0.Reg5 - IR Status Register (USR).................................................................................................60 4.2.7 Set0.Reg6 - Reserved.........................................................................................................................60 4.2.8 Set0.Reg7 - User Defined Register (UDR/AUDR) ..............................................................................61 W83977ATF Publication Release Date:April 1998 -II - PRELIMINARY Revision 0.52 ...
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... SET6 - IR PHYSICAL LAYER CONTROL REGISTERS........................................................................74 4.8.1 Set6.Reg0 - Infrared Configure Register 2 (IR_CFG2).......................................................................74 4.8.2 Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width ..........................................................................75 4.8.3 Set6.Reg2 - SIR Pulse Width..............................................................................................................75 4.8.4 Set6.Reg3 - Set Select Register ..........................................................................................................76 4.8.5 Set6.Reg4 - High Speed Infrared Beginning Flag Number (HIR_FNU) .............................................76 W83977ATF Publication Release Date:April 1998 -III - PRELIMINARY Revision 0.52 ...
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... FIFO Mode) Mode = 110 .................................................................................................93 5.3.8 cnfgA (Configuration Register A) Mode = 111...................................................................................93 5.3.9 cnfgB (Configuration Register B) Mode = 111...................................................................................93 5.3.10 ecr (Extended Control Register) Mode = all ....................................................................................94 5.3.11 Bit Map of ECP Port Registers ........................................................................................................95 5.3.12 ECP Pin Descriptions......................................................................................................................96 5.3.13 ECP Operation ................................................................................................................................97 5.3.14 FIFO Operation...............................................................................................................................97 5.3.15 DMA Transfers ................................................................................................................................98 W83977ATF Publication Release Date:April 1998 -IV - PRELIMINARY Revision 0.52 ...
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... SMI TO SCI/SCI TO SMI AND BUS MASTER ....................................................................................114 9.2 POWER MANAGEMENT TIMER ........................................................................................................115 9.3 ACPI REGISTERS (ACPIRS)................................................................................................................116 9.3.1 Power Management 1 Status Register 1 (PM1STS1).........................................................................116 9.3.2 Power Management 1 Status Register 2 (PM1STS2).........................................................................117 9.3.3 Power Management 1 Enable Register 1(PM1EN1) .........................................................................118 9.3.4 Power Management 1 Enable Register 2 (PM1EN2) ........................................................................118 W83977ATF Publication Release Date:April 1998 -V - PRELIMINARY Revision 0.52 ...
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... LOGICAL DEVICE 2 (UART A) ¢) .....................................................................................................141 11.5 LOGICAL DEVICE 3 (UART B).........................................................................................................141 11.6 LOGICAL DEVICE 5 (KBC)...............................................................................................................142 11.7 LOGICAL DEVICE 6 (IR)...................................................................................................................143 11.8 LOGICAL DEVICE 7 (GP I/O PORT I)...............................................................................................144 11.9 LOGICAL DEVICE 8 (GP I/O PORT II) .............................................................................................148 11.10 LOGICAL DEVICE 9 (GP I/O PORT III) ..........................................................................................151 11.11 LOGICAL DEVICE A (ACPI) ...........................................................................................................154 W83977ATF Publication Release Date:April 1998 -VI - PRELIMINARY Revision 0.52 ...
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... ECP Parallel Port Reverse Timing ................................................................................................181 13.4 KBC.....................................................................................................................................................182 13.4.1 Write Cycle Timing........................................................................................................................182 13.4.2 Read Cycle Timing ........................................................................................................................182 13.4.3 Send Data to K/B...........................................................................................................................182 13.4.4 Receive Data from K/B ..................................................................................................................183 13.4.5 Input Clock....................................................................................................................................183 13.4.6 Send Data to Mouse.......................................................................................................................183 13.4.7 Receive Data from Mouse..............................................................................................................183 W83977ATF Publication Release Date:April 1998 -VII - PRELIMINARY Revision 0.52 ...
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... GPIO WRITE TIMING DIAGRAM .....................................................................................................184 13.6 MASTER RESET (MR) TIMING ........................................................................................................184 14.0 APPLICATION CIRCUITS....................................................................................185 14.1 PARALLEL PORT EXTENSION FDD................................................................................................185 14.2 PARALLEL PORT EXTENSION 2FDD..............................................................................................185 14.3 FOUR FDD MODE..............................................................................................................................186 15.0 ORDERING INFORMATION ...............................................................................186 16.0 HOW TO READ THE TOP MARKING ...............................................................186 W83977ATF Publication Release Date:April 1998 -VIII - PRELIMINARY Revision 0.52 ...
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... Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB) -42 - W83977ATF PRELIMINARY and, convert serial Publication Release Date: April 1998 Revision 0.52 ...
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... CTS DSR RI Falling Toggling Toggling Edge (TCTS) (TDSR) (FERI) Bit 0 Bit 1 Bit 2 Bit 0 Bit 1 Bit 2 Bit 8 Bit 9 Bit 10 -43 - W83977ATF PRELIMINARY Data RX Data RX Data Bit 3 Bit 4 Bit 5 TX Data TX Data TX Data Bit 3 Bit 4 Bit 5 HSR 0 0 Interrupt ...
Page 54
... RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI) -44 - W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
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... This register controls the pins of the UART used for handshaking peripherals such as modem, and controls the diagnostic mode of the UART Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable -45 - W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
Page 56
... CTS, Loopback RI input ( bit 2 of HCR) DCD . CTS toggling (TCTS) DSR toggling (TDSR) RI falling edge (FERI) DCD toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD) -46 - W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
Page 57
... Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before other bits of UFR are programmed FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB -47 - W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
Page 58
... Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR empty 1. TCTS = 1 2. TDSR = 1 3. FERI = 1 4. TDCD = 1 -48 - W83977ATF PRELIMINARY 0 if interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled Clear Interrupt ...
Page 59
... RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI) -49 - W83977ATF PRELIMINARY 16 -1. The output frequency of Publication Release Date: April 1998 Revision 0.52 ...
Page 60
... W83977ATF PRELIMINARY Error Percentage between desired and actual ** ** 0.18% 0.099 0.53 Publication Release Date: April 1998 Revision 0.52 ...
Page 61
... Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB) -42 - W83977ATF PRELIMINARY and, convert serial Publication Release Date: April 1998 Revision 0.52 ...
Page 62
... CTS DSR RI Falling Toggling Toggling Edge (TCTS) (TDSR) (FERI) Bit 0 Bit 1 Bit 2 Bit 0 Bit 1 Bit 2 Bit 8 Bit 9 Bit 10 -43 - W83977ATF PRELIMINARY Data RX Data RX Data Bit 3 Bit 4 Bit 5 TX Data TX Data TX Data Bit 3 Bit 4 Bit 5 HSR 0 0 Interrupt ...
Page 63
... RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI) -44 - W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
Page 64
... This register controls the pins of the UART used for handshaking peripherals such as modem, and controls the diagnostic mode of the UART Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable -45 - W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
Page 65
... CTS, Loopback RI input ( bit 2 of HCR) DCD . CTS toggling (TCTS) DSR toggling (TDSR) RI falling edge (FERI) DCD toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD) -46 - W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
Page 66
... Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before other bits of UFR are programmed FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB -47 - W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
Page 67
... Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR empty 1. TCTS = 1 2. TDSR = 1 3. FERI = 1 4. TDCD = 1 -48 - W83977ATF PRELIMINARY 0 if interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled Clear Interrupt ...
Page 68
... RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI) -49 - W83977ATF PRELIMINARY 16 -1. The output frequency of Publication Release Date: April 1998 Revision 0.52 ...
Page 69
... W83977ATF PRELIMINARY Error Percentage between desired and actual ** ** 0.18% 0.099 0.53 Publication Release Date: April 1998 Revision 0.52 ...
Page 70
... Each of these register sets has a common register, namely Sets Select Register (SSR), in order to switch to another register set. The summary description of these Sets is given below. Also, a superior traditional SIR function can be used with Set 1 Set 2 Set 3 Set 4 Set 5 Set 6 Set W83977ATF PRELIMINARY All in one Reg to Select SSR Publication Release Date:April 1998 Revision 0.52 ...
Page 71
... TX DMA channel is disabled, then the single DMA channel will be selected. Sets Description Register Description Receiver/Transmitter Buffer Registers Interrupt Control Register Interrupt Status or IR FIFO Control Register IR Control or Sets Select Register Handshake Control Register IR Status Register Handshake Status Register User Defined Register - 52 - W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.52 ...
Page 72
... MIR, FIR, Remote Controller: EHSRI/ETXURI - Enable USR Interrupt or Enable Transmitter Underrun Interrupt A write to 1 will enable USR interrupt or enable transmitter underrun interrupt ETXTHI EDMAI 0 Publication Release Date:April 1998 - 53 - W83977ATF PRELIMINARY EUSRI ETBREI ERDRI EUSRI/ ETBREI ERBRI TXURI Revision 0.52 ...
Page 73
... No Interrupt pending 1. OER = 1 2. PBER =1 3. NSER = 1 4. SBD = 1 1. RBR data ready 2. FIFO interrupt active level reached Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR empty - 54 - W83977ATF PRELIMINARY IID1 IID0 USR_I/ TXEMP_I RXTH_I FEND_I 0 0 ...
Page 74
... RBR time-out occurs if the receiver buffer register has valid data and is below the threshold level. Cleared to 0 when RBR is less than threshold level after reading RBR. Cleared to 0 when Frame Status FIFO is below the Publication Release Date:April 1998 - 55 - W83977ATF PRELIMINARY Revision 0.52 ...
Page 75
... Bit 0: This bit enables the 16550 (FIFO) mode of the IR. This bit should be set to logical 1 before other bits of UFR can be programmed. Bit 5 Bit 4 Bit TXFTL1 TXFTL0 0 (MSB) (LSB W83977ATF PRELIMINARY Bit 2 Bit 1 Bit 0 TXF_RST RXF_RST EN_FIFO TXF_RST RXF_RST EN_FIFO Publication Release Date:April 1998 Revision 0.52 ...
Page 76
... Size: 16-byte FIFO Threshold Level TX FIFO Threshold Level (FIFO Size: 16-byte Set, but IR Control Register can only be programmed in Set 0 and - 57 - W83977ATF PRELIMINARY (FIFO Size: 32-byte (FIFO Size: 32-byte Publication Release Date:April 1998 Revision 0.52 ...
Page 77
... XLOOP EN_IRQ TX_WT W83977ATF PRELIMINARY Selected Hex Set Value ¡Ð Set 0 ¡Ð Set1 0xE0 Set 2 0xE4 Set 3 0xE8 Set 4 0xEC Set 5 0xF0 Set 6 0xF4 Set ...
Page 78
... Low speed MIR (0.576M bps) 010 Advanced ASK-IR 011 Advanced SIR 100 High Speed MIR (1.152M bps) 101 FIR (4M bps) 110 Consumer IR 111 data W83977ATF PRELIMINARY When backward operation Reserved Reserved this prevents short queues of data Publication Release Date:April 1998 Revision 0.52 ...
Page 79
... Set to 1 when an attached CRC is erroneous. Bit 1, 0: OER - Overrun Error, RDR - RBR Data Ready Definitions are the same as legacy IR. 4.2.7 Set0.Reg6 - Reserved TBRE SBD NSER TBRE MX_LEX PHY_ERR CRC_ERR Publication Release Date:April 1998 - 60 - W83977ATF PRELIMINARY PBER OER RDR OER RDR Revision 0.52 ...
Page 80
... Set to 1 when one or more remote pulses are detected. Cleared to 0 when this register is read. Bit 5 Bit 4 Bit 3 Bit 5 Bit 4 Bit 3 RX_BSY/ LST_FE/ S_FEND RX_IP RX_PD W83977ATF PRELIMINARY Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 0 LB_SF RX_TO Publication Release Date:April 1998 Revision 0.52 ...
Page 81
... Interrupt Status or IR FIFO Control Register IR Control or Sets Select Register Handshake Control Register IR Status Register Handshake Status Register User Defined Register Advanced Mode DIS_BACK= ¡Ñ Bit 7~5 Bit Bit W83977ATF PRELIMINARY Legacy Mode DIS_BACK=0 - Bit Publication Release Date:April 1998 Revision 0.52 ...
Page 82
... Advanced Baud Rate Divisor Latch (High Byte) Advanced IR Control Register 1 Sets Select Register Advanced IR Control Register 2 Transmitter FIFO Depth Receiver FIFO Depth Bit 5 Bit 4 Bit 3 EN_LOU ALOOP D_CHSW DMATHL W83977ATF PRELIMINARY - Bit 2 Bit 1 Bit 0 DMA_F ADV_SL Publication Release Date:April 1998 Revision 0.52 ...
Page 83
... Function Description DMA request (DREQ) is forced inactive after 10.5us No effect DMA request. Bit 5 Bit 4 Bit 3 SSR5 SSR4 SSR3 W83977ATF PRELIMINARY RX FIFO Threshold (16/32-Byte Bit 2 Bit 1 Bit 0 SSR2 SRR1 SRR0 Publication Release Date:April 1998 Revision 0.52 ...
Page 84
... PR_DIV1 PR_DIV0 RX_FSZ1 RX_FSZ0 TX_FSZ1 TXFSZ0 Pre-divisor 13.0 1.625 6 FIFO Size 16-Byte 32-Byte Reserved TX FIFO Size 16-Byte 32-Byte Reserved - 65 - W83977ATF PRELIMINARY Bit 2 Bit 1 Bit Max. Baud Rate 115.2K bps 921.6K bps 230.4K bps 1.5M bps Publication Release Date:April 1998 Revision 0.52 0 ...
Page 85
... W83977ATF PRELIMINARY Error Percentage between desired and actual ** ** 0.18% 0.099 0.53 Publication Release Date:April 1998 Revision 0.52 ...
Page 86
... RXFD4 RXFD3 Register Description Advanced IR ID Mapped IR Control Register Mapped IR FIFO Control Register Sets Select Register Bit 5 Bit 4 Bit 3 SSR5 SSR4 SSR3 W83977ATF PRELIMINARY Bit 2 Bit 1 Bit 0 TXFD2 TXFD1 TXFD1 Bit 2 Bit 1 Bit 0 RXFD2 RXFD1 RXFD1 ...
Page 87
... Timer Value High Byte Infrared Mode Select Sets Select Register Transmitter Frame Length Low Byte Transmitter Frame Length High Byte Receiver Frame Length Low Byte Receiver Frame Length High Byte Publication Release Date:April 1998 - 68 - W83977ATF PRELIMINARY Bit 2 Bit 1 Bit 0 SSR2 SRR1 SRR0 0 ...
Page 88
... Bit 4 Bit IR_MSL1 IR_MSL0 Operation Mode Selected Legacy IR Legacy ASK-IR Legacy SIR Bit 5 Bit 4 Bit 3 SSR5 SSR4 SSR3 W83977ATF PRELIMINARY 12 Bit 2 Bit 1 Bit 0 TMR_TST EN_TMR 0 0 CIR Bit 2 Bit 1 SSR2 SRR1 SRR0 Publication Release Date:April 1998 Revision 0.52 -1 ms. ...
Page 89
... Flow Control Baud Rate Divisor Latch Register (High Byte) Flow Control Mode Operation Sets Select Register Infrared Configure Register Frame Status FIFO Register Receiver Frame Length FIFO Low Byte Receiver Frame Length FIFO High Byte - 70 - W83977ATF PRELIMINARY Bit 2 Bit 1 Bit 0 bit 2 bit 1 bit 0 ...
Page 90
... Bit 3 - FC_DSW Next Mode After Flow Control Occurred Receiver Channel Transmitter Channel Bit 5 Bit 4 Bit 3 SSR5 SSR4 SSR3 Publication Release Date:April 1998 - 71 - W83977ATF PRELIMINARY Bit 2 Bit 1 Bit 0 EN_FD EN_BRFC EN_FC Bit 2 Bit 1 Bit 0 SSR2 SRR1 SRR0 Revision 0.52 ...
Page 91
... Reset Value 0 0 Bit 5 Bit 4 Bit 3 FEND_M AUX_RX - Status FIFO Threshold Level 2 4 Bit 5 Bit 4 Bit 3 - MX_LEX PHY_ERR CRC_ERR RX_OV W83977ATF PRELIMINARY Bit 2 Bit 1 Bit 0 - IRHSSL IR_FULL Bit 2 Bit 1 Bit 0 FSF_OV Publication Release Date:April 1998 Revision 0.52 ...
Page 92
... This bit is in frame status FIFO bottom and is valid only when Bit 5 Bit 4 Bit 6 Bit 5 Bit Bit W83977ATF PRELIMINARY Bit 3 Bit 2 Bit 1 Bit 3 Bit 2 Bit Bit 11 Bit 10 Bit Publication Release Date:April 1998 Revision 0 ...
Page 93
... Modulation Mode IRTX modulate 500K Hz Square Wave Re-rout IRTX Demodulation Mode Demodulation 500K Hz Re-rout IRRX CRC Type 16-bit CRC 32-bit CRC CRC Type 16-bit CRC 32-bit CRC - 74 - W83977ATF PRELIMINARY - - - Bit 2 Bit 1 Bit 0 INV_CRC DIS_CRC - Publication Release Date:April 1998 Revision 0.52 ...
Page 94
... MIR Output Width (0.576M bps 20.83 ns 41.66 (==20.83*2) ns ... 20.83 ... 645 ns Bit 5 Bit 4 Bit 3 - S_PW4 S_PW3 0 0 SIR Output Pulse Width 3/16 bit time of IR 1 W83977ATF PRELIMINARY Bit 2 Bit 1 Bit 0 M_PW2 M_PW1 M_PW0 41.66 ns 83.32 (==41.66*2) ns ... 41.66 ... 1290 ns Bit 2 Bit 1 S_PW2 S_PW1 S_PW0 ...
Page 95
... SSR3 Bit 5 Bit 4 Bit 3 M_FG1 M_FG0 F_FL3 M_FG3~0 1000 1 1001 1010 3 1011 4 1100 5 1101 6 1110 8 1111 - 76 - W83977ATF PRELIMINARY Bit 2 Bit 1 Bit 0 SSR2 SRR1 SRR0 Bit 2 Bit 1 Bit 0 F_FL2 F_FL1 F_FL0 Beginning Flag Number Reserved Publication Release Date:April 1998 Revision 0 ...
Page 96
... Sets Select Register Infrared Module (Front End) Select 1 Infrared Module Select 2 Infrared Module Select 3 Infrared Module Control Register Bit 5 Bit 4 Bit 3 RX_FR0 RX_FSL4 RX_FSL3 RX_FSL2 RX_FSL1 RX_FSL0 W83977ATF PRELIMINARY Beginning Flag Number (Default Reserved Bit 2 Bit 1 ...
Page 97
... RX_FSL4~0 00011 01000 01011 Note that those unassigned combinations are reserved. RX_FR2~0 (Low Frequency) 010 Max. Min. Max. 29.6 24.7 31.7 32.0 26.7 34.3 33.3 27.8 35.7 34.0 28.4 36.5 35.6 29.6 38.1 36.4 30.3 39.0 37.2 31.0 39.8 38.1* 31.7 40.8 39.0 32.5 41.8 41.0 34.2 44.0 42.1 35.1 45.1 43.2 36.0 46.3 45.7 38.1 49.0 47.1 39.2 50.4 48.5 40.4 51.9 50.0 41.7 53.6 51.6 43.0 55.3 55.2 46.0 59.1 57.1 47.6 61.2 61.5 51.3 65.9 RX_FR2~0 (High Frequency) 001 Min. 355.6 380.1 410 W83977ATF PRELIMINARY 011 Min. Max. 23.4 34.2 25.3 36.9 26.3 38.4 26.9 39.3 28.1 41.0 28.7 42.0 29.4 42.9 30.1 44.0 30.8 45.0 32.4 47.3 33.2 48.6 34.1 49.9 36.1 52n.7 37.2 54.3 38.3 56.0 39.5 57.7 40.7 59.6 43.6 63.7 45.1 65.9 48.6 71.0 Max. 457.1 489.8 527.4 Publication Release Date:April 1998 Revision 0.52 ...
Page 98
... Bit 4 Bit Low Frequency 10.6 s Low Frequency 30K Hz 31K HZ ... 56K Hz High Frequency 400K Hz 450K Hz 480K W83977ATF PRELIMINARY 101 110 400.0 685.6 384.0 738.5 Bit 2 Bit 1 Bit High Frequency 0.7 s 0.8 s 0.9 s 1.0 s Publication Release Date:April 1998 ...
Page 99
... Bit value Selected Frequency 30K ~ 56K Hz 400K ~ 480K Hz Selected Frequency 30K ~ 56K Hz 400K ~ 480K Hz Demodulation Mode Enable internal decoder Disable internal decoder - 80 - W83977ATF PRELIMINARY Bit 2 Bit 1 Bit 0 RX_DM TX_MM1 TX_MM0 Publication Release Date:April 1998 Revision 0.52 ...
Page 100
... Reserved. Bit 5 Bit 4 Bit 3 Bit 5 Bit 4 Bit Bit 5 Bit 4 Bit 3 - AIR_SL2 AIR_SL1 AIR_SL0 Publication Release Date:April 1998 - 81 - W83977ATF PRELIMINARY Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit Bit 2 Bit 1 Bit Revision 0.52 ...
Page 101
... IR_SL2~0, respectively. Bit 5 Bit 4 Bit 3 - MIR_SL2 MIR_SL1 MIR_SL0 These values will be automatically loaded to IR_SL2~0, Bit 5 Bit 4 Bit 3 - HRC_SL2 HRC_SL1 HRC_SL0 Publication Release Date:April 1998 - 82 - W83977ATF PRELIMINARY Bit 2 Bit 1 Bit Bit 2 Bit 1 Bit Revision 0.52 ...
Page 102
... RXINV TXINV Receiver Pin selected IRRX (Low/High Speed) IRRXH (High Speed) Function IRRXH (I/P) IRSL0 (O/P) AUX_RX High Speed Publication Release Date:April 1998 - 83 - W83977ATF PRELIMINARY Bit 2 Bit 1 Bit Selected IR Pin X IRRX X IRRXH 0 IRRX 1 IRRXH X IRRX X Reserved ...
Page 103
... Printer Interface Logic The parallel port of the W83977ATF makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83977ATF supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD) on the parallel port ...
Page 104
... GENERAL PURPOSE I/O W83977ATF provides 23 Input/Output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. These 23 GP I/O ports are divided into three groups; the first group contains 8 ports, the second group contains only 7 ports, and the third group contains 8 ports ...
Page 105
... Bit 0: IPD (Immediate Power Down). When set will put the whole chip into power down mode immediately. CR24 (Default 0b1s000s0s) Bit 7: EN16SA = 0 12 bit Address Qualification = 1 16 bit Address Qualification 0x74 (read only). Publication Release Date: Auguest 1997 -133 - W83977ATF PRELIMINARY Revision 0.51 ...
Page 106
... TYP. MAX. 2.4 BAT 2.0 BAT V 0.8 IL 2.0 IH 0.4 OL 2.4 OH +10 LIH I -10 LIL V 0.8 IL 2.0 IH 0.4 OL 2.4 OH +10 LIH I -10 LIL 161- W83977ATF PRELIMINARY UNIT V +0 UNIT CONDITIONS 2.5 V BAT 5.0 V, All ACPI pins are SB not connected ...
Page 107
... Input Low Leakage I LIL MIN. TYP. MAX. 0.3xV DD 0.7xV DD 0.4 3 0.3xV DD 0.7xV DD 0.4 3 0.3xV DD 0.7xV DD 0.4 3 0.3xV DD 0.7xV DD 0.4 3 162- W83977ATF PRELIMINARY UNIT CONDITIONS ...
Page 108
... IH Input High Leakage I LIH Input Low Leakage I LIL MIN. TYP. MAX. 0.8 2.0 0.4 2 0.8 2.0 0.4 2 0.4 2.4 0.4 2.4 0.4 0.4 0.8 2.0 +10 -10 Publication Release Date: April 1998 163- W83977ATF PRELIMINARY UNIT CONDITIONS ...
Page 109
... IL V 0.7xV LIH I LIL V 0.5 0 1.6 2 0.5 1 LIH I LIL V 0.5 0 1.6 2 0.5 1 LIH I LIL 164- W83977ATF PRELIMINARY MAX. UNIT CONDITIONS + - ...
Page 110
... MCY 260/430 AA /510 165- W83977ATF PRELIMINARY TYP. MAX. UNIT (NOTE 360/570 nS /675 360/570 nS /675 Publication Release Date: April 1998 ...
Page 111
... TC /260 T 1.8/3/3. RST T 0.5/0.9 IDX T 1.0/1.6 DST T 24/40/48 STD T 6.8/11.5 STP /13.8 T Note 100/185 WDD /225 T 100/138 WPC /225 166- W83977ATF PRELIMINARY TYP. MAX. (NOTE 1) 6/12 /20/24 5 /1.0 /2.0 7/11.7 7.2/11.9 /14 /14.2 Note 2 Note 2 125/210 150/235 /250 /275 125/210 150/235 /250 /275 Publication Release Date: April 1998 Revision 0.52 UNIT ...
Page 112
... T 100 pF Loading MWO T SIM T RIM T 100 pF Loading IAD T 100 pF Loading IID N 100 pF Loading SYM. MIN 200 t5 Publication Release Date: April 1998 167- W83977ATF PRELIMINARY MIN. MAX. UNIT 9/16 Baud Rate 1 S 1/16 8/16 Baud Rate 175 nS 9/16 16/16 Baud Rate 1/2 Baud Rate 250 nS 200 ...
Page 113
... Command Asserted to PD Valid Command Deasserted to PD Hi-Z WAIT Deasserted to PD Drive WRITE Deasserted to Command PBDIR Set to Command PD Hi-Z to Command Asserted Asserted to Command Asserted WAIT Deasserted to Command Deasserted Time out PD Valid to WAIT Deasserted PD Hi-Z to WAIT Deasserted W83977ATF SYM. MIN ...
Page 114
... IOW Asserted to PD Valid WAIT Asserted to PD Invalid PD Invalid to Command Asserted IOW to Command Asserted WAIT Asserted to Command Asserted WAIT Deasserted to Command Deasserted Command Asserted to WAIT Deasserted Time out Command Deasserted to WAIT Asserted IOW Deasserted to WRITE Deasserted and PD invalid W83977ATF SYM. MIN ...
Page 115
... Asserted to BUSY Asserted BUSY Asserted to nSTROBE Deasserted 12.3.8 ECP Parallel Port Reverse Timing Parameters PARAMETER PD Valid to nACK Asserted nAUTOFD Deasserted to PD Changed nAUTOFD Asserted to nACK Asserted nAUTOFD Deasserted to nACK Deasserted nACK Deasserted to nAUTOFD Asserted PD Changed to nAUTOFD Deasserted W83977ATF SYMBOL MIN. t1 600 t2 600 t3 450 t4 ...
Page 116
... Time from inactive CLK transition, used to time when the auxiliary device sample DATA T25 Time of inhibit mode T26 Time from rising edge of CLK to DATA transition T27 Duration of CLK inactive T28 Duration of CLK active T29 Time from DATA transition to falling edge of CLK W83977ATF MIN ...
Page 117
... GPIO Timing Parameters SYMBOL t Write data to GPIO update WGO t SWITCH pulse width SWP Note : Refer to Microprocessor Interface Timing for Read Timing. PARAMETER 172- W83977ATF PRELIMINARY MIN. MAX. UNIT 300(Note msec Publication Release Date: April 1998 Revision 0.52 ...
Page 118
... IOR TMW (IOW) TMR (IOR) TRA TRR TDH TDF TR TWA TWW TWD TDW TWI DIR TMCY TAA TMRW STEP 173- W83977ATF PRELIMINARY Write Date WD TWDD Index INDEX TIDX TIDX Terminal Count TC TTC Reset RESET TRST Drive Seek operation TSTP TDST TSTD ...
Page 119
... SERIAL OUT (SOUT) THRS IRQ3 or IRQ4 THR IOW (WRITE THR) IOR (READ TIR) Receiver Timing STAR DATA BITS (5-8) PARITY Transmitter Timing STAR DATA (5-8) PARITY THR TSI 174- W83977ATF PRELIMINARY STOP TSINT TRINT STAR STOP (1-2) TSTI TIR Publication Release Date: April 1998 Revision 0.52 ...
Page 120
... Printer Interrupt Timing ¢x ¢x ¢x ¢x ¡ö ¢x TLAD ¢x ¢x ¢x ¢x ¢x ¢x 175- W83977ATF PRELIMINARY ¢x ¢x ¢x ¡÷ ¡ö TMWO ¢x ¢x ¢x ¢x ¢x ¡ö TSIM ¢x ¢x ¢x ¢ ...
Page 121
... Parallel Port 13.3.1 Parallel Port Timing IOW INIT, STROBE AUTOFD, SLCTIN PD<0:7> ACK IRQ (SPP) IRQ (EPP or ECP) nFAULT (ECP) ERROR (ECP) IRQ Publication Release Date: April 1998 176- W83977ATF PRELIMINARY t3 t4 Revision 0.52 ...
Page 122
... EPP Data or Address Read Cycle (EPP Version 1.9) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 PD<0:7> t22 t23 t24 ADDRSTB DATASTB WAIT t18 t17 t21 t25 t27 t26 177- W83977ATF PRELIMINARY t15 t19 t20 t28 Publication Release Date: April 1998 Revision 0.52 ...
Page 123
... EPP Data or Address Write Cycle (EPP Version 1.9) A10-A0 SD<0:7> t1 IOW IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT PBDIR t10 t11 t13 t15 t16 t17 t19 t20 t22 178- W83977ATF PRELIMINARY t12 t14 t18 t21 Publication Release Date: April 1998 Revision 0.52 ...
Page 124
... EPP Data or Address Read Cycle (EPP Version 1.7) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 PD<0:7> t22 t23 ADDRSTB t24 DATASTB WAIT t18 t17 t21 t25 t26 t27 179- W83977ATF PRELIMINARY t15 t19 t20 t28 Publication Release Date: April 1998 Revision 0.52 ...
Page 125
... IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT 13.3.6 Parallel Port FIFO Timing PD<0:7> nSTROBE BUSY t10 t11 t13 t15 t16 t17 t18 t19 t20 t1 t2 >| > t6 >| 180- W83977ATF PRELIMINARY t22 t22 t4 >| t3 >| t5 >| Publication Release Date: April 1998 Revision 0.52 ...
Page 126
... ECP Parallel Port Forward Timing nAUTOFD PD<0:7> nSTROBE BUSY 13.3.8 ECP Parallel Port Reverse Timing PD<0:7> nACK nAUTOFD 181- W83977ATF PRELIMINARY Publication Release Date: April 1998 Revision 0.52 ...
Page 127
... RDB D0-D7 13.4.3 Send Data to K/B CLOCK (KCLK) T12 SERIAL DATA START (KDAT ACTIVE T7 DATA ACTIVE T10 T11 DATA OUT T14 T13 T19 182- W83977ATF PRELIMINARY T17 T18 T16 D7 P STOP Publication Release Date: April 1998 Revision 0.52 ...
Page 128
... Receive Data from Mouse MCLK T29 MDAT START T14 T13 T23 T24 T22 T26 T27 T28 183- W83977ATF PRELIMINARY STOP D7 P STOP Bit D7 P STOP Bit Publication Release Date: April 1998 Revision 0.52 ...
Page 129
... GPIO Write Timing Diagram A0-A15 IOW D0-7 GPIO10-17 GPIO20-25 13.6 Master Reset (MR) Timing Vcc MR VALID VALID PREVIOUS STATE tVMR 184- W83977ATF PRELIMINARY VALID tWGO Publication Release Date: April 1998 Revision 0.52 ...
Page 130
... DCH2/PD4 18 RDD2/PD3 5 17 STEP2/SLIN 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension 2FDD Connection Diagram JP13 JP13 185- W83977ATF PRELIMINARY JP 13A DCH2 34 33 HEAD2 32 31 RDD2 30 29 WP2 28 27 TRK02 26 25 WE2 24 23 WD2 22 21 STEP2 20 19 ...
Page 131
... W83977ATF-A AM. MEGA. 87-96 719AC27039520 1st line: Winbond logo 2nd line: the type number: W83977ATF-A 3rd line: the source of KBC F/W -- American Megatrends Incorporated 4th line: Tracking code 719 7039530 719: packages made in '97, week 19 A: assembly house ID; A means ASE, S means SPIL B: IC revision ...
Page 132
... Detail F Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 187- W83977ATF PRELIMINARY Dimension in mm Dimension in inch Symbol Min Nom Max Min Nom Max A 0.25 0.35 0.45 0.010 0.014 ...
Page 133
... Enable IR legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ = 1 Disable IR legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ PNPCSV The corresponding power-on Publication Release Date: Auguest 1997 -134 - W83977ATF PRELIMINARY must be complementary PNPCSV to 0 PNPCSV is 1. Revision 0.51 ...
Page 134
... Reserved = 101 External FDC Mode = 110 Reserved = 111 External two FDC Mode CR2A (Default 0x00) Bit 7: PIN57S = 0 KBRST = 1 GP12 Bit 6: PIN56S = 0 GA20 = 1 GP11 Bit PIN40S1, PIN40S0 = 00 CIRRX = 01 GP24 = 10 8042 P13 = 11 Reserved Publication Release Date: Auguest 1997 -135 - W83977ATF PRELIMINARY Revision 0.51 ...
Page 135
... KBLOCK = 1 GP13 CR2C (Default 0x00) Bit PIN121S1, PIN121S0 = 00 DRQ0 = 01 GP17 = 10 8042 P14 = 11 SCI Bit PIN119S1, PIN119S0 = 00 NDACK0 = 01 GP16 = 10 8042 P15 = 11 Reserved Bit PIN104S1, PIN104S0 = 00 IRQ15 = 01 GP15 = 10 WDTO = 11 Reserved Publication Release Date: Auguest 1997 -136 - W83977ATF PRELIMINARY Revision 0.51 ...
Page 136
... The internal pull-up resistors of FDC are turned on.(Default The internal pull-up resistors of FDC are turned off during POR, default 0x00 otherwise) if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise during POR, default 0x00 otherwise during POR, default 0x04 otherwise) Publication Release Date: Auguest 1997 -137 - W83977ATF PRELIMINARY Revision 0.51 ...
Page 137
... Forced to logic Forced to logic 0) Bit 1: DISFDDWR = 0 Enable FDD write Disable FDD write(forces pins WE, WD stay high). Bit 0: SWWP = 0 Normal, use WP to determine whether the FDD is write protected or not FDD is always write-protected. Publication Release Date: Auguest 1997 -138 - W83977ATF PRELIMINARY Revision 0.51 ...
Page 138
... When FDD is in enhanced 3-mode(CRF0.bit0=1),these bits determine SELDEN value in TABLE A of CRF4 and CRF5 as follows. DTYPE1 DPYTE0 Note: X means don't care. DRATE1 DRATE0 SELDEN Publication Release Date: Auguest 1997 - 138.1 - W83977ATF PRELIMINARY Revision 0.51 ...
Page 139
... DRVDEN1(pin 3) SELDEN DRATE0 DRATE1 DRATE0 DRATE0 SELDEN DRATE0 DRATE1 - 139 - W83977ATF PRELIMINARY SELDEN FM CRF0 bit 0=0 --- 1 250K 1 150K 0 125K 0 --- 1 250K 1 250K 0 125K 0 --- 1 250K 1 --- 0 125K 0 DRIVE TYPE 4/2/1 MB 3.5 ”“ ...
Page 140
... ECP and EPP - 1.9 mode = 111 ECP and EPP - 1.7 mode during POR, default 0x00 otherwise) if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) (all modes supported, EPP is only available when the base = 0 during POR, default 0x00 otherwise) - 140 - W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.52 ...
Page 141
... POR, default 0x00 otherwise) if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise during POR, default 0x00 otherwise during POR, default 0x00 otherwise) if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise during POR, default 0x00 otherwise) - 141 - W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.52 ...
Page 142
... Select 8MHz as KBC clock input Select 12Mhz as KBC clock input Select 16Mhz as KBC clock input. Bit Reserved. Bit Port 92 disable Port 92 enable. if PENKBC= 1 during POR, default 0x00 otherwise) if PENKBC= 1 during POR, default 0x00 otherwise) - 142 - W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.52 ...
Page 143
... DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04-0x07 No DMA active CR75 (Default 0x04) Bit 7-3 : Reserved. Bit 2-0 : These bits select DRQ resource for TX of UART C. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04-0x07 No DMA active . Publication Release Date:April 1998 - 143 - W83977ATF PRELIMINARY Revision 0.52 ...
Page 144
... GP15 alternate function (General Purpose Write Decode). CR70 (Default 0x00) Bit Reserved. Bit These bits select IRQ resource for GP10 as you set GP10 alternate function (Interrupt Steering). Publication Release Date:April 1998 - 144 - W83977ATF PRELIMINARY Revision 0.52 ...
Page 145
... Bit 0: In/Out selection Input Output. CRE2 (GP12, Default 0x01) Bit Reserved. Bit Select Function Select Basic I/O function Select 1st alternate function Reserved = 11 Reserved GP11 alternate function Watch Dog Timer Output. Publication Release Date:April 1998 - 145 - W83977ATF PRELIMINARY Revision 0.52 ...
Page 146
... Bit 2: Reserved. Bit 1: Polarity: 1: Invert Invert Bit 0: In/Out: 1: Input, 0: Output CRE6 (GP16, Default 0x01) Bit Reserved. Bit Select Function Select Basic I/O function Select 1st alternate function Reserved Watch Dog Timer Output. Publication Release Date:April 1998 - 146 - W83977ATF PRELIMINARY Revision 0.52 ...
Page 147
... If the logical device's activate bit is not set then bit 0 and 1 have no effect. WDT_CTRL1 BIT[ Publication Release Date:April 1998 - 147 - W83977ATF PRELIMINARY POWER LED STATE 1 Hertz Toggle pulse Continuous high or low* Continuous high or low* 1 Hertz Toggle pulse Revision 0.52 ...
Page 148
... Select Basic I/O function = 01 Reserved = 10 Select 2nd alternate function: Keyboard P13 I Reserved Bit 2: Int Enable Common IRQ = 0 Disable Common IRQ Bit 1: Polarity: 1: Invert Invert Bit 0: In/Out: 1: Input, 0: Output GP20~GP26 Publication Release Date:April 1998 - 148 - W83977ATF PRELIMINARY at Logic Device 8. Revision 0.52 ...
Page 149
... Bit Select Function Select Basic I/O function = 01 Reserved = 10 Select 2nd alternate function: Keyboard P16 I Reserved Bit 2: Int Enable Common IRQ = 0 Disable Common IRQ Bit 1: Polarity: 1: Invert Invert Bit 0: In/Out: 1: Input, 0: Output Publication Release Date:April 1998 - 149 - W83977ATF PRELIMINARY Revision 0.52 ...
Page 150
... Time-out Disable = 0x01 Time-out occurs after 1 minute = 0x02 Time-out occurs after 2 minutes = 0x03 Time-out occurs after 3 minutes ................................................ = 0xFF Time-out occurs after 255 minutes Watch Dog Timer Time-out value, but can Counter. Publication Release Date:April 1998 - 150 - W83977ATF PRELIMINARY Watch Dog Counter Revision 0.52 ...
Page 151
... These two registers select GP32 alternate function Primary I/O base address [0x100:0xFFE byte boundary; they are available as you set GP32 alternate function (General Purpose Address Decode). Timer time-out event; this bit is self-clearing. Timer Status). The ORed signal is self-clearing. - 151 - W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.52 ...
Page 152
... Bit 4: IRQ Filter Select = 1 Debounce Filter Enabled = 0 Debounce Filter Bypassed Bit 3: Select Function Select Alternate Function: Interrupt Steering Select Basic I/O Function. Bit 2: Reserved. Bit 1: Polarity Invert Invert. Bit 0: In/Out selection Input Output. Publication Release Date:April 1998 - 152 - W83977ATF PRELIMINARY Revision 0.52 ...
Page 153
... Bit 0: In/Out: 1: Input, 0: Output CRE6 (GP36, Default 0x01) Bit Reserved. Bit 1: Polarity: 1: Invert Invert Bit 0: In/Out: 1: Input, 0: Output CRE7 (GP37, Default 0x01) Bit Reserved. Bit 1: Polarity: 1: Invert Invert Bit 0: In/Out: 1: Input, 0: Output Publication Release Date:April 1998 - 153 - W83977ATF PRELIMINARY Revision 0.52 ...
Page 154
... Bit 6: ENKBWAKEUP. Enable Keyboard to wake-up system via = 0 Disable Keyboard wake-up function Enable Keyboard wake-up function. Bit 5: ENMSWAKEUP. Enable Mouse to wake-up system via = 0 Disable Mouse wake-up function Enable Mouse wake-up function. SCI . PANSWOUT . PANSWOUT . PANSWOUT PANSWOUT Publication Release Date:April 1998 - 154 - W83977ATF PRELIMINARY . . Revision 0.52 ...
Page 155
... CRE4 This Register is reserved for test. CRE5 (Default 0x00) Bit 7: Reserved. Bit 6-0: Compared Code Length. When the compared codes are storage in the data register, these data length should be written to this register. PANSWOUT PANSWIN . This bit is cleared by Publication Release Date:April 1998 - 155 - W83977ATF PRELIMINARY . Revision 0.52 ...
Page 156
... CRF0.bit7 (CHIPPME) is also set to 1. Bit 0: URBPME. UART B power management enable disable the auto power management functions enable the auto power management functions provided CRF0.bit7 (CHIPPME) is also set to 1. power management enable. - 156 - W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.52 ...
Page 157
... UART B is now in the sleeping state due to no UART A access, no IRQ, the receiver is now waiting for a start bit, the transmitter shift register is now empty, and no transition on MODEM control input lines in a preset expiry time period. Publication Release Date:April 1998 - 157 - W83977ATF PRELIMINARY Revision 0.52 ...
Page 158
... Bit 7: Reserved. Return zero when read. Bit 6: IRIRQSTS. IR IRQ status. Bit 5: MOUIRQSTS. MOUSE IRQ status. Bit 4: KBCIRQSTS. KBC IRQ status. Bit 3: PRTIRQSTS. printer port IRQ status. Bit 2: FDCIRQSTS. FDC IRQ status. Publication Release Date:April 1998 - 158 - W83977ATF PRELIMINARY bit is set Revision 0.52 ...
Page 159
... IRQ. SMI interrupt due to printer port's IRQ. SMI interrupt due to FDC's IRQ. SMI interrupt due to FDC's IRQ. SMI interrupt due to UART A's IRQ. SMI interrupt due to UART A's IRQ. Publication Release Date:April 1998 - 159 - W83977ATF PRELIMINARY SMI logic output Revision 0.52 ...
Page 160
... IRQ status bit in CRF3 is set and no SMI interrupt is generated on the pin SMI . = 0 Disable SMI = 1 Enable SMI CRFE, FF (Default 0x00) Reserved. Reserved for Winbond test. SMI interrupt due to UART B's IRQ. SMI interrupt due to UART B's IRQ. Publication Release Date:April 1998 - 160 - W83977ATF PRELIMINARY Revision 0.52 ...
Page 161
... W83977ATF Figure 7.2 Figure 7.3 Publication Release Date:April 1998 -105 - PRELIMINARY Revision 0.53 ...
Page 162
... Non-inverted output bit value of GP2 drive to Common Interrupt 1 Inverted output bit value of GP2 drive to Common Interrupt 0 Basic non-inverting input 1 Basic inverting input 0 Non-inverted input drive to Common Interrupt 1 Inverted input drive to Common Interrupt Publication Release Date:April 1998 -106 - W83977ATF PRELIMINARY Common Revision 0.53 ...
Page 163
... BIT 6 GP16 BIT 7 GP17 BIT 0 GP20 BIT 1 GP21 BIT 2 GP22 BIT 3 GP23 BIT 4 GP24 BIT 5 GP25 BIT 6 GP26 BIT 0 GP30 BIT 1 GP31 BIT 2 GP32 BIT 3 GP33 BIT 4 GP34 BIT 5 GP35 BIT 6 GP36 BIT 7 GP37 - - W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.53 ...
Page 164
... ALTERNATE FUNCTION can be programmed to map their own interrupt channels. The configuration registers CR70 and CR72 of logical device 7 -108 - W83977ATF PRELIMINARY GP I/O ports. Table Publication Release Date:April 1998 Revision 0.53 ...
Page 165
... GP14 and at CR62-65 of logical device output is normally active low. Users can alter its polarity GP32, and GP33's configuration register. -109 - W83977ATF PRELIMINARY POWER LED STATE 1 Hertz Toggle pulse Continuous high or low * Continuous high or low * 1 Hertz Toggle pulse registers. ...
Page 166
... W83977ATF uses Compatible PNP protocol to access configuration registers for setting up different W83977ATF, there are nine Logical Devices ( Logical Device A, individual functions: (logical device 3), KBC (logical device 5), IR (logical device 6), GPIO1 (logical device 7), GPIO2 (logical device 8), GPIO3 (logical device 9), and ACPI ((logical device A). ...
Page 167
... Configuration Register 0 (CR0), Configuration Data Register (EFDR). The EFIRs are write-only registers with port address 3F0h or 370h on PC/AT systems; the EFDRs are read/write registers with port address 3F1h or 371h on PC/AT systems. To program W83977ATF configuration registers, the following configuration sequence must be followed: (2). Configure the configuration registers (3) ...
Page 168
... MOV DX,3F1H MOV AL,01H OUT DX,AL ; select logical device 1 ; MOV DX,3F0H MOV AL,F0H OUT DX,AL ; select CRF0 MOV DX,3F1H MOV AL,3CH OUT DX,AL ; update CRF0 with value 3CH ;------------------------------------------ ; Exit extended function mode ;------------------------------------------ MOV DX,3F0H MOV AL,AAH OUT DX, -112 - W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.53 ...
Page 169
... ACPI REGISTERS FEATURES The W83977ATF supports both ACPI and legacy power managements. The switch logic of the power managment block generates an SMI interrupt in the legacy mode and an SCI interrupt in the ACPI mode. For the legacy mode, the SMI_EN bit is used set, it routes the power management events to the SMI interrupt logic ...
Page 170
... ACPI software. If BIOS_RLS is set by the BIOS software and GBL_EN is set by the ACPI software, an SCI interrupt is raised. Writing BIOS_RLS sets it to logic 1 and also sets GBL_STS to logic 1. Writing BIOS_RLS has no effect. Writing GBL_STS clears it to logic 0 and also clears BIOS_RLS to logic 0. Writing GBL_STS has no effect. W83977ATF clear GBL_STS set ...
Page 171
... The TMR_ON is located in GPE register block cleared to 0, the power management timer function will not work. requirements, except that the timer should function after power-up. See the following figure for illustration. W83977ATF PRELIMINARY There are no timer reset Publication Release Date:April 1998 ...
Page 172
... ACPI specification and is specified in CR64, CR65 of logical device A. 9.3.1 Power Management 1 Status Register 1 (PM1STS1) Register Location: <CR60, Default Value: 00h Attribute: Read/write Size: 8 bits 7 61> System I/O Space W83977ATF PRELIMINARY Reversed or 0 TMR_STS Reserved Reserved Reserved BM_STS GBL_STS Reserved Reserved Publication Release Date:April 1998 Revision 0. the ...
Page 173
... Description This bit is set when the BIOS wants the > System I/O Space Reserved Reserved Reserved Reserved Reserved Reserved Reserved WAK_STS -117 - W83977ATF PRELIMINARY , or by the sleeping/working state Publication Release Date:April 1998 Revision 0.53 ...
Page 174
... Reserved Reserved. These bits always return zeros. 61> System I/O Space TMR_EN Reserved Reserved Reserved GBL_EN Reserved Reserved Reserved Description 61> System I/O Space Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description -118 - W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.53 ...
Page 175
... Reserved Reserved Reserved When this bit is reset and SMI_EN bit is set, the power SMI interrupt if BIOS_EN is also set. > System I/O Space Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved - - W83977ATF PRELIMINARY SCI or an SMI Publication Release Date:April 1998 Revision 0.53 ...
Page 176
... Reserved Reserved. These bits always return zeros. 61> System I/O Space Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description 61> System I/O Space Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description -120 - W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.53 ...
Page 177
... Attribute: Read only Size: 8 bits > System I/O Space TMR_VAL0 TMR_VAL1 TMR_VAL2 TMR_VAL3 TMR_VAL4 TMR_VAL5 TMR_VAL6 TMR_VAL7 Description 61> System I/O Space TMR_VAL8 TMR_VAL9 TMR_VAL10 TMR_VAL11 TMR_VAL12 TMR_VAL13 TMR_VAL14 TMR_VAL15 - - W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.53 ...
Page 178
... TMR_STS bit is set any time the last bit of the timer (bit 23) goes from from the TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. Description 61> System I/O Space TMR_VAL16 TMR_VAL17 TMR_VAL18 TMR_VAL19 TMR_VAL20 TMR_VAL21 TMR_VAL22 TMR_VAL23 Description -122 - W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.53 ...
Page 179
... IRQ to the SCI logic input is ignored and no SCI interrupt will be raised. 61> System I/O Space Description 63> System I/O Space -123 - W83977ATF PRELIMINARY 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved URBSCISTS URASCISTS FDCSCISTS PRTSCISTS KBCSCISTS MOUSCISTS ...
Page 180
... Default Value: 00h Attribute: Read/write Size: 8 bits Bit Name 0-7 Reserved Reserved. These bits always return zeros. Description 63> System I/O Space Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description -124 - W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.53 ...
Page 181
... Reserved Reserved. 9.3.16 General Purpose Event 0 Enable Register 2 (GP0EN2) Register Location: <CR62, Default Value: 00h Attribute: Read/write Size: 8 bits 63> System I/O Space URBSCIEN URASCIEN FDCSCIEN PRTSCIEN KBCSCIEN MOUSCIEN IRSCIEN Reserved Description 63> System I/O Space -125 - W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.53 ...
Page 182
... Default Value: 00h Attribute: Read/write Size: 8 bits Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description 65> System I/O Space BIOS_STS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description 65> System I/O Space -126 - W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.53 ...
Page 183
... Default Value: 00h Attribute: Read/write Size: 8 bits Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description 65> System I/O Space Description 65> System I/O Space -127 - W83977ATF PRELIMINARY 0 BIOS_EN TMR_ON Reserved Reserved Reserved Reserved Reserved Reserved Publication Release Date:April 1998 Revision 0.53 ...
Page 184
... SCI interrupt is generated. Writing a 1 sets BM_CNTRL to 1 and also sets BM_STS. Writing a 0 has no effect. Writing BM_STS clears BM_STS and also clears BM_CNTRL. 2-7 Reserved Reserved BIOS_RLS BM_CNTRL Reserved Reserved Reserved Reserved Reserved Reserved Description -128 - W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.53 ...
Page 185
... MOUSCISTS KBCSCISTS MOUSCIEN KBCSCIEN -129 - W83977ATF PRELIMINARY GBL_RLS BM_RLD TMR_VAL3 TMR_VAL2 TMR_VAL1 TMR_VAL11 TMR_VAL10 TMR_VAL9 ...
Page 186
... SERIAL IRQ W83977ATF supports a Serial IRQ scheme. This allows a signal line to be used to report the legacy ISA interrupt rerquests. Because more than one device may need to share the signal serial IRQ signal line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is transfered on the IRQSER signal, one cycle consisting of three frame types: a start frame, several IRQ/Data frames, and one Stop frame ...
Page 187
... IRQ is inactive, then IRQSER must be left tri-stated. During the Recovery phase, the peripheral device drives the IRQSER high. During the Turn-around phase, the peripheral device leaves the IRQSER tri-stated. The IRQ/Data Frame has a number of specific order, as shown in Table 10-1. W83977ATF PRELIMINARY Publication Release Date:April 1998 -131 - ...
Page 188
... Start IRQ0 IRQ1 SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK INTA INTB INTC INTD Unassigned -132 - W83977ATF PRELIMINARY Publication Release Date:April 1998 ...
Page 189
... Printer status buffer (Read) 0 Printer control latch (Write) 0 Printer control swapper (Read) 1 EPP address port (R/W) 0 EPP data port 0 (R/W) 1 EPP data port 1 (R/W) 0 EPP data port 2 (R/W) 1 EPP data port 2 (R/ W83977ATF PRELIMINARY EXT2FDD PIN EXTFDD ATTRIBUTE --- --- --- I INDEX 2 INDEX 2 I TRAK02 TRAK02 I ...
Page 190
... A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect TMOUT ERROR SLCT PE ACK BUSY - 86 - W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.52 ...
Page 191
... The address port is available only in EPP mode. Bit definitions are as follows STROBE AUTO FD INIT SLCT IN IRQ ENABLE DIR W83977ATF PRELIMINARY 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Publication Release Date:April 1998 Revision 0.52 ...
Page 192
... SLIN PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 - 88 - W83977ATF PRELIMINARY PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD2 PD1 PD0 1 1 TMOUT INIT AUTOFD STROBE INIT ...
Page 193
... EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high. W83977ATF EPP DESCRIPTION Publication Release Date:April 1998 - 89 - PRELIMINARY ...
Page 194
... ECP FIFO (Address) R All Status Register R/W All Control Register R/W 010 Parallel Port Data FIFO R/W 011 ECP FIFO (DATA) R/W 110 Test FIFO R 111 Configuration Register A R/W 111 Configuration Register B R/W All Extended Control Register DESCRIPTION Publication Release Date:April 1998 - 90 - W83977ATF PRELIMINARY FUNCTION Revision 0.52 ...
Page 195
... These bits are at low level during a read of the Printer Status Register. The bits of this status register are defined as follows Address/RLE W83977ATF PRELIMINARY PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Address or RLE nFault Select PError nAck nBusy Publication Release Date:April 1998 Revision 0.52 ...
Page 196
... Bit 2: This bit is output to the INIT output. Bit 1: This bit is inverted and output to the AFD output. Bit 0: This bit is inverted and output to the STB output W83977ATF PRELIMINARY strobe autofd nInit SelectIn ackIntEn Direction Publication Release Date:April 1998 Revision 0.52 ...
Page 197
... Bit 7: This bit is read-only low level during a read. This means that this chip does not support hardware RLE compression. Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts W83977ATF PRELIMINARY IRQx 0 IRQx 1 IRQx 2 intrValue compress Publication Release Date:April 1998 Revision 0.52 ...
Page 198
... Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 in this mode. Bit 4: Read/Write (Valid only in ECP Mode) IRQ resource W83977ATF PRELIMINARY . empty full service Intr dmaEn nErrIntrEn MODE MODE MODE Publication Release Date:April 1998 ...
Page 199
... These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO PD5 PD4 PD3 PError Select nFault Directio ackIntEn SelectIn nErrIntrEn dmaEn serviceIntr - 95 - W83977ATF PRELIMINARY NOTE PD2 PD1 PD0 nInit autofd strobe ...
Page 200
... ECP Mode. This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. This signal is always deasserted in ECP mode W83977ATF PRELIMINARY Publication Release Date:April 1998 Revision 0.52 ...