W25P243AF-4A Winbond, W25P243AF-4A Datasheet

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W25P243AF-4A

Manufacturer Part Number
W25P243AF-4A
Description
64K*64 high speed, low power synchronous-burst pipelined CMOS static RAM
Manufacturer
Winbond
Datasheet

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GENERAL DESCRIPTION
The W25P243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM
organized as 65,536
address counter supports both Pentium
executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by
the FT pin. A snooze mode can reduce power dissipation.
W25P243A supports 2T/1T mode, while disable data output within one cycle in a burst read when the
device is deselected by CE2/ CE3 .
This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.
FEATURES
BLOCK DIAGRAM
Synchronous operation
High-speed access time: 4.5/5/6 nS (max.)
Single +3.3V power supply
Individual byte write capability
3.3V LVTTL compatible I/O
Clock-controlled and registered input
Asynchronous output enable
64K
64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst
BW(8:1)
CE(3:1)
A(15:0)
ADSC
ADSP
BWE
ADV
LBO
CLK
GW
OE
ZZ
64 BURST PIPELINED HIGH-SPEED
REGISTER
REGISTER
CONTROL
INPUT
LOGIC
burst mode and linear burst mode. The mode to be
- 1 -
REGISTER
DATA I/O
Pipelined data output capability
Supports snooze mode (low-power state)
Internal burst counter supports Intel burst
(Interleaved) mode & linear burst mode
Support 2T/1T mode
Packaged in 128-pin QFP and TQFP
64K X 64
ARRAY
CORE
CMOS STATIC RAM
Publication Release Date: August 1999
I/O(64:1)
W25P243A
Revision A3

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W25P243AF-4A Summary of contents

Page 1

GENERAL DESCRIPTION The W25P243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM organized as 65,536 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both Pentium executed is controlled by ...

Page 2

PIN CONFIGURATION VSSQ I/O33 3 I/O34 4 I/O35 5 I/O36 6 I/O37 7 I/O38 8 I/O39 9 I/O40 10 I/O41 11 I/O42 12 ...

Page 3

PIN DESCRIPTION SYMBOL Input, Synchronous A0 A15 I/O, Synchronous I/O1 I/O64 CLK Input, Clock Input, Synchronous CE1, CE2, CE3 Input, Synchronous GW Input, Synchronous BWE Input, Synchronous BW1 BW8 Input, Asynchronous OE Input, Synchronous ADV Input, Synchronous ADSC Input, Synchronous ...

Page 4

FUNCTIONAL DESCRIPTION The W25P243A is a synchronous-burst pipelined SRAM designed for use in high-end personal computers. It supports two burst address sequences for Intel systems (Interleaved mode) and linear mode, which can be controlled by the LBO pin. The burst ...

Page 5

Truth Table, continued ADDRESS CYCLE USED Begin Write Current Begin Write Current Begin Write External Continue Write Next Continue Write Next Suspend Write Current Suspend Write Current Notes: 1. For a detailed definition of read/write, see the Write Table below. ...

Page 6

Write Table, continued READ/WRITE FUNCTION Write byte 5, byte 2 Write byte 5, byte 2, byte 1 Write byte 5, byte 3 Write byte 5, byte 3, byte 1 Write byte 5, byte 3, byte 2 Write byte 5, byte ...

Page 7

DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Core Supply Voltage to Vss I/O Supply Voltage to Vss Input/Output to V Potential SSQ Allowable Power Dissipation Storage Temperature Operating Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may ...

Page 8

AC CHARACTERISTICS AC Test Conditions PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load AC Test Loads and Waveform ohm VL = 1.5V OUTPUT ohm AC ...

Page 9

AC Timing Characteristics, continued PARAMETER ADSP Setup Time ADSP Hold Time ADSC Setup Time ADSC Hold Time CE1, CE2, CE3 Setup Time CE1, CE2, CE3 Hold Time GW , BWE , BWEx Setup Time GW , BWE , BWEx Hold ...

Page 10

TIMING WAVEFORMS Read Cycle Timing Single Read CLK T T ADSS ADSH ADSP T ADSC T T ADVS ADVH ADV A[15:0] RD1 BWE BW[8: CES ...

Page 11

Timing Waveforms, continued Write Cycle Timing Single Write CLK T T ADSS ADSH ADSP T ADCS ADSC T ADVS ADV A[15:0] WR1 BWE T WS WR1 BW[8: CEH CES ...

Page 12

Timing Waveforms, continued Read/Write Cycle Timing Single Read CLK T T ADSS ADSH ADSP T ADCS ADSC T T ADVS ADVH ADV A[15:0] RD1 BWE BW[8:1] T ...

Page 13

Timing Waveforms, continued ZZ and RD Timing Single Read CLK T T ADSS ADSH ADSP ADSC T ADVS ADV A[15:0] RD1 BWE T WS BW[8: CES CEH CE1 T ...

Page 14

Timing Waveforms, continued Dual Bank Burst Read Cycle CLK Select Bank 0 ADSP ADSC ADV Read 1 A[31:3] GW BWE BW[8:1] CE1 CE[3:2] Active Bank 0 CE[3:2] Non- Active Bank 1 OE D[63:0] Bank 0 D[63:0] Bank 1 DON'T CARE ...

Page 15

... ORDERING INFORMATION PART NO. ACCESS TIME (nS) W25P243AF-4A 4.5 W25P243AF-5 5 W25P243AF-6 6 W25P243AD-4A 4.5 W25P243AD-5 5 W25P243AD-6 6 Notes 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. ...

Page 16

PACKAGE DIMENSIONS 128-pin QFP 128 See Detail F Seating Plane 103 102 Dimension in inches Dimension in mm Symbol Nom. Nom. ...

Page 17

Package Dimensions, continued 128-pin TQFP 128 See Detail F Seating Plane 103 102 Dimension in inches Dimension in mm Symbol Nom. ...

Page 18

... Support 83, 75 MHz Change from "Output Enable" to " OHZ Output Disable" Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. Winbond Memory Lab. Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Winbond Microelectronics Corp. Kowloon, Hong Kong Winbond Systems Lab. ...

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