W27C020-70 Winbond, W27C020-70 Datasheet
W27C020-70
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W27C020-70 Summary of contents
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... ELECTRICALLY ERASABLE EPROM GENERAL DESCRIPTION The W27C020 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 262144 provides an electrical chip erase function. FEATURES High speed access time: 70/90/120 nS (max.) Read operating current (max.) Erase/Programming operating current (max ...
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... The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C020 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. ...
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... OE and PGM. Two-line Output Control Since EPROMs are often used in large memory arrays, the W27C020 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur ...
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... IL, IH, PGM = 2 -0 and removed simultaneously or after Preliminary W27C020 RATING -55 to +125 -65 to +125 -0 +0 -0.5 to +14.5 -0.5 to +14.5 LIMITS MIN. TYP. MAX. - -0.3 - 0.8 2 0.45 2 13.75 14.0 14.25 13.75 14.0 14.25 4 ...
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... Jig and Scope for 70 nS (Including Jig and Scope) Test Points 2.4V 2.0V 2.0V 0.8V 0.8V 0.45V Test Point 3.0V 1.5V 1.5V 0V Publication Release Date: September 1998 - 5 - Preliminary W27C020 MAX. UNIT 6 12 CONDITIONS 90/120 nS 0.45V to 2. 0.8V/2. 100 pF -0.4 mA/2 Test Points ...
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... 0. OUT MHz 2 -0 SYM. W27C020-70 W27C020-90 MIN. MAX. MIN ACC and removed simultaneously or after Preliminary W27C020 LIMITS MIN ...
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... PGM Erase Pulse Width Data Hold Time OE Setup Time Data Valid from OE OE High to Output High Z Address Hold Time after PGM High Address Hold Time (Erase) CE Setup Time Note: V must be applied simultaneously or before V CC Preliminary W27C020 SYM. CONDITIONS ...
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... Others AHC T DFP Data All One OUT VPS T T OES OE T OEV T PWE T CES - 8 - Preliminary W27C020 Valid Output High Z Blank Check Read Verify Address Address Stable Stable T ACC D D OUT OUT ...
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... PGM V IL Program Program Verify Address Stable Address Stable T DFP D D Data In Stable OUT OUT CES T OES T OEV T PWP - 9 - Preliminary W27C020 Read Verify Address Valid T ACC D OUT Publication Release Date: September 1998 Revision A1 ...
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... Address = First Location Vcc = 5V Vpp = 12V Program One 100 S Pulse Increment X Yes X = 25? No Fail Verify One Byte Pass No Last Address? Yes Vcc = 5V Vpp = 5V Compare Fail All Bytes to Original Data Pass Pass Device - 10 - Preliminary W27C020 Fail Verify One Byte Pass Fail Device ...
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... Vpp = 14V A9 = 14V Chip Erase 100 mS Pulse Address = First Location Increment X Fail Erase Verify Pass No Last Address? Yes Vcc = 5V Vpp = 5V Compare Fail All Bytes to FFs (HEX) Pass Pass Device - 11 - Preliminary W27C020 20? Yes Fail Device Publication Release Date: September 1998 Revision A1 ...
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... Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. Preliminary W27C020 POWER SUPPLY STANDBY V CURRENT MAX. ...
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... 32-Lead PLCC Seating Plane Preliminary W27C020 Base Plane Seating Plane Symbol Notes Dimensions D & not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. ...
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... Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. Preliminary W27C020 PAGE DESCRIPTION Initial Issued Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. Winbond Memory Lab. ...