DS80C400 Dallas Semiconductor, DS80C400 Datasheet
DS80C400
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DS80C400 Summary of contents
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... To accelerate data transfers between the microcontroller and the 16MB memory map, the DS80C400 provides four data pointers, each of which can be configured to automatically increment or decrement upon execution of certain data pointer-related instructions. ...
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FEATURES (continued) § 10/100 Ethernet MAC - Flexible IEEE 802.3 MII (10/100Mbps) and ENDEC (10Mbps) interfaces allow selection of PHY - Low-power operation - Ultra-low-power sleep mode with Magic ™ Packet and wake-up frame detection - 8kB on-chip Tx/Rx packet ...
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Figure 1. Block Diagram 1-WIRE CONTROLLER PORT LATCH PORT 5 P5.0–P5.7 P1.0–P1.7 PORT 1 SERIAL PORT 1 PORT LATCH TIMER 125 P0.0–P0.7 PORT 0 ...
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Table 1. Pin Description PIN NAME 70 V +1.8V Core Supply Voltage CC1 12, 36, V +3.3V I/O Supply Voltage CC3 62, 87 13, 39, V Digital Circuit Ground SS 63 ALE Address Latch Enable, Output. When the ...
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PIN NAME P1.0–P1.7 Port 1, I/O. Port 1 can function as either an 8-bit, bidirectional I/O port alternate interface for internal resources. The reset condition of Port 1 is all bits at logic 1 through a weak ...
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PIN NAME P4.0–P4.7 Port 4, I/O. Port 4 can function as an 8-bit, bidirectional I/O port, and as the source for external address and chip-enable signals for program and data memory. Port pins are configured as I/O or memory signals ...
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PIN NAME P6.0–P6.7 Port 6, I/O. Port 6 can function as an 8-bit, bidirectional I/O port, as program and data memory address/chip-enable signals, and/or a third serial port. The reset condition of Port 6 is all bits at logic 1 ...
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PIN NAME 10 RXClk Receive Clock, Input. The receive clock is a continuous clock sourced from the Ethernet PHY controller used to provide timing reference for transferring of RX_DV, RX_ER, and RXD[3:0] signals from the external Ethernet PHY ...
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... Tx/Rx packet activity and status reporting through an on-chip 8kB SRAM. To further reduce host (DS80C400) software intervention, the MAC can be set up to generate a hardware interrupt following each transmit or receive status report. The DS80C400 MAC can be operated in half-duplex or full-duplex mode with flow control, and provides multicast/broadcast-address filtering modes as well as VLAN tag- recognition capability ...
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... The microcontroller can be configured to automatically switch back from PMM to the faster mode in response to external interrupts or serial port activity. The DS80C400 provides the ability to place the CPU into an idle state or an ultra-low-power stop-mode state. As protection against brownout and power-fail conditions, the microcontroller is capable of issuing an early warning power-fail interrupt and can generate a power-fail reset ...