W9816G6BB-7 Winbond, W9816G6BB-7 Datasheet
W9816G6BB-7
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W9816G6BB-7 Summary of contents
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... Precharge Command ...................................................................................................................... 10 Self Refresh Command................................................................................................................... 10 Power Down Mode .......................................................................................................................... 10 No Operation Command ................................................................................................................. 11 Deselect Command......................................................................................................................... 11 Clock Suspend Mode ...................................................................................................................... 11 Table of Operating Modes............................................................................................................... 12 8. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 13 9. RECOMMENDED DC OPERATING CONDITIONS ......................................................................... 13 10. CAPACITANCE ............................................................................................................................... 13 512K × 2 BANKS × 16 BITS SDRAM Publication Release Date: January 2, 2003 - 1 - W9816G6BB Revision A1 ...
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... Auto Precharge Timing ................................................................................................................... 36 Timing Chart of Write-to-Read Cycle .............................................................................................. 37 Timing Chart of Burst Stop Cycle.................................................................................................... 37 Timing Chart of Burst Stop Cycle (Prechare Command)................................................................ 38 CKE/DQM Input Timing................................................................................................................... 39 CKE/DQM Input Timing................................................................................................................... 40 Self Refresh/ Power Down Mode Exit Timing ................................................................................. 41 14. PACKAGE DIMENSIONS ............................................................................................................... 42 BGA 60 Balls Pitch = 0.65 mm........................................................................................................ W9816G6BB ...
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... Burst length and full page • • Burst read, single write mode • Byte data controlled by UDQM and LDQM 3. PART NUMBER INFORMATION PART NUMBER W9816G6BB-7 • Auto-precharge and controlled precharge • 4K refresh cycles/64 mS • Interface: LVTTL • Package: BGA 60 balls pitch = 0.65 mm using ...
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... DQ7 WE# WE# CAS# CAS# CS# CS A10 A10 VDD VDD W9816G6BB Bottom View DQ0 DQ15 Vss VDDQ VssQ DQ14 VssQ VDDQ DQ13 DQ4 DQ11 DQ12 VDDQ VssQ DQ10 VssQ VDDQ DQ9 NC NC DQ8 ...
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... Power Separated power from V (+3.3V) for to improve noise immunity. I/O buffer Ground for Separated ground from V I/O buffer to improve noise immunity connection Connection Publication Release Date: January 2, 2003 - 5 - W9816G6BB DESCRIPTION and define the CAS WE , used for output buffers DD , used for output buffers SS Revision A1 ...
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... COUNTER COLUMN DECODER CELL ARRAY D BANK # SENSE AMPLIFIER DATA CONTROL CIRCUIT COLUMN DECODER CELL ARRAY D E BANK # SENSE AMPLIFIER Note: The cell array configuration is 2048 * 256 * W9816G6BB DQ0 DQ BUFFER DQ15 LDQM UDQM ...
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... Commands can also be issued to the same bank or between active banks on every clock cycle. and V pins must be ramp up simultaneously to the DD DDQ supplies. After power up, an initial pause of 200 µ The maximum time that each bank can be held active is RRD RCD Publication Release Date: January 2, 2003 - 7 - W9816G6BB has RSC ). RC delay. WE pin voltage level Revision A1 ...
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... Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge W9816G6BB ...
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... No address carry from Access Address W9816G6BB Burst Length Bust Length Publication Release Date: January 2, 2003 Revision A1 ...
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... Power Down mode longer than the Refresh period (t device. ) has been satisfied. Issue of Auto-Precharge command is RP and When using the Auto Precharge Command, the interval W9816G6BB . The bank WR are satisfied. This is referred the REF ...
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... While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one-clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. W9816G6BB . The input buffers need (min (min) ...
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... W9816G6BB A10 A9-0 CAS CS RAS ...
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... SOLDER OUT SYM. MIN. TYP. MAX. V 2.7 3 2.7 3.3 DDQ SYM Publication Release Date: January 2, 2003 - 13 - W9816G6BB UNIT NOTES °C 1 °C 1 ° UNIT NOTES MIN. MAX. UNIT - 4 pf ...
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... CKE = CC3 CKE = CC3P (Power Down mode) I CC4 I CC5 Standard I CC6 Low Power I CC6L SYMBOL I I( W9816G6BB -7 UNIT NOTES MAX 100 1.5 µA 200 MIN. MAX. UNIT NOTES µ µA ...
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... 1.5 CKS t 1 CKH t 1.5 CMS t 1 CMH t REF t 14 RSC Publication Release Date: January 2, 2003 - 15 - W9816G6BB -7 UNIT MAX. nS 100000 Cycle nS 1000 1000 5 Revision A1 ...
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... Transition times are measured between V 8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. SS. PARAMETER output ohms AC TEST LOAD and W9816G6BB CONDITIONS 1.4V/1.4V See diagram below 2.4V/0. 1.4V 1 ohms 30pF ...
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... IL CS RAS CAS WE A0-A10 CKS CKH CKE t t CMS CMH t t CMS CMH t t CMS CMH t t CMS CMH CKS CKH CKS - 17 - W9816G6BB CMH CMS t CKH Publication Release Date: January 2, 2003 Revision A1 ...
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... Timing Waveforms, continued Read Timing CLK CS RAS CAS WE A0-A10 BA DQ Read Command Read CAS Latency Valid Data-Out - 18 - W9816G6BB Valid Data-Out Burst Length ...
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... Valid Valid Data-Out Data-Out CKH CKS CKH CKS Valid Data-Out - 19 - W9816G6BB Valid Valid Data-in Data- Valid Valid Data-in Data- ...
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... Sequential A0 1 Interleave CAS Latency Reserved Reserved Reserved Single Write Mode 0 Burst read and Burst write Burst read and single write W9816G6BB next command A0 Interleave Reserved ...
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... RAS t t RCD RCD RBb RAc CBx RBb RAc t AC bx1 aw0 aw1 aw2 aw3 bx0 t t RRD Active Precharge Precharge Active Read - 21 - W9816G6BB RAS RAS t RCD RBd CAy RBd CBz t AC ...
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... RAS t RCD t RCD RAc CBx RAc aw0 aw1 aw2 aw3 bx0 bx1 t RRD AP* Active Read - 22 - W9816G6BB RAS RAS t RCD RBd RAe CAy CBz RAe RBd ...
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... RAS RP t RAS t RCD RBb RBb CBy t AC ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 t RRD Precharge Active Read - 23 - W9816G6BB RAS RCD RAc RAc CAz t AC by4 by5 by6 by7 ...
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... RAS RP t RCD RBb RBb CBy ax3 ax4 ax0 ax2 ax5 ax6 ax7 ax1 t RRD AP* Read Active * AP is the internal precharge start timing - 24 - W9816G6BB RAS t t RAS RP t RCD RAc CAz RAc t CAC t ...
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... RC t RAS t RCD RBb RBb CBy ax4 ax5 ax6 ax7 by0 by1 by2 by3 t RRD Precharge Active Write Publication Release Date: January 2, 2003 - 25 - W9816G6BB RAS t RCD RAc RAc CAz by4 by5 by6 by7 CZ0 CZ1 Active ...
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... RC t RAS t RCD RBb CBy RBb ax4 by2 ax5 ax6 ax7 by0 by1 t RRD AP* Active Write * AP is the internal precharge start timing - 26 - W9816G6BB RAS t RCD RAb CAz RAb by5 by3 by4 by6 by7 CZ0 Write ...
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... RAS t RAS CAm CBx CAy bx0 bx1 Ay0 Ay1 Ay2 Read Read Read * AP is the internal precharge start timing - 27 - W9816G6BB CBz am0 am1 am2 bz0 bz1 bz2 bz3 Precharge ...
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... RAa CAx A0-A9 DQM CKE Bank #0 Active Read Bank # RAS CAy ax5 ay1 ax0 ax1 ax3 ay0 ax2 ax4 Write - 28 - W9816G6BB ay2 ay4 ay3 Precharge 23 ...
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... RCD RAb RAb aw0 aw1 aw2 aw3 AP* Active * AP is the internal precharge start timing Publication Release Date: January 2, 2003 - 29 - W9816G6BB RAS RP CAx t AC bx0 bx1 bx2 Read AP* Revision A1 23 ...
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... Write Bank #1 Bank #2 Idle Bank # RCD RAb RAb CAx bx0 aw3 Active Write AP the internal precharge start timing - 30 - W9816G6BB RAS RP RAc RAc bx1 bx3 bx2 Active AP* 23 ...
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... Auto Refresh Cycle CLK RAS CAS WE BA A10 A0-A9 DQM CKE DQ All Banks Auto Prechage Refresh (CLK = 100 MHz Publication Release Date: January 2, 2003 - 31 - W9816G6BB Auto Refresh (Arbitrary Cycle) Revision A1 ...
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... MHz CLK RAS CAS WE BA A10 A0-A9 DQM t CKE t CKS DQ All Banks Self Refresh Precharge Entry CKS SB Self Refresh Cycle - 32 - W9816G6BB CKS Operation Cycle Arbitrary Cycle 23 ...
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... Bank # CBw CBx CBy av0 av1 av3 aw0 ax0 ay0 av2 Single Write - 33 - W9816G6BB CBz t AC az0 az1 az2 az3 Read Publication Release Date: January 2, 2003 Revision A1 23 ...
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... When CKE goes high, command input must be No operation at next CLK rising edge CAa t CKS ax0 ax2 ax3 ax1 Precharge Read - 34 - W9816G6BB RAa RAa CAx CKS NOPActive Precharge Standby Power Down mode ...
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... represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. (min W9816G6BB Act Act Publication Release Date: January 2, 2003 ...
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... RP AP Act Act t RP Act represents the Write with Auto precharge command. represents the start of internal precharging W9816G6BB Act Act Act ...
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... Read Read Read Q0 Q1 Read BST BST BST represents the Burst stop command Publication Release Date: January 2, 2003 - 37 - W9816G6BB Revision A1 ...
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... Commad DQ (2) Write cycle ( a ) CAS latency = 2 Write Commad DQM CAS latency = 3 Write Commad DQM Note: PRCG PRCG PRCG PRCG PRCG represents the Precharge command - 38 - W9816G6BB ...
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... CLK cycle No. External CLK Internal CKE DQM DQM MASK ( DQM MASK ( CKE MASK ( W9816G6BB CKE MASK CKE MASK Publication Release Date: January 2, 2003 Revision A1 ...
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... Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM W9816G6BB Open Open Open ...
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... Self Refresh mode NOP Command (min (min)+t (min) CKS CK NOP Command Input Buffer Enable (min (min)+t (min) CKS CK Command Input Buffer Enable Represents the No-Operation command Represents one command - 41 - W9816G6BB (min (min Publication Release Date: January 2, 2003 Revision A1 ...
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... PACKAGE DIMENSIONS BGA 60 Balls Pitch = 0. W9816G6BB ...
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... FAX: 886-2-8751-3579 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. W9816G6BB Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China ...