SAA7102H Philips Semiconductors, SAA7102H Datasheet
SAA7102H
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DATA SHEET SAA7102; SAA7103 Digital video encoder Product specification File under Integrated Circuits, IC22 INTEGRATED CIRCUITS 2001 Sep 25 ...
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... Philips Semiconductors Digital video encoder CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 QUICK REFERENCE DATA 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 Reset conditions 7.2 Input formatter 7.3 RGB LUT 7.4 Cursor insertion 7.5 RGB Y-C -C matrix B R 7.6 Horizontal scaler 7.7 Vertical scaler and anti-flicker filter 7.8 FIFO 7.9 Border generator 7.10 Oscillator and Discrete Time Oscillator (DTO) 7 ...
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... Philips Semiconductors Digital video encoder 1 FEATURES Digital PAL/NTSC encoder with integrated high quality scaler and anti-flicker filter for TV output from MHz crystal-stable subcarrier generation Maximum graphics pixel clock 45 MHz at double edged clocking, synthesized on-chip or from external source Up to 800 600 graphics data with ...
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... Philips Semiconductors Digital video encoder 3 ORDERING INFORMATION TYPE NUMBER NAME SAA7102E BGA156 SAA7103E SAA7102H QFP44 SAA7103H 4 QUICK REFERENCE DATA SYMBOL V analog supply voltage DDA V digital supply voltage DDD I analog supply current DDA I digital supply current DDD V input signal voltage levels i V analog CVBS output signal voltage for a 100/100 ...
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... RGB TO Y CURSOR RGB LUT MATRIX INSERTION (OR BYPASS) (OR BYPASS) VERTICAL HORIZONTAL SCALER AND FIFO SCALER ANTI-FLICKER FILTER VIDEO TRIPLE ENCODER DAC SAA7102H SAA7103H 2 OSCILLATOR/ TIMING I C-BUS DTO GENERATOR CONTROL XTALI XTAL VSVGC HSVGC SDA ...
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... Philips Semiconductors Digital video encoder 6 PINNING PIN SYMBOL BGA156 QFP44 PD8 B2 PD9 B1 PD10 C2 PD11 C1 RESET D2 TMS D3 TDO D1 TCLK SSD1 V F4 DDD1 SCL E2 SDA G2 FSVGC G1 VSVGC F1 PIXCLKI F2 PD3 F3 PD2 H1 PD1 H2 PD0 H3 PIXCLKO G4 CBO G3 HSVGC E3 TTX_SRES C3 TTXRQ_XCLKO2 C4 VSM D7 HSM_CSYNC D8 RED_CR_C C8 GREEN_VBS_CVBS C7 V A10, B9, ...
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... Philips Semiconductors Digital video encoder PIN SYMBOL BGA156 QFP44 RSET A9 DUMP A7 A8, B8 SSA1 XTALO A6 XTALI A5 V B6, D6 DDA2 TRST A4 TDI B5 V C5, D5 SSD2 V D4 DDD2 PD4 A3 PD5 B3 PD6 B4 PD7 A2 Notes 1. Pin type input output supply accordance with the “IEEE1149.1” standard the pins TDI, TMS, TCLK and TRST are input pins with an internal pull-up resistor and TDO is a 3-state output pin ...
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... Philips Semiconductors Digital video encoder Table 1 Pin assignment SAA7102E; SAA7103E (top view PD7 PD4 TRST B PD9 PD8 PD5 PD6 C PD11 PD10 TTX_ TTXRQ_ SRES XCLKO2 D TDO RESET TMS V DDD2 E TCLK SCL HSVGC V SSD1 F VSVGCPIXCLKI PD3 V DDD1 G FSVGC SDA CBO PIXCLKO ...
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... SAA7102E H SAA7103E Fig.2 Pin configuration (SAA7102E; SAA7103E). SAA7102H SAA7103H Fig.3 Pin configuration (SAA7102H; SAA7103H). 9 Product specification SAA7102; SAA7103 MHB907 33 V SSA1 32 DUMP 31 RSET 30 BLUE_CB_CVBS 29 V DDA1 28 GREEN_VBS_CVBS 27 RED_CR_C ...
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... Philips Semiconductors Digital video encoder 7 FUNCTIONAL DESCRIPTION The digital video encoder encodes digital luminance and colour difference signals (C -Y-C B into analog CVBS, S-video and, optionally, RGB or C -Y-C signals. NTSC M, PAL B/G and sub-standards R B are supported. The SAA7102; SAA7103 can be directly connected to a ...
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... Philips Semiconductors Digital video encoder 7.1 Reset conditions To activate the reset a pulse at least of 2 crystal clocks duration is required. During reset (RESET = LOW) plus an extra 32 crystal clock periods, FSVGC, VSVGC, CBO, HSVGC and TTX_SRES are set to input mode and HSM_CSYNC and VSM are set to 3-state. A reset also forces the I interface to abort any running bus transfer and sets it into receive condition ...
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... Philips Semiconductors Digital video encoder Table 4 Cursor bit map BYTE row 0 row 0 column 3 column 2 1 row 0 row 0 column 7 column 6 2 row 0 row 0 column column 11 10 ... ... ... 6 row 0 row 0 column column row 0 row 0 column column 31 30 ... ... ... 254 row 31 row 31 column ...
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... Philips Semiconductors Digital video encoder 7.8 FIFO The FIFO acts as a buffer to translate from the PIXCLK clock domain to the XTAL clock domain. The write clock is PIXCLK and the read clock is XTAL. An underflow or overflow condition can be detected via the I access. In order to avoid underflows and overflows essential ...
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... Philips Semiconductors Digital video encoder Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. TTXRQ_XCLKO2 provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which can be selected independently for both fields ...
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... Philips Semiconductors Digital video encoder Only vertical frequencies of 50 and 60 Hz are allowed with the SAA7102; SAA7103. In slave mode not possible to lock the encoders colour carrier to the line frequency with the PHRES bits. In the (more common) master mode, the time base of the circuit is continuously free-running ...
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... Philips Semiconductors Digital video encoder Most TV sets use overscan, and not all pixels respectively lines are visible. There is no standard for the factor highly recommended to make the number of output pixels and lines adjustable. A reasonable underscan factor is 10%, giving approximately 640 output pixels per line. ...
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... Philips Semiconductors Digital video encoder 7.18 Input levels and formats The SAA7102; SAA7103 accepts digital Y, C “ITU-R BT.601” ; see Table 23. For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated for by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up ...
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... Philips Semiconductors Digital video encoder Table 7 Y scaler programming at NTSC, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 4 29 212 2 31 212 0 33 212 2 35 212 4 37 214 4 28 214 2 30 214 0 32 ...
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... Philips Semiconductors Digital video encoder Table 8 Y scaler programming at NTSC, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 4 29 212 2 31 212 0 33 212 2 35 212 4 37 214 4 28 214 2 30 214 0 32 ...
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... Philips Semiconductors Digital video encoder Table 9 Y scaler programming at NTSC, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 4 29 212 2 31 212 0 33 212 2 35 212 4 37 214 4 28 214 2 30 214 0 32 ...
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... Philips Semiconductors Digital video encoder Table 10 Y scaler programming at NTSC, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 4 29 212 2 31 212 0 33 212 2 35 212 4 37 214 4 28 214 2 30 214 0 32 ...
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... Philips Semiconductors Digital video encoder Table 11 Y scaler programming at NTSC, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 4 29 212 2 31 212 0 33 212 2 35 212 4 37 214 4 28 214 2 30 214 0 32 ...
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... Philips Semiconductors Digital video encoder Table 12 Y scaler programming at NTSC, input frame size: 800 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 4 29 212 2 31 212 0 33 212 2 35 212 4 37 214 4 28 214 2 30 214 0 32 ...
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... Philips Semiconductors Digital video encoder Table 13 Y scaler programming at NTSC, input frame size: 800 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 4 29 212 2 31 212 0 33 212 2 35 212 4 37 214 4 28 214 2 30 214 0 32 ...
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... Philips Semiconductors Digital video encoder Table 14 Y scaler programming at NTSC, input frame size: 800 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 4 29 212 2 31 212 0 33 212 2 35 212 4 37 214 4 28 214 2 30 214 0 32 ...
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... Philips Semiconductors Digital video encoder Table 15 Y scaler programming at PAL, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 255 4 43 257 4 34 257 2 36 257 0 38 ...
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... Philips Semiconductors Digital video encoder Table 16 Y scaler programming at PAL, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 255 4 43 257 4 34 257 2 36 257 0 38 ...
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... Philips Semiconductors Digital video encoder Table 17 Y scaler programming at PAL, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 255 4 43 257 4 34 257 2 36 257 0 38 ...
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... Philips Semiconductors Digital video encoder Table 18 Y scaler programming at PAL, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 255 4 43 257 4 34 257 2 36 257 0 38 ...
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... Philips Semiconductors Digital video encoder Table 19 Y scaler programming at PAL, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 255 4 43 257 4 34 257 2 36 257 0 38 ...
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... Philips Semiconductors Digital video encoder Table 20 Y scaler programming at PAL, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 255 4 43 257 4 34 257 2 36 257 0 38 ...
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... Philips Semiconductors Digital video encoder Table 21 Y scaler programming at PAL, input frame size: 800 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 255 4 43 257 4 34 257 2 36 257 0 38 ...
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... Philips Semiconductors Digital video encoder Table 22 Y scaler programming at PAL, input frame size: 800 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 255 4 43 257 4 34 257 2 36 257 0 38 ...
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... Philips Semiconductors Digital video encoder Table 23 Y scaler programming at PAL, input frame size: 800 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 255 4 43 257 4 34 257 2 36 257 0 38 ...
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... Philips Semiconductors Digital video encoder Table 24 “ITU-R BT.601” signal component levels SIGNALS COLOUR White 235 128 128 Yellow 210 16 146 Cyan 170 166 16 Green 145 54 34 Magenta 106 202 222 Red 81 90 240 Blue 41 240 110 Black 16 128 ...
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... Philips Semiconductors Digital video encoder Table 28 Pin assignment for input format 8-BIT INTERLACED C (ITU-R BT.656, 27 MHz CLOCK) RISING RISING CLOCK CLOCK PIN EDGE EDGE PD7 C 7(0) Y7(0) B PD6 C 6(0) Y6(0) B PD5 C 5(0) Y5(0) B PD4 C 4(0) Y4(0) B PD3 C 3(0) Y3(0) B PD2 C 2(0) Y2(0) B PD1 C 1(0) Y1(0) B PD0 ...
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Acrobat reader. white to force landscape pages to be ... 7.19 Bit allocation map Table 31 Slave receiver (slave address 88H) SUB REGISTER FUNCTION ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) Gain V 5C GAINV7 Gain U MSB, black level ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) First active line 7A FAL7 Last active line 7B ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) Border colour U A3 BCU7 Border colour V A4 ...
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... Philips Semiconductors Digital video encoder 2 7.20 I C-bus format 2 Table 32 I C-bus write access to control registers; see Table SUBADDRESS 2 Table 33 I C-bus write access to cursor bit map (subaddress FEH); see Table FEH ...
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... Philips Semiconductors Digital video encoder 7.21 Slave receiver Table 38 Subaddress 16H DATA BYTE DACF output level adjustment fi steps for all DACs; default after reset is 00H; see Table 39 Table 39 Fine adjustment of DAC output voltage BINARY 0111 0110 0101 0100 0011 0010 ...
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... Philips Semiconductors Digital video encoder Table 42 Subaddress 1BH LOGIC DATA BYTE LEVEL MSM 0 monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset 1 monitor sense mode on RCOMP 0 check comparator at DAC on pin 27 is active, output is loaded (read only) ...
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... Philips Semiconductors Digital video encoder Table 46 Subaddresses 2AH to 2CH LOGIC DATA BYTE LEVEL CG LSB of the respective bytes are encoded immediately after run-in, the MSBs of the respective bytes have to carry the CRCC bits, in accordance with the definition of copy generation management system encoding format. ...
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... Philips Semiconductors Digital video encoder Table 49 Subaddress 3AH LOGIC DATA BYTE LEVEL CBENB 0 data from input ports is encoded 1 colour bar with fixed colours is encoded SYMP 0 horizontal and vertical trigger is taken from FSVGC or both VSVGC and HSVGC; default after reset horizontal and vertical trigger is decoded out of “ITU-R BT.656” compatible data at PD port ...
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... Philips Semiconductors Digital video encoder Table 52 Subaddress 5AH; note 1 DATA BYTE DESCRIPTION CHPS phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees Note 1. The default after reset is 00H. Table 53 Subaddresses 5BH and 5DH DATA BYTE DESCRIPTION ...
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... Philips Semiconductors Digital video encoder Table 56 Subaddress 5EH DATA BYTE DESCRIPTION BLNNL variable blanking level Notes 1. Output black level/IRE = BLNNL 2. Output black level/IRE = BLNNL Table 57 Subaddress 5FH DATA BYTE CCRS select cross-colour reduction filter in luminance; see Table 58 BLNVB variable blanking level during vertical blanking interval is typically identical to value of BLNNL ...
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... Philips Semiconductors Digital video encoder Table 60 Subaddress 62H DATA BYTE DESCRIPTION BSTA amplitude of colour burst; input representation in accordance with “ITU-R BT.601” Table 61 Subaddresses 63H to 66H (four bytes to program subcarrier frequency) DATA BYTE DESCRIPTION FSC0 to FSC3 f = subcarrier frequency fsc (in multiples of line frequency) ...
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... Philips Semiconductors Digital video encoder Table 64 Subaddress 6DH DATA BYTE VTRIG sets the vertical trigger phase related to chip-internal vertical input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines; variation range of VTRIG = (1FH); the default value is 0 Table 65 Subaddress 6EH ...
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... Philips Semiconductors Digital video encoder Table 69 Subaddress 6FH DATA LOGIC BYTE LEVEL CCEN enables individual line 21 encoding; see Table 70 TTXEN 0 disables teletext insertion; default after reset 1 enables teletext insertion SCCLN selects the actual line, where Closed Caption or extended data are encoded; ...
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... Philips Semiconductors Digital video encoder Table 75 Subaddresses 76H, 77H and 7CH DATA BYTE TTXOVS first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in odd field line = (TTXOVS + 4) for M-systems line = (TTXOVS + 1) for other systems TTXOVE last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in odd fi ...
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... Philips Semiconductors Digital video encoder Table 80 Subaddresses 81H to 83H DATA BYTE PCL defines the frequency of the synthesized pixel clock PIXCLKO; PCL f = ---------- - PIXCLK 24 2 640 480 to PAL B/G: PCL = 1B5A73H (as by strapping pins) Table 81 Subaddresses 90H and 94H DATA BYTE XOFS horizontal offset; defines the number of PIXCLKs from horizontal sync (HSVGC) output to composite ...
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... Philips Semiconductors Digital video encoder Table 86 Subaddress 96H LOGIC DATA BYTE LEVEL EFS 0 frame sync signal at pin FSVGC ignored in slave mode 1 frame sync signal at pin FSVGC accepted in slave mode PCBN 0 normal polarity of CBO signal (HIGH during active video) 1 inverted polarity of CBO signal (LOW during active video) ...
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... Philips Semiconductors Digital video encoder LOGIC DATA BYTE LEVEL OHS 0 pin HSVGC is switched to input 1 pin HSVGC is switched to active output PHS 0 polarity of signal on HSVGC in output mode (master mode) is active HIGH; rising edge of the input signal is used in slave mode 1 polarity of signal on HSVGC in output mode (master mode) is active LOW; falling edge ...
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... Philips Semiconductors Digital video encoder Table 94 Subaddresses A0H and A1H DATA BYTE YSKIP vertical line skip; defines the effectiveness of the anti-flicker filter; YSKIP = 0: most effective; YSKIP = 4095: anti-flicker filter switched off Table 95 Subaddress A1H LOGIC DATA BYTE LEVEL BLEN 0 no internal blanking for non-interlaced graphics in bypass mode ...
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... Philips Semiconductors Digital video encoder Table 103 Subaddress FCH DATA BYTE YHS vertical hot spot of cursor Table 104 Subaddress FDH LOGIC DATA BYTE LEVEL LUTOFF 0 colour look-up table is active 1 colour look-up table is bypassed CMODE 0 cursor mode; input colour will be inverted 1 auxiliary cursor colour will be inserted ...
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... Philips Semiconductors Digital video encoder 7.22 Slave transmitter Table 107 Slave transmitter (slave address 89H) REGISTER SUBADDRESS FUNCTION Status byte 00H Chip ID 1CH FIFO status 80H Table 108 Subaddress 00H LOGIC DATA BYTE LEVEL VER version identification of the device: it will be changed with all versions of the IC that have different programming models ...
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... Philips Semiconductors Digital video encoder handbook, full pagewidth (dB ( (1) SCBW = 1. (2) SCBW = 0. handbook, halfpage (1) SCBW = 1. (2) SCBW = 0. 2001 Sep 25 ( Fig.4 Chrominance transfer characteristic (dB) 0 (1) ( 0.4 0.8 1.2 Fig.5 Chrominance transfer characteristic 2. ...
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... Philips Semiconductors Digital video encoder handbook, full pagewidth (dB (1) CCRS1 = 0; CCRS0 = 1. (2) CCRS1 = 1; CCRS0 = 0. (3) CCRS1 = 1; CCRS0 = 1. (4) CCRS1 = 0; CCRS0 = 0. Fig.6 Luminance transfer characteristic 1 (excluding scaler). handbook, halfpage (1) CCRS1 = 0; CCRS0 = 0. Fig.7 Luminance transfer characteristic 2 (excluding scaler). ...
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... Philips Semiconductors Digital video encoder handbook, full pagewidth (dB Fig.8 Luminance transfer characteristic in RGB (excluding scaler). handbook, full pagewidth (dB Fig.9 Colour difference transfer characteristic in RGB (excluding scaler). ...
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... Philips Semiconductors Digital video encoder 8 BOUNDARY SCAN TEST The SAA7102; SAA7103 has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7102; SAA7103 follows the “IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture” set by the Joint Test Action Group (JTAG) chaired by Philips ...
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... Philips Semiconductors Digital video encoder MSB handbook, full pagewidth 31 TDI 0010 4-bit version code MSB handbook, full pagewidth 31 TDI 0010 4-bit version code 2001 Sep 0111000100000010 16-bit part number a. SAA7102 0111000100000011 16-bit part number b. SAA7103. Fig.10 32 bits of identification code. ...
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... Philips Semiconductors Digital video encoder 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); all ground pins connected together and all supply pins connected together. SYMBOL PARAMETER V digital supply voltage DDD V analog supply voltage DDA V output voltage at analog outputs ...
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... Philips Semiconductors Digital video encoder 11 CHARACTERISTICS V = 3 unless otherwise specified. DDD amb SYMBOL PARAMETER Supplies V analog supply voltage DDA V digital supply voltage DDD I analog supply current DDA I digital supply current DDD Inputs V LOW-level input voltage at all digital ...
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... Philips Semiconductors Digital video encoder SYMBOL PARAMETER C RYSTAL SPECIFICATION T ambient temperature amb C load capacitance L R series resistance S C motional capacitance (typical parallel capacitance (typical) 0 Data and reference signal output timing C output load capacitance o(L) t output hold time o(h) t output delay time o(d) CVBS and RGB outputs ...
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... Philips Semiconductors Digital video encoder handbook, full pagewidth PIXCLKO t d(CLKD) PIXCLKI PDn any output handbook, full pagewidth HSVGC CBO PD 2001 Sep 25 T PIXCLK t HIGH HD;DAT t HD;DAT t SU;DAT t o(d) t o(h) Fig.11 Input/output timing specification. XOFS IDEL XPIX HLEN Fig.12 Horizontal input timing. ...
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... Philips Semiconductors Digital video encoder handbook, full pagewidth HSVGC VSVGC CBO 2001 Sep 25 YOFS YPIX Fig.13 Vertical input timing. 67 Product specification SAA7102; SAA7103 MHB906 ...
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... Philips Semiconductors Digital video encoder 11.1 Teletext timing Time t is the time needed to interpolate input data TTX FD and insert it into the CVBS and VBS output signal, such that it appears 9.78 s (PAL TTX (NTSC) after the leading edge of the horizontal synchronization pulse. ...
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... PD11 3 PD10 2 PD9 1 PD8 27 44 RED_CR_C PD7 43 28 PD6 GREEN_VBS_CVBS 42 PD5 30 41 PD4 BLUE_CB_CVBS 16 PD3 17 25 PD2 VSM 18 PD1 26 SAA7102H 19 HSM_CSYNC PD0 SAA7103H 34 22 XTALO HSVGC 14 VSVGC 35 XTALI 13 FSVGC 21 CBO R2 23 4.7 k TTX_SRES 24 TTXRQ_XCLKO2 S1 CP1 JP9 ...
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... Philips Semiconductors Digital video encoder handbook, halfpage 12.1 Analog output voltages The analog output voltages are dependent on the total load (typical value 37.5 ), the digital gain parameters and 2 the I C-bus settings of the DAC reference currents (analog settings). The digital output signals in front of the DACs under ...
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... Philips Semiconductors Digital video encoder 13 PACKAGE OUTLINES BGA156: plastic ball grid array package; 156 balls; body 1.15 mm ball A1 index area DIMENSIONS (mm are the original dimensions) ...
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... Philips Semiconductors Digital video encoder QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 1. pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.25 1.85 0.40 mm 2.10 0.25 0.05 1.65 0.20 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... Philips Semiconductors Digital video encoder 14 SOLDERING 14.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). ...
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... This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specifi ...
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... Philips Semiconductors customers using or selling these products for use in such applications their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes reserves the right to make changes, without notice, in the ...
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... Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2001 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. ...