M2V64S40DTP-7L MITSUBISHI, M2V64S40DTP-7L Datasheet
M2V64S40DTP-7L
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M2V64S40DTP-7L Summary of contents
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... Burst length and full page (programmable) - Burst type- sequential and interleave (programmable) - Byte Control- DQM L and DQMU for M2V64S40DTP - Random column access - Auto precharge and All bank precharge controlled by A10 - Auto refresh and Self refresh ...
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... Vdd Vdd Vdd CLK : Master Clock CKE : Clock Enable /CS : Chip Select /RAS : Row Address Strobe /CAS : Column Address Strobe /WE : Write Enable DQ0-15 : Data I/O M2V64S20DTP M2V64S30DTP M2V64S40DTP PIN CONFIGURATION (TOP VIEW ...
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... Cell Array Bank #0 Mode Register Address Buffer A0-11 Note : This figure shows the M2V64S30DTP. The M2V64S20DTP configration is 4096x1024x4 of cell array and DQ 0-3. The M2V64S40DTP configration is 4096x256x16 of cell array and DQ 0-15. Type Designation Code DQ0-7 I/O Buffer Memory Array Memory Array 4096 x512 x8 ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 PIN FUNCTION CLK Input CKE Input /CS Input /RAS, /CAS, /WE Input A0-11 Input BA0,1 Input DQ0-3(x4), DQ0-7(x8), Input / Output DQ0-15(x16) DQM(x4,x8), Input DQM(U, L)(x16) Vdd, Vss Power Supply VddQ, VssQ Power Supply Master Clock: All other inputs are referenced to the rising edge of CLK ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 BASIC FUNCTIONS The M 2V64S20, 30 and 40DTP p rovides basic functions, bank (row) activate, burst read and write, bank (row) precharge, and auto and self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 COMMAND TRUTH TABLE COMMAND Deselect No Operation Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with Auto-Precharge Column Address Entry & ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 FUNCTION TRUTH TABLE Current State /CS /RAS /CAS /WE Address IDLE ROW ACT IVE Command Action DESEL ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address H X READ WRITE Command Action DESEL ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address H X READ with AUTO L H PRECHARGE WRITE with AUTO PRECHARGE ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address H X PRE - CHARGING ROW H X ACTIVATING Command Action DESEL ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address H X WRITE RECOVERING REFRESHING Command Action X X DESEL ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address MODE H X REGISTER SETTING ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration NOTES: 1 ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 FUNCTION TRUTH TABLE for CKE CKE CKE Current State n SELF- REFRESH POWER DOWN ALL BANKS IDLE ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 SIMPLIFIED STATE DIAGRAM MODE REGISTER SET SUSPEND CKEL WRITE SUSPEND CKEH CKEL WRITEA SUSPEND CKEH POWER APPLIED POWER ON REFS MRS IDLE CLK CKEH ACT CKEL CKEH ROW ACTIVE TERM WRITE WRITEA READA READ ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 POWER ON SEQUENCE Before starting normal op eration, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs aintain stable power, stable clock, and NOP input conditions for a minimum of 200µs. ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 CLK Read Command Address Y DQ /CAS Latency CL= 3 BL= 4 Initial Address ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 OPERATIONAL DESCRIPTION BANK ACTIVATE One of four banks is activated by an ACT command. An bank is selected by BA0-1. A row is selected by A0-11. M ultiple banks can be active state concurrently by issuing multiple ACT commands. M inimum activation interval between one bank and another bank is tRRD. ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 Multi Bank Interleaving Read (CL=2, BL=4) CLK Command ACT tRCD A0-9,11 Xa A10 Xa BA0 Read with Auto-Precharge (CL=2, BL=4) CLK Command ACT tRCD A0-9,11 Xa A10 Xa BA0 Auto-Precharge Timing (READ, BL=4) CLK Command ACT tRCD DQ CL=2 DQ CL=3 READ ACT READ tRCD ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 WRITE A WRITE command can be issued to any active bank.The start address is specified by A0-9(x4), A0-8 (x8), A0-7 (x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst Type ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 BURST INTERRUPTION [ Read Interrupted by Read ] Burst read op eration can be interrupted by new read of any active bank. Random column access is allowed. READ to READ interval is minimum 1 CLK. Read interrupted by Read (CL=2, BL=4) CLK Command READ A0-9,11 Ya A10 0 BA0 Read Interrupted by Write ] Burst read op eration can be interrupted by write of any active bank ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 [ Read Interrupted by Precharge ] A burst read operation can be interrupted by a precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. CLK Command DQ Command CL=2 DQ Command DQ Command DQ Command ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 [ Read Interrupted by Burst Terminate ] Similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. The terminated bank remains active. READ to TBST interval is minimum 1 CLK. A TBST command to output disable latency is equivalent to the /CAS Latency. ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 [ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any active bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. Write interrupted by Write (BL=4) CLK Command Write A0-9,11 Ya A10 0 BA0 Da0 [ Write Interrupted by Read ] Burst write operation can be interrupted by read of any active bank ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 [ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank. Write recovery time (tWR) is required from the last data to PRE command. During write recovery, data inputs must be masked by DQM . Write interrupted by Precharge (BL=4) ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 [ Write with Auto-Precharge Interrupted by Write or Read to another Bank ] Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT comand can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-precharge interruption by a command to the same bank is inhibited. ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 [ Read with Auto-Precharge Interrupted by Read to another Bank ] Burst read with auto-precharge can be interrupted by read to another bank. Next ACT comand can be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same bank is inhibited. ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 64M bit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto- refresh, all banks must be in idle state ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input. All other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 CLK SUSPEND and POWER DOWN CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 DQM CONTROL DQM ( dual functional signal defined as the data mask for writes and the output disable for reads. During writes, DQM (U, L) masks input data word by word. DQM ( Data In latency is ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vdd Supply Voltage VddQ Supply Voltage for Output with respect to VssQ VI Input Voltage VO Output Voltage IO Output Current Pd Power Dissipation Topr Operating Temperature Tstg Storage Temperature RECOM M ENDED OPERATING CONDITIONS ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 AVERAGE SUPPLY CURRENT from Vdd (Ta=0 ~ 70'C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, Output Open, unless otherwise noted) ITEM operating current tRC=min, tCLK =min, BL=1 , CL=3 precharge standby current in Non Power down mode /CS > Vcc -0.2V precharge standby current in Power down mode /CS > ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 AC TIM ING REQUIREMENTS (Ta=0 ~ 70'C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted) Input Pulse Levels: Input Timing Measurement Level: Parameter Symbol tCLK CLK cycle time tCH CLK High pulse width tCL CLK Low pulse width ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 SWITCHING CHARACTERISTICS (Ta=0 ~ 70'C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted) SWITCHING CHARACTERISTICS (Ta=0 – 70'C, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted ) Symbol Parameter tAC Access time f rom CLK Output Hold time tOH f rom CLK ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 Burst Write (Single Bank) [BL= CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9,11 X BA0 ACT#0 WRITE tRC tRAS tRP tWR PRE#0 MITSUBISHI ELECTRIC (4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x 8-BIT) ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 Burst Write (Multi Bank) [BL= CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9,11 X BA0 ACT#0 WRITE tRC tRC tRAS tRP tRCD tWR ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 Burst Read (Single Bank) [CL=2, BL= CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9,11 X BA0 ACT#0 READ tRC tRAS tRP PRE#0 ACT #0 READ#0 MITSUBISHI ELECTRIC ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 Burst Read (Multi Bank) [CL=2, BL= CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9,11 X BA0 ACT#0 READA tRC tRC tRCD ACT #0 READ#0 ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 Write Interrupted by Write [BL= CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9,11 X BA0 ACT#0 WRITE WRITE#0 WRITEA#1 interrupt interrupt ACT#1 ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 Read Interrupted by Read [CL=2, BL= CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9,11 X BA0 ACT#0 READ tRCD READ#1 READA#1 interrupt interrupt ACT#1 ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 Write Interrupted by Read, Read Interrupted by Write [CL=2, BL= CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9,11 X BA0 ACT#0 ACT tRCD WRITE#0 READ#1 MITSUBISHI ELECTRIC ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 Write / Read Terminated by Precharge [CL=2, BL= CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9,11 X BA0 ACT#0 WRITE tRP tWR ACT#0 PRE#0 Terminate MITSUBISHI ELECTRIC (4-BANK x 4,194,304-WORD x ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 Write / Read Terminated by Burst Terminate [CL=2, BL= CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9,11 X BA0 ACT#0 WRITE READ#0 TERM TERM MITSUBISHI ELECTRIC (4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x 8-BIT) ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 Single Write Burst Read [CL=2, BL= CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9,11 X BA0 ACT#0 WRITE#0 READ MITSUBISHI ELECTRIC (4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 Power-Up Sequence and Intialize CLK 200µs /CS /RAS /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ NOP Power On PRE ALL tRP tRFC REFA REFA Minimum 8 REFA cycles Italic paramater shows minimum case MITSUBISHI ELECTRIC (4-BANK x 4,194,304-WORD x ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 Auto Refresh CLK /CS tRP /RAS /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ PRE ALL REFA All banks must be idle before REFA is issued tRFC ACT#0 Italic paramater shows minimum case MITSUBISHI ELECTRIC ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 Self Refresh CLK /CS tRP /RAS /CAS /WE CKE DQM A0-8, A10 A9,11 BA0,1 DQ PRE ALL Self Refresh Entry All banks must be idle before REFS is issued Italic paramater shows minimum case MITSUBISHI ELECTRIC ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 CLK Suspension [CL=2, BL= CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9,11 X BA0 ACT#0 WRITE internal READ#0 CLK suspended MITSUBISHI ELECTRIC (4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 Power Down CLK /CS /RAS /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ PRE ALL Standby Power Down ACT #0 Italic paramater shows minimum case MITSUBISHI ELECTRIC (4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x 8-BIT) ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 Revison History Date Rev. 1.0 Jun '99 2.0 July '99 3.0 Oct. '99 3.1 Oct. '99 Description -1st edition -single write mode is added -Icc5 for -6 is changed form 110mA to 130mA -tRFC is added -tRSC is changed -tSRX and tPDE are removed -tWR is changed to 12ns ...
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... M2V64S20DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V64S30DTP-6,-6L,-7,-7L,-8,-8L SDRAM (Rev.3.2) M2V64S40DTP-6,-6L,-7,-7L,-8,-8L Feb.'00 Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum ef f ort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury , f ire or property damage ...