M32000D4AFP MITSUBISHI, M32000D4AFP Datasheet
M32000D4AFP
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M32000D4AFP Summary of contents
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... DRAM and this is then executed. The M32000D4AFP also has a slave mode additional to its master mode. When set to slave mode the M32000D4AFP can be used as a coprocessor. In this mode it does not access its external bus immediatly after reset, but waits for the master to start its operation. ...
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... VCC 91 VSS 92 VCC 93 94 WKUP VCC 95 D11 96 D10 VSS 100 2 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER M32000D4AFP 100-pin QFP/0.65 mm pitch Note: Connect *1 pins to VCC. M32000D4AFP 50 VSS VCC 44 VCC 43 VSS 42 VSS 41 VCC 40 HREQ HACK 39 SBI 38 INT ...
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... MITSUBISHI MICROCOMPUTERS M32000D4AFP M32000D4AFP RST M/S multiply- accumulate unit bits INT MUL + SBI 56-bit -ACC WKUP STBY PP0 programmable I/O port PP1 ...
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... MHz) logical address space: linear 4G bytes external address bus: 24 bits (external output pin A30, BCH, BCL) external data bus: 16 bits general-purpose registers: 32 bits 16 control registers: 32 bits 5 16-bit/32-bit instruction format 83 instructions/6 addressing modes MITSUBISHI MICROCOMPUTERS M32000D4AFP ____ ____ ...
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... SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER SID CLKIN BCL PLLCAP BCH PLLVCC BS PLLVSS ST R/W RST BURST M/S DC WKUP HREQ STBY HACK A30 INT SBI D15 PP0 PP1 16 15 VCC VSS MITSUBISHI MICROCOMPUTERS M32000D4AFP bus control interrupt input programmable I/O port 5 ...
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... CPU sleep mode. input Sets the M32000D4AFP default operation to either system bus master (M/S = "H") or bus slave (M/S = "L"). When the M32000D4AFP is set to bus slave, it does not carry out a reset vector entry fetch after a reset. _ The setting of M/S cannot be changed during operation. ...
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... When accessing the internal DRAM from an external bus master, the byte control signal is input from the system bus side. output When the M32000D4AFP drives an external bus cycle, BS goes to an "L" level at the start of the bus cycle. (Hi-z burst transfer, BS goes to the " ...
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... INT external interrupt programm- PP0, PP1 port able I/O port __ * The DC pin becomes an output pin when the CS signal is input to the M32000D4AFP. 8 SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER I/O function I/O When the M32000D4AFP drives an external bus cycle, it (Hi-z) automatically inserts wait cycles until DC is input by the slave device in the system bus ...
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... R8 Notes 1: CRn ( denotes the control register number. R9 R10 R11 R12 Fig. 2 Control registers R13 (see note) MITSUBISHI MICROCOMPUTERS M32000D4AFP 0 31 CR0 PSW processor status word register CR1 CBR condition bit register CR2 SPI interrupt stack pointer ...
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... C bit when EIT occurs 0: uses R15 as the interrupt stack pointer 1: uses R15 as the user stack pointer 0: does not accept interrupt 1: accepts interrupt indicates carry, borrow and overflow resulting from operations (instruction dependent) MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER PSW field ...
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... RTE instruction is executed. However, the values of the lower 2 bits of the PC become "00" on returning (It always returns to the word boundary SPI SPU BPC MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER ...
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... Since the M32R CPU in- struction starts with even-numbered addresses, the LSB (bit 31) is always "0". read range with MVFACMI instruction MVTACLO or MVFACLO instruction An attempt to write to this area is ignored. PC MITSUBISHI MICROCOMPUTERS M32000D4AFP read/write range with 31 0 ...
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... LDUB instruction byte from memory (LDH, LDUH instruction) byte 31 halfword 31 halfword word 24 31 byte to memory (STB instruction) 31 halfword to memory (STH instruction) 31 MITSUBISHI MICROCOMPUTERS M32000D4AFP address + byte byte byte byte halfword halfword word 31 13 ...
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... Address space The M32000D4AFP logical address is 32-bit wide and offers 4 GB linear space. The M32000D4AFP has address spaces allocated as shown below. The user space is specified by SID = 0 (H'0000 0000 to H'7FFF FFFF). The area available to the user from address H'0000 0000 to address H'00FF FFFF. ...
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... H'0000 0000 to address H'0000 008F of this area. The internal DRAM is connected to the M32R CPU via cache memory with a 128-bit bus. When the M32000D4AFP is in the hold state, the internal DRAM can be accessed from an external bus master by inputting control signals. ...
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... It has the highest priority. • Wakeup interrupt (WI) The wakeup interrupt (WI) is accepted when the WKUP signal is input while the M32000D4AFP is in standby mode only used to return from standby mode. • System break interrupt (SBI) The system break interrupt (SBI interrupt request from the SBI pin ...
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... Internal memory system The memory system built into the M32000D4AFP has the following characteristics. • internal 16M-bit (2M-byte) DRAM • internal 4K-byte cache memory • CPU, cache and internal DRAM are connected by a 128-bit bus • selectable cache memory operation mode – ...
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... CPU cache Fig. 14 Instruction cache mode 18 SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER When the cache-off mode is selected, the M32000D4AFP internal memory system is configured as follows. In this mode, caching is not applied, and all bus cycles are directly to the internal DRAM or exter- nal bus. M32000D4AFP CPU ...
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... BCH and/or BCL "L" level depending on the bytes to be written. If the M32000D4AFP is in the hold state and the internal DRAM is accessed from an external bus master, the byte control signal is input from the system bus side. ...
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... Internal DRAM access control (CS) The internal DRAM can be accessed when CS is driven to an "L" level after the M32000D4AFP enters the hold state (HACK = "L"). To access the internal DRAM from external, the following signals from the system bus side should be controlled. ...
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... When an "L" level is input to DC, the next bus cycle is processed and wait cycles are inserted until this point. When a write cycle comes immediately after a read cycle, the M32000D4AFP inserts an idle cycle to prevent a collision with data on the system bus. The same applies to write cycles (burst write access) immediately after a burst read cycle ...
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... The M32000D4AFP outputs the BURST signal and carries out a burst transfer when reading "the word-size data aligned on the 32-bit bound- ary" or "a maximum 4 words of instructions aligned on the 128-bit ______ boundary". The BURST signal is synchronized with the CLKIN falling edge of the first bus access cycle and output "L" level. It returns to an " ...
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... After returning from the hold state, an idle cycle CLKIN clock periods is always inserted. 2: "Hi-z" means high impedance, and indicates sampling timing. 3: While the M32000D4AFP is in the hold state, the DC signal is driven and output when the CS signal is input. _____ (see note 1) ...
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... When the M32000D4AFP is in the hold state and an "L" level is input __ to CS, the M32000D4AFP interprets bus access request to the internal DRAM. In this case, when the R/W signal is an "H" level, the memory controller drives a read cycle to the internal DRAM. In ...
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... When the M32000D4AFP is in the hold state and an "L" level is input __ to CS, the M32000D4AFP interprets bus access request to the internal DRAM. In this case, when the R/W signal "L" level, the memory controller drives a write cycle to the internal DRAM. ...
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... This is normal operation mode. Set the M/S pin to an "H" level used when the M32000D4AFP is used as the main CPU in a system. _ • slave mode (M/S = "L") This operation mode is for when the M32000D4AFP is used coprocessor. Set the M/S pin to an " ...
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... DRAM are retained. The power requirement is only that which the internal DRAM needs for refreshing itself. When set to standby mode, the M32000D4AFP waits for the current bus operation to be completed. It then purges the cache memory and switches the inter- nal DRAM to self-refresh mode. After that, the PLL and all clock sup- plies stop and the STBY signal goes to an " ...
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... W = Fig. 31 Programmable I/O port data register 28 Reset When an "L" level is input to RST, the M32000D4AFP switches to the reset state. The reset state is released when an "H" level is input ____ to RST, and the program is executed from the EIT vector entry of the reset interrupt. All internal resources including the internal PLL (4x clock generator) are initialized. In order to stabilize PLL oscillation, the " ...
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... Clock generating circuit The M32000D4AFP has a clock multiplier circuit and operates at four times the input frequency. The internal operation frequency be- comes 66.6 MHz when a 16.65 MHz clock is input to CLKIN. A ca- pacitor (C) should be connected to the PLLCAP pin, and the clock is input to the CLKIN pin. The PLLVCC and PLLVSS pins should be connected to the power source or the ground, respectively ...
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... ADD ADD3 ADDI ADDV ADDV3 ADDX NEG SUB SUBV SUBX MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Load Load byte Load unsigned byte Load halfword Load unsigned halfword Load locked Store Store byte Store halfword Store unlocked ...
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... Branch JL Jump and link JMP Jump NOP No operation MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER <EIT-related instructions> The EIT-related instructions carry out the EIT events (Exception, In- terrupt and Trap). Trap initiation and return from EIT are EIT-related instructions. TRAP Trap RTE Return from EIT < ...
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... SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Conditions TOPR = 25 °C (VCC = 3.3 V ± 0.3 V, TOPR = °C unless otherwise noted) Parameter All inputs except following ____ RST pin All inputs except following ____ RST pin MITSUBISHI MICROCOMPUTERS M32000D4AFP Ratings Unit Min. Max. 4.6 V –0.5 4.6 V –0.5 4.6 V –0.5 ...
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... Test conditions IOH = –2 mA IOL = VCC VIH = 0 to VCC +0.3 V VIH = 0 to VCC +0.3 V Average in normal operation mode VCC = 3.3 V Average in CPU sleep mode VCC = 3.3 V Average in standby mode VCC = 3.3 V All pins MITSUBISHI MICROCOMPUTERS M32000D4AFP Ratings Unit Min. Typ. Max. 2.4 V 0.4 V –10.0 10.0 µA 10.0 µ ...
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... Min. CMOS input ____ RST pin CMOS input ____ RST pin Limits Test conditions Min. 60 1/4CLKIN 1/4CLKIN 2 2 Limits Test conditions Min. 5 M32000D4AFP Reference Unit number Max Reference Unit number Max. ns 100 ...
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... Note: Both INT and SBI are level-sense inputs. Keep them at an "L" level until the interrupt is accepted. (6) I/O port timing Symbol Parameter tw(PORTINL) Port input “L” pulse width tw(PORTINH) Port input “H” pulse width MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Limits Test conditions Min. Max ...
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... Data output effective time after CLKIN td(CLKIN-DXZ) Data output disable time after CLKIN 36 (VCC = 3.3 ± 0 pF, TOPR = °C unless otherwise noted) Test conditions Test Parameter conditions MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Limits Unit Typ. Min. Max Limits Unit Min ...
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... Note: The minimum pulse width value is that where the output is changed within 1 clock of the internal clock. Software processing time to write to the port data register is not included. Test conditions Parameter __ Test conditions Parameter Test conditions MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Limits Unit Max. Min ...
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... VCC 0.0 V VCC 0.0 V timing reference point "H" "Z" 0.9VCC 0.1VCC "L" "Z" MITSUBISHI MICROCOMPUTERS M32000D4AFP 0. timing reference point (when not specified) 0.8VCC 0.2VCC 0.9VCC 0.1VCC 0.8VCC 0.2VCC "Z" ...
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... The WKUP and RST signals can be input asynchronously. When returning from standby mode, the same timing applies. MITSUBISHI MICROCOMPUTERS M32000D4AFP 2 t f(INPUT) 0.8VCC 0.2VCC 2 t f(INPUT) 0.9VCC 0.1VCC 0.8VCC 0.2VCC ...
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... MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER *2 *2 d(CLKIN-AX) d(CLKIN-BCX d(CLKIN-SIDX d(CLKIN-STX d(CLKIN-RWX d(CLKIN-BURSTLX d(CLKIN-BURSTH) *2 h(CLKIN-D) t d(CLKIN-DVX d(CLKIN-DXZ) ...
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... Fig. 41 Bus arbitration timing 0.5VCC 0.5VCC * su(HREQ-CLKIN) h(CLKIN-HREQ d(CLKIN-HACKHX d(CLKIN-HACKL d(CLKIN-AZ) MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER * d(CLKIN-HACKLX d(CLKIN-HACKH) t d(CLKIN-AZX ...
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... M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 41 t h(CLKIN-HREQ d(CLKIN-HACKLX d(CLKIN-HACKH su(D-CLKINL) t h(CLKINL- d(CLKIN-DXZ ...
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... WKUP has returned from "L" to "H" CLKINs after sampling that RST = "L". Fig. 44 Standby timing [for input] PX [for output] PX Fig. 45 I/O port timing MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER * w(INT) w(SBI d(CLKIN-STBYHX d(CLKIN-STBYL w(PORTINL) t w(PORTINH w(PORTOUTL) t w(PORTOUTH) M32000D4AFP t d(CLKIN-STBYLX d(CLKIN-STBYH) 43 ...
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... Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. © 1998 MITSUBISHI ELECTRIC CORP. Revised edition, effective May. 1998 Specifications subject to change without notice. MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER ...
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... Arbitration and external bus master read/write timing Symbol Parameter ~ ~ __ td(CS-DCZX) DC output enable time after CS •" 58 td(CS-DCZX) " in Fig. 42 corrected (page 42). *1 • Notes in Figure 44 revised (page 43). 1.2 • Figure 23 revised (page 24). M32000D4AFP DATA SHEET Revision Description ~ __ corrected (page 37). (1/1) Rev. date 970901 980501 980911 ...