MC74HCT373AFL1 ON Semiconductor, MC74HCT373AFL1 Datasheet

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MC74HCT373AFL1

Manufacturer Part Number
MC74HCT373AFL1
Description
Octal 3-State NonInverting Transparent Latch with LSTTL-Compatible Inputs
Manufacturer
ON Semiconductor
Datasheet
MC74HCT373A
Octal 3-State Noninverting
Transparent Latch with
LSTTL-Compatible Inputs
High–Performance Silicon–Gate CMOS
interfacing TTL or NMOS outputs to High–Speed CMOS inputs.
While the Latch Enable is high the Q outputs follow the Data Inputs.
When Latch Enable is taken low, data meeting the setup and hold
times becomes latched.
Output Enable is high, all outputs are forced to the high–impedance
state. Thus, data may be latched even when the outputs are not
enabled.
the input pins on the opposite side of the package from the output pins.
This device is similar in function to the HCT533A, which has
inverting outputs.
March, 2000 – Rev. 8
The MC74HCT373A may be used as a level converter for
The HCT373A is identical in pinout to the LS373.
The eight latches of the HCT373A are transparent D–type latches.
The Output Enable does not affect the state of the latch, but when
The HCT373A is identical in function to the HCT573A, which has
No. 7A
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS–Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 A
In Compliance with the Requirements Defined by JEDEC Standard
Chip Complexity: 196 FETs or 49 Equivalent Gates
Semiconductor Components Industries, LLC, 2000
1
20
MC74HCT373AN
MC74HCT373ADW
MC74HCT373ADWR2 SOIC–WIDE
MC74HCT373ADT
MC74HCT373ADTR2
20
20
1
1
Device
ENABLE A
1
ORDERING INFORMATION
A
WL = Wafer Lot
YY = Year
WW = Work Week
GND
YB3
YB4
YB2
YB1
SOIC WIDE–20
A1
A2
PIN ASSIGNMENT
A3
A4
http://onsemi.com
DW SUFFIX
CASE 751D
= Assembly Location
CASE 948G
DT SUFFIX
TSSOP–20
1
2
3
4
5
6
7
8
9
10
CASE 738
N SUFFIX
PDIP–20
SOIC–WIDE
TSSOP–20
TSSOP–20
Publication Order Number:
Package
PDIP–20
20
19
18
17
16
15
14
13
12
11
MC74HCT373A/D
20
MC74HCT373AN
20
1
1
V CC
ENABLE B
YA1
B4
YA2
B3
YA3
B2
YA4
B1
DIAGRAMS
MARKING
AWLYYWW
AWLYYWW
20
HCT373A
1
1000 / Reel
2500 / Reel
1440 / Box
Shipping
38 / Rail
75 / Rail
ALYW
373A
HCT

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MC74HCT373AFL1 Summary of contents

Page 1

MC74HCT373A Octal 3-State Noninverting Transparent Latch with LSTTL-Compatible Inputs High–Performance Silicon–Gate CMOS The MC74HCT373A may be used as a level converter for interfacing TTL or NMOS outputs to High–Speed CMOS inputs. The HCT373A is identical in pinout to the LS373. ...

Page 2

LOGIC DIAGRAM DATA D3 INPUTS LATCH ENABLE 1 OUTPUT ENABLE Î Î Î Î Î Î ...

Page 3

... SOIC Package: – from 125 _ C TSSOP Package: – 6.1 mW from 125 _ C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Î Î Î Î ...

Page 4

... NOTE: 1. Total Supply Current = NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS Î Î Î Î Î ...

Page 5

LATCH 11 ENABLE OUTPUT 1 ENABLE 2.7 V INPUT D 1 PLH 90% 1 10% t TLH Figure 1. ...

Page 6

TEST POINT OUTPUT DEVICE UNDER TEST *Includes all probe and jig capacitance Figure 5. MC74HCT373A TEST CIRCUITS TEST POINT 1 k OUTPUT DEVICE UNDER TEST *Includes all probe and jig capacitance Figure 6. http://onsemi.com ...

Page 7

SEATING PLANE 0.25 (0.010 20X T 0. 18X MC74HCT373A PACKAGE DIMENSIONS PDIP–20 N SUFFIX PLASTIC DIP PACKAGE CASE 738–03 ...

Page 8

... CENTRAL/SOUTH AMERICA: Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST) Email: ONlit–spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001–800–4422–3781 Email: ONlit– ...

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