M5M410092BRF MITSUBISHI, M5M410092BRF Datasheet
M5M410092BRF
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M5M410092BRF Summary of contents
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Overview of 3D-RAM and Its Functional Blocks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pixel ALU Operations Elements of the Pixel ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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DRAM Operations Masked Write Block (MWB ...
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Packaging ...
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Formal Specification of Operations Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Revision History 0 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Revision History Rev. 0.95 • First version of distributed databook Rev. 0.96 • Chapter 2 • The “Total” entry in Table 2.2 on pp. 19 was corrected. • Entries in Table 2.6 on pp. 22 were cor- rected. • Tracking label mnemonic was corrected to show the speed grade “-12”. ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP • Chapter 7 • The speed grade “-10A” was added to all tables. • Entries in Table 7.4 on pp. 117 and 118, Table 7 119, Table 7 120, and Table 121 were corrected. • Chapter 8 • The speed grade “-10A” was added to all tables. • ...
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Overview of 3D-RAM and Its Functional Blocks 1 ...
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... In addition to the performance boost, the new architecture also significantly reduces the system chip count. In 1994 Mitsubishi pioneered the introduction of the first member of the 3D-RAM family of products. This databook specifies all the features and operations of the third generation product of the 3D-RAM family to further elevate the performance of the 3D-RAM based 3D graphics systems ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 8-bit color components— a—for all 1280 x 1024 pixels; (2) Each 3D-RAM holds all 32 bits of a pixel value for 320 x 1024 pixels, allowing fast scrolling in the vertical direction and interleaving four 3D-RAMs in the horizontal direction. If the width of the data bus from the rendering System Interface Address & ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Simplified 3D-RAM Block Diagram The 3D-RAM block diagram is shown in Figure 1.2. The DRAM array is partitioned into four independent banks of 2.5 Mbits each. Together, these four banks can support a screen resolution of 1280 x 1024 x 8. The independent banks can be interleaved to facilitate almost ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 3D-RAM Functional Blocks The 3D-RAM has five major functional blocks in: DRAM banks, Video Buffers, Pixel Buffer, Global Bus, and Pixel ALU. The following sections provide a quick overview of each of these functional blocks. Chapter 3 describes details of the Pixel ALU operations, Chapter 4 presents ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Global Bus 256 Pixel Buffer Block 0 7:0 15:8 23:16 31:24 Word 0 in Block 0 Figure 1.3 Relations and addressing scheme of blocks and words in the Pixel Buffer and in the DRAM page 256 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP DRAM Banks and Basic DRAM Operations The 3D-RAM contains four independent DRAM banks which can be interleaved to facilitate hidden precharge or access in one bank while screen refresh is being performed in another bank. Each DRAM bank has 256 pages with 10,240 bits per page for a total storage of 2,621,440 bits ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Pixel Buffer The Pixel Buffer is a 2048-bit SRAM organized into eight 256-bit blocks, as seen in Figure 1.3, and functions as a level-one write-back pixel cache. It has a 256-bit read/write port, a 32-bit read port, and a 32-bit write port. Referring to Figure 1.6, the 256-bit read/write port is ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Global Bus The Global Bus connects the Pixel Buffer to the sense amplifiers of all four DRAM banks. The Global Bus consists of 256 data lines. Referring to Figure 1.6, during a transfer from the Pixel Buffer to DRAM, the 256 bits are conditionally written depending on the 32-bit Dirty Tag and the 32-bit Plane Mask ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Pixel ALU Basics The Pixel ALU consists of four 8-bit ROP/Blend units, which may be independently programed to perform either a raster operation or a blending function, one 32-bit Match Compare unit, and one 32-bit Magnitude Compare unit. The two Compare units are also commonly referred to as the Dual Compare units ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP corresponding color chips important to note that due to the pipelining, the color chips do not wait for the magnitude comparison results from the Z chips; rather, the results of the ROP/ blending operations and comparison operations on the color chips, and the results of the ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Pipelining The 3D-RAM Pixel ALU pipeline is designed so that read and write operations can be performed with minimal delay. This is achieved by having all operations conform to a uniform 7-stage pipeline. Figure 1 example that illustrates the efficiency afforded by the pipeline flow of Pixel ALU read/write operations ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP The Picking Logic From the user’s view point, a common experience of the picking function in 2D computer graphics may be using the mouse and the associated cursor to select an icon on the display screen, resulting in the selected icon highlighted in a different color. This is a basic function in ...
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Pin Descriptions and Pinouts 2 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Pin Descriptions and Pinouts This chapter describes the 3D-RAM pins. Unless otherwise specified, all signals comply with the Low Voltage TTL (LVTTL) standard. The functional block diagram in Figure 2.1 shows all I/O signals on the external pins. The master clock MCLK synchronizes all operations of the Pixel ALU Control and DRAM Covntrol ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP DRAM Bank A 640 Video Buffer I 640 DRAM Bank C SCAN_RST SCAN_TCK Test Access SCAN_TMS Port SCAN_TDI SCAN_TDO Figure 2.1 3D-RAM functional block diagram with external pins DRAM Bank B 640 16 Video Buffer II 256 640 DRAM Bank D 32 SRAM Pixel ALU ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Pixel ALU Interface These signals control the Pixel ALU and Pixel Buffer. Table 3.2 Pixel ALU control signals Signal Name Pin Count PALU_EN 2 PALU_WE 1 PALU_OP 3 PALU_A 6 PALU_BE 4 PALU_DQ 32 PALU_DX 4 PASS_OUT 1 PASS_IN 2 HIT 1 Total 56 PALU_EN [1:0] The PALU_EN pins must be “11” to start [1:0] a Pixel ALU operation ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP PALU_DX [3:0] Extra high-order bits of PALU_DQ data are provided by PALU_DX . PALU_DX0 is [3:0] associated with PALU_DQ[ 7:0] associated with PALU_DQ [15:8] is for PALU_DQ ; and PALU_DX3 is for [23:16] PALU_DQ . [31:24] PASS_OUT The comparison result of the Dual Compare unit is output on the PASS_OUT pin. PASS_OUT is low (“0”) only when the Pixel ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP DRAM_A [8:0] The address pins DRAM_A [8:0] select one of the following: (i) a page in a DRAM bank, (ii) a block of data to be trans- ferred between the sense amplifiers of a DRAM bank and the Pixel Buffer over the Global Bus, or (iii) 80 bytes of video data from the sense amplifiers of a DRAM page to a Video Buffer ...
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... Tracking Label On the top surface of the 3D-RAM package, a Description tracking label is printed below the Mitsubishi logo and the 3D-RAM product number. The tracking label consists of 7 numbers followed by a dash and a speed/power grade designation and is represented by the mnemonic “DDDMMMMM-nn”. ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Normal Pinout Diagram SCAN_TMS 1 SCAN_TCK 2 SCAN_RST 3 VID_Q 4 8 VID_Q VID_Q 7 10 VID_Q 8 11 VID_Q 9 12 VID_Q VID_Q 12 14 VID_Q 13 15 VID_QSF 14 VID_CKE PASS_IN VID_CLK PASS_IN ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Reverse Pinout Diagram V 102 DD PALU_DQ 101 27 PALU_DQ 100 26 PALU_DQ 99 25 PALU_DQ PALU_DQ 96 23 PALU_DQ 95 22 PALU_DQ 94 21 PALU_DQ PALU_DQ 91 19 PALU_DQ 90 18 PALU_DQ 89 17 PALU_DQ PASS_OUT MCLK ...
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Pixel ALU Operations 3 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Pixel ALU Operations This chapter discusses details on the elements and operations of the Pixel Buffer and Pixel ALU in 3D-RAM. An operation that involves only the Pixel ALU and the Pixel Buffer is called a Pixel ALU operation. An operation that involves a DRAM array is categorized as a DRAM operation and is described in Chapter 4, “ ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Dirty Tag Each data byte of a 256-bit block is associated with a Dirty Tag bit. This means that each 4-byte word is associated with four Dirty Tag bits and that a 32-bit Dirty Tag memory controls the corresponding 32-byte block data. The Dirty Tag RAM in the Pixel Buffer contains eight such 32-bit Dirty Tags ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP The Dirty Tag bits play an important role for all four write operations of the Pixel ALU to the Pixel Buffer: Stateful/Stateless Initial Data Write and Stateful/Stateless Normal Data Write. (These operations are also explained in “Pixel ALU Operations” on page 56.) Since the Pixel ALU ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP A particular sense amplifier bit can be written only if both the Dirty Tag bit and the Plane Mask bit are logically “1”. This kind of relationship among multiple enables and block data is illustrated in Figure 3.2 for the first 40 bits (which are Word 0 and byte 0 of Word 1) of the Global Bus ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Elements of the Pixel ALU Chapter 2 presented an overview of the Pixel ALU, with an emphasis on the motivation and applications of the elements in the Pixel ALU. In this section, some of the same information is repeated, but the emphasis is on detailed technical specification. The elements of the Pixel ALU are four 8-bit ROP/ ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP ROP/Blend Units Each ROP/Blend unit can be independently configured as either a ROP unit or a Blend unit through the programming of the ROP/Blend Control register. Each ROP unit can perform all 16 standard ROP functions, which are listed in Table 3.16. ROP functions are performed on a byte of the Old Data (“ ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 3.2 Source and Destination Blending Factors OpenGL Parameter GL_ZERO GL_ONE GL_DST_COLOR GL_SRC_COLOR GL_ONE_MINUS_DST_COLOR GL_ONE_MINUS_SRC_COLOR GL_SRC_ALPHA GL_ONE_MINUS_SRC_ALPHA GL_DST_ALPHA GL_ONE_MINUS_DST_ALPHA GL_SRC_ALPHA_SATURATE GL_CONSTANT_COLOR_EXT GL_ONE_MINUS_CONSTANT_COLOR_EXT GL_CONSTANT_ALPHA_EXT GL_ONE_MINUS_CONSTANT_ALPHA_EXT can be completed in two consecutive cycles using the 3D-RAM’s Two-Cycle Blend operation by looping back during the first cycle one of the two ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 3.3OpenGL blending factor selection matrix 3D-RAM (M5M410092B) BLANK SPACE BLANK SPA 28 Rev. 1.03 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP registers have been programmed, an “Initial Two- Cycle Blending” operation (PALU_OP=110, PALU_WE=1) should be performed and followed by a Stateful Initial Data Write or Stateful Normal Data Write operation on the same pixel location (i.e. PALU_A with the same Block and Word ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 8 O [8n+7:8n [8n+7:8n [8n+7:8n] O [31:24] sat* N [31:24 { [31:24] 9 100h 8 Figure 3.4 ROP/Blend unit n (Pipeline stages ar not shown [31:24] O [31:24] Figure 3.5 Block diagram of the Alpha-Saturate unit 8 ROP 8 1 stage delay ADDEND stage delay Mult ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP PALU_BE CDS [0] RBC [8n+5] BLD2 nibble nibble [8n] 8 mode DUP [8n+7:8n] direction Out 8 [8n+7:8n [8n+7:8n] BLD2 [8n Preblend Command Cycle (PALU_OP =110) [2:0] RBC [8n+6] RBC [8n+ BLD2 00 [8n+ ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 1 2 MCLK PALU_EN, PALU_BE, PALU_WE 111 111 PALU_OP 000100 001000 PALU_A Data PALU_DQ,DX Control Register Pixel Buffer PASS_IN PASS_OUT Figure 3.7 An Example of a Two-Cycle Blend operation 111 110 010 or 011 Block:Word 001001 Preblend Normal Data Data ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP The mathematic operations performed in the Blend unit are summarized in Table 3.4. The Clamped Result is written to the Pixel Buffer, depending (1) on the PASS_OUT pin, which is the Table 3.4 Mathematical operations in Blend unit n Operand Range Multiplicand 1 0.00h ~ 0.FFh (8-bit unsigned) 0.00h ~ 0.FFh (8-bit unsigned) 0 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP The “Alpha” value, denoted as As and Ad, should be placed at the most significant byte of the respective bus, i. which is from [31:24] PALU_DQ ; and Ad at the O [31:24] [31:24] from the Pixel Buffer. Table 3.5 lists possible multiplicand/addend selections for each OpenGL blending mode. Note that the “Preblend Cycle” ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 3.5 Multiplicand/Addend selection for each OpenGL blending factor pairs Blending Fractions sfactor dfactor MULTP1 1–Ad, 1– Ck 1–Ck, 1– Ak 1–Ak, 1– Cs Cs, As ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 3.5 Multiplicand/Addend selection for each OpenGL blending factor pairs Blending Fractions sfactor dfactor MULTP1 1–Ck, 1–Ak 1–Cs, 1–As x Ak, Ak 1–Cs, 1–As x 1–Ak, 1–Ak 1–Cs, 1– Cd, Ad As, As Cs, As 1–Cd, 1–Ad ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 3.5 Multiplicand/Addend selection for each OpenGL blending factor pairs Blending Fractions sfactor dfactor MULTP1 1–Ck, 1–Ak 1–As, 1–As x Ak, Ak 1–As, 1–As x 1–Ak, 1–Ak 1–As, 1– Cd, Ad Ad, Ad Cs, As 1–Cd, 1–Ad ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 3.5 Multiplicand/Addend selection for each OpenGL blending factor pairs Blending Fractions sfactor dfactor MULTP1 Cd, Ad Ck, Ak Cs, As 1-Cd, 1-Ad Ck, Ak Cs, As As 1–As, 1–As Ck Ad, Ad Ck, Ak Cs, As 1–Ad, 1–Ad Ck, Ak ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 3.5 Multiplicand/Addend selection for each OpenGL blending factor pairs Blending Fractions sfactor dfactor MULTP1 Ck, Ak 1–Ck, 1–Ak x 1–Ck, 1–Ak 1–Ck, 1–Ak x Ak, Ak 1–Ck, 1–Ak x 1–Ak, 1–Ak 1–Ck, 1– Cd, Ad ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 3.5 Multiplicand/Addend selection for each OpenGL blending factor pairs Blending Fractions sfactor dfactor MULTP1 Ad, Ad 1–Ak, 1–Ak Cs, As 1–Ad, 1–Ad 1–Ak, 1–Ak Cs 1–Ak, 1–Ak Cs, x Ck, Ak 1–Ak, 1–Ak x 1–Ck, 1–Ak 1–Ak, 1–Ak x Ak, Ak 1–Ak, 1–Ak x 1– ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP StF.FUNC StF.Mask [7:0] StF.MASK StF.REF OLD [31:24] OLD PALU_DQ [31:24 [31:24] StC Magnitude [19] Figure 3.8 Operations of OpenGL stencil mode The Stencil Function block compares the magnitude of the stencil reference data, StF.REF, to the OLD stencil data that is read from the Pixel Buffer. A mask for the stencil data is available which provides the capability to ignore certain bits in the stencil data comparison ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP the stencil planes. The pseudo code below summarizes the above explanations in a concise format. Note that the expression “St.Test(StF)” refers to an OpenGL stencil test based on the stencil function selected in the glStencil_Func. The glStencil_Func should set and reset the bits in the 3D-RAM Stencil Planes register and Stencil Control register ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP IF (StC[19]==0) StF.REF=PALU_DQ[31:24] ELSE StF.REF=K[31:24] IF( ((!PINS[0]||PASS_IN[0]) && (!PINS[8]||PASS_IN[1]) && MATCH_COMP)== Pixel_Buffer_Write_Enable_Byte[3:0]=0000b PASS_OUT=0 } ELSE /* match test passes and both PASS_IN */ /* pins TRUE IF ( St.Test(StF)== Pixel_Buffer_Write_Enable_Byte[3:0] =1000b For bits disabled by St.Enable[7:0] Pixel_Buffer_Data_In[31:24]=OLD[31:24] For bits enabled by St.Enable[7:0] Pixel_Buffer_Data_In[31:24] =StOP ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP The decal stencil mode may be selected by setting the Compare Control register bit 10 to “1”. In this mode, the internal Pixel Buffer write enable for a stateful write is no longer solely controlled by PASS_IN and PASS_OUT. The added [1:0] condition to the write enable signal generation is ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Write DQ Control “Write” PALU_BE [ PALU_BE [ PALU_BE [ PALU_BE [0] 0 Figure 3.9 Data mapping in the ( color mode Write DQ Control “Write” 31 PALU_BE A [3] PALU_BE B [1] R PALU_BE A [3] R PALU_BE B [1] G PALU_BE A [2] G PALU_BE B [0] ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP The solid black arrows correpond to data flow of Buffer A, and the gray arrows correspond to data flow of Buffer B. During write operations, the 4-bit data may be duplicated or padded with zeros in the lower nibble when processed by the byte-wide Pixel ALU; after the Pixel ALU processing, the ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 3.8 Byte Enable controls and color data placement in ( mode PALU_DQ [31:28] NBL 7 PALU_BE 3 Color Data The following is how PALU_BE [3:0] ( mode Read Data, Stateless Initial/Normal Write operations • PALU_BE may be any combination [3:0] (decoded as in Table 3.7) ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 3.9 Pixel ALU operations involving Dirty Tags in ( mode Pixel Operation Pixel Data (Stateful/Stateless) Write to Buffer A from PALU_DQ Normal Data Write pins (per PALU_BE (Stateful/Stateless) Write to Buffer B from PALU_DQ Normal Data Write pins (per PALU_BE (Stateful/Stateless) ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 32-bit Dirty Tag Figure 3.12 PALU_BE Mapping to Dirty Tags for (4,4,4,4) Mode ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 4-bit to 8-bit Expansion for Pixel ALU Blending The Pixel ALU blending function operates on 8-bit components. To implement the 8-bit blending operation on a 4-bit color component necessary to expand the 4-bit data (either from PALU_DQ pins or from Pixel Buffer 8-bit operand ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Dual Compare Unit A functional block diagram of the Dual Compare units is shown in Figure 3.13. Both Match Compare and Magnitude Compare are performed in parallel. The Match Mask and Magnitude Mask define which bits of the 32-bit word will be compared and which will be “don’t care.” One of the sources is always the Old Data (“ ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Pipelining The 3D-RAM Pixel ALU pipeline is designed so that the rendering controller can issue read and Table 3.12 Pixel ALU and Pixel Buffer operation pipeline Stage External Activities 1 Operation specified on PALU_EN, PALU_WE, PALU_OP, PALU_A, and PALU_BE pins 2 Write data on PALU_DQ and PALU_DX ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP The pipeline flow of the ROP/Blend units and the Dual Compare units of the Pixel ALU and the Pixel Buffer is illustrated in Figure 3.15 helpful to point out that the dotted lines show the boundaries of the pipeline stages and the numbers in the square boxes indicate the pipeline stages ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 2 PALU_DQ Figure 3.15 Pixel ALU and Pixel Buffer block diagram with pipeline flow 3D-RAM (M5M410092B) 6 PASS_IN 6 PASS_OUT Compare Unit Enables ROP/Blend Units Write Data 3 2 Read Data PALU_BE 54 Rev. 1. Write Addr 7 Pixel ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP The Picking Logic The block diagram of the Picking Logic is shown again in Figure 3.16. At the beginning, the Picking Logic should be enabled and the HIT flag should be cleared. This is done either by asserting the RESET pin low or by writing the data Eh into byte 3 of the Compare Control register helpful to note that writing “ ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Operations of the Pixel ALU All operations that involve the Pixel ALU and the Pixel Buffer but not the DRAM array are collectively referred to as Pixel ALU operations. Table 3.13 summarizes the Pixel ALU operations. There are two categories of Pixel ALU operations: register operations and pixel data operations ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Register Operations There are fourteen registers in the 3D-RAM. Their encoding is shown in Table 3.14. Among these registers, the Identification Register is read-only, and all other registers are write-only. All registers are 32 bits wide except the Constant Source register, which is 36 bits. The write-only ...
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... Figure 3.17. The manufacturer ID is 01Ch for Mitsubishi Electronics. The part number is read as 130Ah for M5M410092B. Bit 0 is always “1”, so for Version 0, this identifi-cation register should be read as 0130 A039h. ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP ROP/Blend Unit 3 ROP/Blend Unit 2 Figure 3.18 ROP/Blend Control register data format ROP/Blend Control Register (RBC This register controls the operations of the four ROP/Blend units. Each ROP/Blend unit is independently controlled by an 8-bit field of this 32-bit register ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Constant Source register bits K selected by bit 8n+5), “OLD” represents the 32-bit data from Pixel Buffer, and “~” means logical inversion. All of these operations are bit-wise logical operations. Table 3.16 Raster operation encoding RBC Raster Operation [8n+3:8n+0] 0000 All bits zero ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP • Bits 17 through 16 select the source for the Dual Compare unit. Bit 16 directly controls the Match Compare source, while the result of Bit 17 XOR Bit 16 controls the Magnitude Compare source. In this way, the first two codes are compatible with the ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP the HIT flag is cleared and the Picking Logic is disabled. During a Stateless Data Write access, the Dual Compare unit behaves as if this register were set to 0000 0000h, regardless of its actual value. Write Address Control Register (WAC Only 1 bit of this register is currently used for the Pixel ALU function ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP •Write into Compare Control Register with 0000 0000h to pass data into the the Pixel Buffer. •Write into Plane Mask Register with FFFF FFFFh to pass every bit into the Pixel Buffer for the Stateful Data Write PALU_DQ ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Unit 3 R=reserved Alpha-Saturate Output Select Figure 3.23 Blend_2 Control register data format Blend_2 Control Register(BLD2 This register provides additional control of the multiplicands and addends for the four Blend units ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP • Bit 8n selects the source for the ADDEND. If this bit is “0”, the data selected by Bit [8n+5] of the ROP/Blend Control Register is used; if this bit is “1”, the OLD is used. This register resets to 0000 0000h. This value causes the ROP/Blend units to operate based on ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP • Bits 8n+3 through 8n+2 select the source for the second multiplicand, MULTP2, for the Preblend Cycle(Table 3.25) Table 3.25 Encoding for MULTP2 Source Selection for Preblend Cycle MULTP2 Source for PBC Preblend Cycle [8n+3:8n+2] 00 OLD [8n+7:8n] 01 ~OLD [8n+7:8n] 1X Data selected by bits [29:28] of this register • ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP comparison functions. A “1” will cause the corresponding bit to be used in the stencil comparison functions. For convenience and clarity, the mnemonic used here corresponds to the OpenGL terminology. Specifically, “StF” refers to the OpenGL command “glStencilFunc” with “MASK” ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 3.26 Stencil Operation for StOP.FAIL StOP.FAIL Stencil Operation [2:0] 000 GL_ZERO 001 GL_KEEP 010 GL_INVERT 011 GL_REPLACE 100 GL_INCR 110 101 GL_DECR 111 • Bits 26 through 24 = StOP.ZFAIL define the stencil operation to be executed in the case of GL_STENCIL_PASS_DEPTH_FAIL. That is, these bits determine which one of the stencil operations listed in Table 3 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 3.28 Stencil Operation for StOP.ZPASS StOP.ZPASS Stencil Operation [2:0] 000 GL_ZERO 001 GL_KEEP 010 GL_INVERT 011 GL_REPLACE 100 GL_INCR 110 101 GL_DECR 111 • Bits 19 = StF.REF_SELECT defines the source of the StF.REF stencil data. Setting this bit to 0 selects the StF.REF from the pins PALU_DQ ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Figure 3.27 PASS_IN Select register data format PASS_INs Select Register (PINS Only 2 bits of this register are currently used for the Pixel ALU function, and the other 30 bits are reserved. • ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Prohibited Register Access Writing to control register address with PALU_A = “011000” and PALU_OP [5:0] “111” for three consecutive rising edges of MCLK MCLK PALU_OP [2:0] PALU_A [5:0] RESET Test_Mode will cause the device to enter into a special test mode and is strictly prohibited in order to avoid unexpected device behavior in the system ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Pixel Data Operations There are six pixel data operations: Stateless Initial Data Write, Stateless Normal Data Write, Stateful Initial Data Write, Stateful Normal Data Write, Replace Dirty Tag, and OR Dirty Tag. Simply put, Stateless Data Writes refer to the ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP The four Dirty Tag bits corresponding to the addressed block and word are inclusive ORed with the PALU_BE value. The other 28 Dirty [3:0] Tag bits corresponding to the addressed block are unchanged. Both the writing to the Pixel Buffer and the ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 3D-RAM (M5M410092B) 74 Rev. 1.03 ...
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DRAM Operations 4 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP DRAM Operations This chapter discusses the 3D-RAM operations involving the DRAM arrays. These include the data transfers between a DRAM bank and the Pixel Buffer and between a DRAM bank and a Video Buffer. An Overview of DRAM Operations Depending on the DRAM_OP code, the DRAM_A ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Description of DRAM Operations Table 4.1 DRAM operation encoding Operation Unmasked Write Block (UWB) Masked Write Block (MWB) Precharge Bank (PRE) Video Transfer (VDX) Duplicate Page (DUP) Read Block (RDB) Access Page (ACP) No Operation (NOP) Table 4.1 lists all of the DRAM operations. One operation can be launched in every cycle ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Unmasked Write Block (UWB) The UWB operation copies 32 bytes from the specified Pixel Buffer block over the Global Bus to the specified block in the sense amplifiers and the DRAM page of a selected DRAM bank. The DRAM_A pins select one of the 40 blocks in a [5:0] DRAM page ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Precharge Bank (PRE) The PRE operation first deactivates the word line corresponding to the most recently accessed DRAM page of a selected DRAM bank and then equalizes the bit lines of the sense amplifiers for a subsequent Access Page operation. After a ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP This paragraph describes the addressing scheme for the Video Transfer operation in detail. A DRAM page has a fixed organization of 10 blocks wide by 4 blocks high. For VDX operation, a 32-byte block is always considered as being 4 rows high (either 32). That is, for VDX operation, a DRAM page is always viewed as containing 16 rows of 80 bytes each ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Video Output Operation There are two byte order formats for the VID_Q video output pins: normal mode and reversed mode. This byte ordering is selected by an internal byte pair mode latch, which is loaded from the DRAM_A7 pin when the DRAM_A8 pin is equal to “ ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Initialize and Abort Video Output When the DRAM_A pin is “1”, the byte pair mode 8 latch is loaded, and the current Video Buffer output operation is aborted. The VID_Q bus is driven starting from the Video Buffer indicated by the DRAM_BS pin ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Duplicate Page (DUP) All 10,240 bits of the data in the sense amplifiers of a selected DRAM bank can be transferred to any specified page in the same bank within one Duplicate Page operation. The data in the sense amplifiers is not affected by this operation. If the ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Figure 4.8 Access Page means transferring a specified page to the sense amplifiers. 3D-RAM (M5M410092B) BANK Page Sense Amp 83 Rev. 1.03 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP No Operation (NOP) The NOP operation may be freely inserted between the ACP operation and the PRE operation on the same bank. NOPs are issued when the DRAM arrays are idle, no read or write is required by the Pixel Buffer, and no Video Buffer 3D-RAM (M5M410092B) load is necessary ...
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Pixel ALU Pipelines and DRAM Activities 5 ...
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...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Pixel ALU Pipelines and DRAM Activities This chapter inculdes some pipeline examples of the interaction between the Global Bus and the Pixel ALU, as well as some typical sequences of DRAM operations on the same bank. For DRAM operations, we assume that the clock cycle time ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 5.2 shows a Read Block operation immediately followed by a Stateful {Initial, Normal} Table 5.2 Read Block on Global Bus to Stateful {Initial, Normal} Data Write on Pixel ALU Cycle DRAM Activities n Read Block op specified on DRAM_EN, DRAM_OP … n+1 Read Block on Global Bus ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 5.3 shows a {Stateless, Stateful} {Initial, Normal} Data Write operation immediately Table 5.3 {Stateless, Stateful} {Initial, Normal} Data Write on Pixel ALU {Masked, Unmasked} Write Block on Global Bus Cycle DRAM Activities n n+1 n+2 n+3 n+4 n+5 n+6 {Masked, Unmasked} Write Block op specified on DRAM_EN, DRAM_OP … ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 5.4 shows a {Replace, OR} Dirty Tag operation immediately followed by a {Masked, Unmasked} Write Block operation. Table 5.4 {Replace, OR} Dirty Tag on Pixel ALU to {Masked, Unmasked} Write Block on Global Bus Cycle DRAM Activities n n+1 n+2 n+3 n+4 n+5 n+6 {Masked, Unmasked} Write Block op specified on DRAM_EN, DRAM_OP… ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 5.5 shows a Write Register operation to the Plane Mask register followed by the latest Masked Table 5.5 Write Register (Plane Mask) on Pixel ALU to Masked Write Block on Global Bus Cycle DRAM Activities n n+1 n+2 n+3 Masked Write Block op specified on DRAM_EN, DRAM_OP … n+4 Masked Write Block on Global Bus ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 5.6 shows a Write Register operation to the Plane Mask register followed by the earliest Table 5.6 Write Register (Plane Mask) on Pixel ALU to Masked Write Block on Global Bus Cycle DRAM Activities n n+1 n+2 n+3 n+4 n+5 n+6 Masked Write Block op specified on DRAM_EN, DRAM_OP … n+7 Masked Write Block on Global Bus ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP DRAM Activities This section discusses consecutive DRAM operations on the same bank. To illustrate interlock timing for DRAM activities, we assume that the clock cycle time equals the minimum specification requirements—10ns or 13ns — depending on the speed grade of the parts. The Table 5 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 5.8 shows minimal length DRAM refresh sequence. Table 5.8 DRAM refresh sequence Cycle External Activities n Access Page specified n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 Precharge Bank specified n+9 n+10 n+11 n+12 3D-RAM (M5M410092B) Internal Activities Access Page Access Page Access Page Access Page Precharge Bank Precharge Bank ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 5.9 shows a sequence of Read Block and {Masked, Unmasked} Write Block operations. Table 5.9 Sequence of Read Block and {Masked, Unmasked} Write Block operations Cycle External Activities n Access Page specified n+1 n+2 n+3 st n+4 1 Read Block specified n+5 nd n+6 2 Read Block specified ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 5.10 shows Duplicate Page sequence. Table 5.10 Duplicate Page sequence Cycle External Activities n Access Page specified n+1 n+2 n+3 n+4 Duplicate Page specified n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 Precharge Bank specified n+13 n+14 n+15 n+16 3D-RAM (M5M410092B) Internal Activities Access Page Access Page Access Page Access Page Duplicate Page ...
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Frame Buffer Organizations 6 ...
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...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Frame Buffer Organizations Introduction There are many ways to use the 3D-RAM to implement frame buffers of various resolutions and depths. This section describes the following frame buffer organizations: • 1280 x 1024 x 8 organization in single chip • 1280 x 1024 x 32, organized as four 1280 x 1024 320 x 1024 x 32 • ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP The Dirty Tag controls the four bytes of 32-bit pixel independently. The following formulas determine which bank, page etc. a given pixel is in, given the x and y coordinates of the pixel. • bank = 2*((y%32)/16) + (x%40)/20 Bank A, 1= Bank Bank C, 1280 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP System Interface Address & Control Rendering Controller 32 32 3D-RAM 3D-RAM Video Control Figure 6.2 1280 x 1024 x 32 Single Buffer 3D-RAM System Pixel Data 32 32 3D-RAM 3D-RAM 16 Video Data 16 Video Data 16 Video Data 16 Video Data 97 Rev. 1.03 3D-RAM (M5M410092B) Monitor ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 320 1024 240 241 247 248 249 255 The screen is 8 page groups wide by 32 page groups high. DRAM_A [5: ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 1280 x 1024 x 32 Double Buffered Organization with Z The basic configuration for a 1280 x 1024 x 32 double buffered organization with Z Buffer is shown in Figure 6.4. This configuration uses only twelve 3D-RAMs. In this example each 3D-RAM (for Buffers A, B, and Z) covers a 320 x 1024 portion of the 1280 x 1024 displayed image ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP System Interface Address & Control Rendering Controller 3D-RAM 3D-RAM Z Buffer Z Buffer 32 3D-RAM 3D-RAM Buffer A Buffer A Buffer B Buffer B Video Control Figure 6.4 1280 x 1024 x 32 double buffered organization with 32-bit Z Buffer 3D-RAM 3D-RAM Z Buffer Z Buffer ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 640 x 512 x 8 Double Buffered Organization With Z A single 3D-RAM chip can be configured to support 640 x 512 x 8 double buffered organization with 16-bit Z. This configuration might be suitable for a very high performance, low cost consumer home or arcade game application. ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 640 512 232 233 239 240 241 255 The screen is 16 page groups wide by 16 page groups high. DRAM_A [5: ...
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Electrical Specifications 7 ...
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...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Electrical Specifications Absolute Maximum Ratings Table 7.1 Absolute Maximum Ratings Symbol Parameter VDD Supply Voltage VI Input Voltage VO Output Voltage IO Output Current Tj Maximum Junction Temperature Topr Operation Temperature Tstg Storage Temperature Testing Conditions The supply voltage VDD and ambient temperature Ta for testing are as follows: VDD = 3 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP HIT Figure 7.2 Output test load for the HIT pin The AC timing measurements are summarized in Figure 7.3 through Figure 7.6. The clock waveform measurements are shown in Figure 7.3. The input and output timing measurements are Clock 0. Clock cycle time (minimum Clock high pulse width (minimum) ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Clock Reset 0.8V Input Reset setup time (minimum Reset pulse width (minimum Input setup time (minimum Input hold time (minimum) 9 Clock 1.5V Output Clock to output low impedance Output access time from clock (maximum) ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP OE (Active High) Output t : Valid output after OE low (minimum Output high impedance Output low impedance Valid output after OE high (maximum) 17 Figure 7.6 Asynchronous output enable timing measurement Clock 1.5V Output Clock to output low impedance Output access time from clock (maximum) ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP DC Specifications Table 7.2 lists the DC characteristics and the operation conditions. Table 7.3 lists the average Table 7.2 DC characteristics Symbol a V Input High Voltage Input Low Voltage IL V (PASS_IN ) PASS_IN IH [1:0] [1:0] V (PASS_IN ) PASS_IN IL [1:0]} [1: Output High Voltage Output Low Voltage, I ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 7.3 Average supply current by function Symbol I Average supply current for ALU operation CC<ALU> min, (1 MCLK cycle) CLK I Average standby current CC<NOP> CLK I Average supply current for DRAM operation ACP CC<ACP> min, (4 MCLK cycles) CLK I Average supply current for DRAM operation PRE CC< ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP AC Specifications Every AC timing parameter is illustrated in at least one of the timing figures in Chapter 8. The “Refer” column in each timing table refers to the exact Table 7.4 Pixel ALU timing parameters Symbol Parameter t Master clock MCLK CLK cycle time t MCLK high pulse ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 7.4 Pixel ALU timing parameters (con’t.) Symbol Parameter t PALU_BE setup BES time t PALU_BE hold BEH time t MCLK to CLZ PALU_DQ low impedance t PALU_DQ access CQ time t PALU_DQ data val- CVD id time t MCLK to CHZ PALU_DQ high im- pedance t PASS_IN setup ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP DRAM Timing Parameters The measurements of the DRAM interlock timings in Tables 7.6 and 7.7 are from the MCLK rising Table 7.5 Minimum requirements of the DRAM timing parameters Symbol Parameter t Refresh interval for array REF t DRAM_EN setup time DENS t DRAM_EN hold time ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 7.6 Minimum requirements of the DRAM interlock timings for operations on same bank Symbol Parameter t Access Page to Block Transfer dABS a t Access Page to Precharge Bank dAPS t Access Page to Duplicate Page dADS t Access Page to Video Transfer dAVS t Block Transfer to Block Transfer ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Symbol Parameter t Access Page to Access Page dAAD t Access Page to Block Transfer dABD t Access Page to Precharge Bank dAPD t Access Page to Duplicate Page dADD t Access Page to Video Transfer dAVD t Block Transfer to Access Page dBAD t Block Transfer to Block Transfer dBBD ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Video Buffer Timing Parameters Table 7.7 Video Buffer timing parameters Symbol Parameter t VID_CLK cycle time VCLK t VID_CLK high pulse width VCLKH t VID_CLK low pulse width VCLKL t VID_CKE setup time VCES t VID_CKE hold time VCEH t VID_Q access time from VID_CLK ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Boundary-Scan Timing Parameters Table 7.8 Boundary-Scan timing parameters Symbol Parameter t SCAN_TCK cycle time SCLK t SCAN_TCK high pulse width SCLKH t SCAN_TCK low pulse width SCLKL t SCAN_TMS setup time SCNTS t SCAN_TMS hold time SCNTH t SCAN_TDI setup time SCNIS t SCAN_TDI hold time ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 3D-RAM (M5M410092B) 116 Rev. 1.03 ...
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Timing Diagrams 8 ...
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...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Timing Diagrams This chapter shows 18 timing diagrams, which are summarized in Table 8.1. These diagrams show the gross timing specifications. Refer to Chapter 7 Table 8.1 Timing diagram figures Figure 8.1 Power on reset 8.2 Restart reset 8.3 DRAM array initialization 8.4 Pixel port read 8.5 Pixel port write 8 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP V DD > 500µs MCLK RESET Internal Stabilize Function internal power supply MCLK t RSP RESET t RSS Internal Function Table 8.2 Reset timing parameters Symbol Parameter t RESET setup time RSS t RESET pulse width RSP > 9 cycles t RSS Reset Initialize Registers DRAM Array Figure 8 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP MCLK ACP DRAM_OP A DRAM_BS Internal Function MCLK ACP PRE DRAM_OP A A DRAM_BS Internal Function ACP ACP ACP Initialize DRAM Array OR ACP PRE ACP PRE Initialize DRAM Array Figure 8.3 DRAM array initialization 119 Rev. 1.03 3D-RAM (M5M410092B) ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP t t CLK MCLK t ENS PALU_EN t OPS PALU_OP t WES PALU_WE t ADS PALU_A t BES PALU_BE n PALU_DQ [8n+7..8n] Note: Refer to Figure 2.6 for an example of combined operations of Pixel ALU read and write. 1 MCLK 2 PALU_EN 111 PALU_OP PALU_WE Register Block:xxx PALU_A PALU_BE n t DQS ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 8.3 Pixel ALU timing parameters Symbol Parameter t Master clock MCLK cycle time CLK t MCLK high pulse width CLKH t MCLK low pulse width CLKL t PALU_EN setup time ENS t PALU_EN hold time ENH t PALU_OP setup time OPS t PALU_OP hold time ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 1 MCLK 2 PALU_EN 111 011 PALU_OP PALU_WE 000101 Block:Word PALU_A PALU_BE [2..0] PALU_BE 3 XEXXXXXX PALU_DQ [31..0] PASS_IN PASS_OUT HIT Note: 1. The HIT signal is cleared by writing to the Compare Control register. 2. The HIT signal can be set by the comparison result from the PASS_IN and PASS_OUT pins, which are generated two cycles before the HIT signal is ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP This page is intentionally left blank. 123 Rev. 1.03 3D-RAM (M5M410092B) ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP t dPAS MCLK t DENS DRAM_EN t t DOPS DOPH PRE NOP DRAM_OP t t DBKS DBKH A DRAM_BS t t DADS DADH PAGE DRAM_A MCLK DRAM_EN PRE NOP DRAM_OP A DRAM_BS PAGE DRAM_A Note: BKX means any block transfer operation, such as UWB, MWB, or RDB. ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 8.5 Minimum requiremens of the DRAM port interface timing parameters Symbol Parameter t DRAM_EN setup time DENS t DRAM_EN hold time DENH t DRAM_OP setup time DOPS t DRAM_OP hold time DOPH t DRAM_BS setup time DBKS t DRAM_BS hold time DBKH t DRAM_A setup time ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP t dAVS MCLK DRAM_EN ACP NOP DRAM_OP A DRAM_BS PAGE DRAM_A MCLK DRAM_EN ACP NOP DRAM_OP A DRAM_BS PAGE DRAM_A Figure 8.9 DRAM operations on the same bank (3) t dVBS MCLK DRAM_EN VDX NOP DRAM_OP DRAM_BS A DRAM_A LINE Note: BKX means any block transfer operation, such as UWB, MWB, or RDB. ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 8.7 Minimum requirements of the DRAM interlock timings for operations on same bank Symbol Parameter t Access Page to Video Transfer dAVS t Block Transfer to Video Transfer dBVS t Precharge Bank to Precharge Bank dPPS t Duplicate Page to Precharge Bank dDPS t Duplicate Page to Video Transfer ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP t dPPD MCLK DRAM_EN PRE PRE DRAM_OP A B DRAM_BS PAGE PAGE DRAM_A MCLK DRAM_EN PRE PRE DRAM_OP A B DRAM_BS PAGE PAGE DRAM_A Note: BKX means any block transfer operation, such as UWB, MWB, or RDB. Figure 8.11 DRAM operations between two different banks (1) ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 8.8 Minimum requirement of the DRAM interlock timings for operations between two different banks Symbol Parameter t Access Page to Access Page dAAD t Access Page to Block Transfer dABD t Access Page to Precharge Bank dAPD t Access Page to Duplicate Page dADD t Block Transfer to Access Page ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP t dDVD MCLK DRAM_EN DUP BKX DRAM_OP A B DRAM_BS PAGE BLOCK DRAM_A Figure 8.13 DRAM operations between two different banks (3) Table 8.9 Minimum requirement of the DRAM interlock timings for operations between two different banks Symbol t Access Page to Video Transfer dAVD ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP This page is intentionally left blank. 131 Rev. 1.03 3D-RAM (M5M410092B) ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP t t VCLKH VCLKL t VCLK 1 VID_CLK t VCES VID_CKE Internal VID_CLK VID_OE Data 1 Data 2 VID_Q t t VQVE VQVC t VQ Note: 1. The deassertion of VID_CKE at the current VID_CLK rising edge will mask out the next internal VID_CLK cycle. 2. Timings are measured from the VID_CLK pin or from the VID_OE pin. ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 8.10 Video Buffer timing parameters Symbol Parameter t VID_CLK cycle time VCLK t VID_CLK high pulse width VCLKH t VID_CLK low pulse width VCLKL t VID_CKE setup time VCES t VID_CKE hold time VCEH t VID_Q access time from VID_CLK VQ t VID_Q valid after VID_CLK ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP VID_QSF VID_Q [ VID_CLK VID_CKE MCLK VDX VDX DRAM_OP 0 1 DRAM_BS 10 0x DRAM_A [ Initial VDX Normal VDX During Retrace During Retrace Note specifies the earliest allowed normal VDX. VXC1 2. t specifies the latest allowed normal VDX. ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP t SCLK t SCLKH SCAN_TCK Controller Test-Logic Reset State t SCNTS Note 1 SCAN_TMS SCAN_TDI SCAN_TDO Table 8.12 Boundary-Scan timing parameters Symbol t SCAN_TCK cycle time SCLK t SCAN_TCK high pulse width SCLKH t SCAN_TCK low pulse width SCLKL t SCAN_TMS setup time SCNTS t SCAN_TMS hold time ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP SCAN_TCK SCAN_RST Table 8.13 Boundary-Scan reset timing parameters Symbol t SCAN_RST setup time SCNRS t SCAN_RST pulse width SCNRP t SCNRP Figure 8.18 Boundary scan reset M5M410092B Parameter -10A, -10, -12 Min 136 Rev. 1.03 3D-RAM (M5M410092B) t SCNRS M1005 Unit Refer Max 8 — — ...
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Packaging 9 ...
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...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Packaging The 3D-RAM is housed in 128-pin QFP(FP) and reverse QFP(RF) packages. For the purpose of convenient reference, the pinout diagrams for the 3D-RAM are repeated on pages 137 and 138. Page 103 contains the mechanical specification for the FP and RF packages. ...
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... Tracking Label On the top surface of the 3D-RAM package, a tracking label is printed below the Mitsubishi logo and the 3D-RAM product number. The tracking label consists of 7 numbers followed by a dash and a speed/power grade designation, and is represented by the mnemonic “DDDMMMMM-nn”. This mnemonic is explained as below: ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Mechanical Drawing for 128-pin FP and RF Packages 128 103 102 SEATING PLANE b SEE DETAIL F Figure 9.1 128-pin FP package drawing 139 Rev. 1.03 3D-RAM (M5M410092B Recommended Mount Pad SEATING ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 103 102 128 SEATING PLANE b SEE DETAIL F Figure 9.2 128-pin RF package drawing 140 Rev. 1.03 3D-RAM (M5M410092B Recommended Mount Pad SEATING L 1 PLANE L DETAIL F M1042 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 9.1 Package drawing parameters in millimeters Description Mounting height Stand-off height Package height Terminal width Terminal thickness Package length Package width Linear spacing between terminals Over length Over width Length of the flat portion of terminal Terminal length Flatness of terminal ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Thermal Characteristics The maximum junction temperature (T 125 C. The junction temperature can be calculated with the following equation C/ ( where is the junction-to-ambient thermal ja resistance the whole chip power dissipation, Table 9.2 Thermal resistance for single package ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 1.0 9.2 1.5 1.5 Figure 9.7 Mechanical drawing of the fin 143 Rev. 1.03 3D-RAM (M5M410092B) 2.0 7.5 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Thermal Resistance for Twelve Packages Mounted on PCB Table 9.3 lists the thermal resistance for 12 packages mounted on two sides of a PCB. Two cases are listed: without heat sink and with aluminum plate for heat sink. Table 9.3 Thermal resistance for 12 packages ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Air Flow Figure 9.10 Mechanical drawing of the mounting, without heat sink 10.16 76.2 145 Rev. 1.03 3D-RAM (M5M410092B) PCB (Glass Epoxy) 1.6 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Air Flow 76.2 Figure 9.11 Mechanical drawing of the mounting, with heat sink 3D-RAM (M5M410092B) Al 10. 1.6 146 Rev. 1.03 Resin 0.6 MAX 2.5 ...
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JTAG Boundary Scan 10 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP JTAG Boundary Scan Boundary-Scan Architecture The 3D-RAM provides test features that are partially in compliance with the IEEE Standard 1149.1 Test Access Port and Boundary-Scan Architecture. The on-chip test logic provides a standardized approach for checking the interconnections between different components on the same printed circuit board ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP The boundary-scan test logic contains the following elements: • Test Access Port (TAP), consisting of input pins SCAN_TMS, SCAN_TCK, SCAN_RST and SCAN_TDI, and an output pin SCAN_TDO • TAP Controller, which interprets the inputs on the test mode select line (SCAN_TMS) ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP The TAP Controller The TAP controller is a synchronous finite state machine controlling the sequence of test logic operations. The TAP controller changes state at the rising edge of the SCAN_TCK pin. The SCAN_TMS pin controls the sequence of the state changes. A state diagram for the TAP ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Test-Logic-Reset State The Instruction Register is set to the default Bypass instruction, so that normal 3D-RAM operations can proceed without interference. The TAP controller enters this state when it is initialized after power- the reset signal SCAN_RST. Regardless of the original state, the ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Shift-IR State The shift-register contained in the Instruction Register is connected between the SCAN_TDI and SCAN_TDO pins. The shift-register shifts data one stage towards its serial output on each rising edge of SCAN_TCK. The test data register selected by the current instruction retains its previous value during this state ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP RESET, B/S PALU_DQ, Cell PALU_DX, PALU_A, PALU_OP, PALU_BE, PALU_EN, DRAM_A, DRAM_BS, DARM_OP, DRAM_EN, VID_CKE B/S VID_OE Cell Figure 10.4 Logical structure of the Boundary-Scan Register 3D-RAM (M5M410092B) 3D-RAM System Logic 152 Rev. 1.03 B/S VID_QSF Cell B/S VID_Q Cell B/S VID_Q Cell B/S HIT Cell M1001 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP The boundary-scan cells inside the Boundary-Scan Register are organized in the following order: SCAN_TDI DRAM_A 3 DRAM_OP 0 PALU_EN 0 PALU_BE 1 PALU_DQ 1 PALU_DQ 5 PALU_DQ 9 PALU_DQ 13 PALU_DQ 17 PALU_DQ 21 PALU_DQ 25 PALU_DQ 29 PALU_DX 3 PALU_WE PALU_A 5 DRAM_A 7 RESET VID_Q 11 VID_Q 15 HIT VID_Q 3 VID_Q 7 Instruction Register ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Table 10.1 Boundary-Scan instruction codes Instruction Code Instruction Name 0000 Extest 0001 Bypass 0010 Bypass 0011 Bypass 0100 Sample/Preload 0101 Bypass 0110 Bypass 0111 Bypass 1000 Bypass 1001 Bypass 1010 Bypass 1011 Bypass 1100 Bypass 1101 Bypass 1110 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP VID_OE Boundary-Scan Cell The VID_OE pin controls the tri-state buffer of the VID_Q bus. Therefore, its boundary-scan cell configuration is different from a normal input pin. The functions performed on this cell for the Sample/Preload and Extest instructions are summarized below. ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 3D-RAM (M5M410092B) 156 Rev. 1.03 ...
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Formal Specification of Operations 11 ...
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...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Formal Specification of Operations This chapter specifies exactly which bits are moved for many types of operations. It uses a Elements bit DA[4][257][10240] bit SA[4][10240] bit RAL[4][9] bit VB[2][640] bit VD[16] bit VC[7] bit VM[1] bit SRAM[8][256] bit DT[8][32] bit PM[32] bit DQ[32] bit BE[4] ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Bit Ordering of Elements Block 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 Page 640 648 656 8960 8968 8976 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Words within a Block Figure 11.2 Orderings of words and blocks in a page Access Page ACCESS PAGE(bit bank[2], bit daddr[9]) { bit i[4]; for < 9; i++) RAL[bank][i] <- daddr[i]; bit j[14]; for(j = 0;j < 10240; j++) SA[bank][j] <- DA[bank][daddr][j]; ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Precharge Bank PRECHARGE(bit bank[2]) {} Read Block READ BLOCK(bit bank[2], bit daddr[9]) { bit i[8]; for < 256; i++) SRAM[daddr[8..6]][i] <- SA[bank][daddr[1..0]*2560 + bit j[5]; for(j = 0;j < 32; j++) DT[daddr[8..6]][j] < Masked Write Block MASKED WRITE BLOCK(bit bank[2], bit daddr[9]) { bit i[8]; for < 256; i++) if(PM[i[4..0]] & ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Unmasked Write Block UNMASKED WRITE BLOCK(bit bank[2], bit daddr[9]) { bit i[8]; for < 256; i++) if(DT[daddr[8..6]][{i[4..3],i[7..5]}]) { SA[bank][daddr[1..0]*2560 + i[7..6]*640 + DA[bank][RAL][daddr[1..0]*2560 + i[7..6]*640 + } } Video Transfer VIDEO TRANSFER(bit bank[2], bit daddr[9]) { bit i[10]; for < 640; i++) VB[bank[0]][i] <- SA[bank][640*daddr[3..0] + i]; ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Video Cycle VIDEO CYCLE(bit enable[1], bit voe[1]) { if(voe) { bit i[4]; for < 16; i++) VD[i] <- VB[VC[6]][{VC[5..1],(VC[0]^VM[0])}*16 + i]; } if(enable) { if(VC[5..0] == 39) { VC[5..0] <- 0; VC[6] <- ~VC[6]; } else { VC[5..0] <- VC[5.. Data Read DATA READ(bit paddr[6]) { bit i[5]; for < 32; i++) if(BE[i[4..3]]) DQ[i] <- SRAM[paddr } 3D-RAM (M5M410092B) [5..3]][paddr[2..0]*32 + i]; 162 Rev. 1.03 ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Stateless Initial Data Write STATELESS INITIAL DATA WRITE(bit paddr[6]) { bit i[5]; for < 32; i++) if(BE[i[4..3]]) SRAM[paddr[5..3]][paddr[2..0]* <- DQ[i]; bit j[5]; for(j = 0;j < 32; j++) if (CDS[ (8,8,8,8) normal mode */ if((paddr[2..0] == j[2..0]) && BE[j[4..3]]) else /* (4,4,4,4) 16-bit color mode */ if(((BE[3] || BE[2 && ((BE[1] || BE[0]) == 1)) else } DT[paddr[5..3]][j] <- 1; else DT[paddr[5..3]][j] < ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP Stateless Normal Data Write STATELESS NORMAL DATA WRITE(bit paddr[6]) { bit i[5]; for < 32; i++) if(BE[i[4..3]]) SRAM[paddr[5..3]][paddr[2..0]* <- DQ[i]; bit j[5]; for < 32; j++) if (CDS[ (8,8,8,8) normal mode */ if((paddr[2..0] == j[2..0]) && BE[j[4..3]]) else /* (4,4,4,4) 16-bit color mode */ if(((BE[3] || BE[2 && ((BE[1] || BE[0]) == 1)) else } Replace Dirty Tag REPLACE DIRTY TAG(bit paddr[6]) { bit i[5] ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP OR Dirty Tag OR DIRTY TAG(bit paddr[6]) { bit i[5]; for < 32; i++) if(BE[i[4..3]] && DQ[i paddr[2..0] + 8*i[4..3]) } Write Plane Mask Register WRITE PLANE MASK REGISTER() { bit i[5]; for < 32; i++) if(BE[i[4..3]]) PM[i] <- DQ[i]; } DT[paddr[5..3]][i] <- DQ[i]; 165 Rev. 1.03 3D-RAM (M5M410092B) ...
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... MITSUBISHI ELECTRONIC DEVICE GROUP 3D-RAM (M5M410092B) 166 Rev. 1.03 ...
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Appendix A 12 ...
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