TE28F640J3C-150

Manufacturer Part NumberTE28F640J3C-150
DescriptionTE28F640J3C-150Intel StrataFlash Memory (J3)
ManufacturerIntel Corporation
TE28F640J3C-150 datasheet
 
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256-Mbit J3 (x8/x16)
9.1.4
Standby
CE0, CE1, and CE2 can disable the device (see
This manipulation of CEx substantially reduces device power consumption. D[15:0] outputs are
placed in a high-impedance state independent of OE#. If deselected during block erase, program, or
lock-bit configuration, the WSM continues functioning, and consuming active power until the
operation completes.
9.1.5
Reset/Power-Down
RP# at V
initiates the reset/power-down mode.
IL
In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and
turns off numerous internal circuits. RP# must be held low for a minimum of t
required after return from reset mode until initial memory access outputs are valid. After this wake-
up interval, normal operation is restored. The CUI is reset to read array mode and Status Register is
set to 0x80.
During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In
default mode, STS transitions low and remains low for a maximum time of t
reset operation is complete. Memory contents being altered are no longer valid; the data may be
partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time
t
is required after RP# goes to logic-high (V
PHWL
As with any automated device, it is important to assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash memory. Automated flash memories provide
status information when accessed during block erase, program, or lock-bit configuration modes. If
a CPU reset occurs with no flash memory reset, proper initialization may not occur because the
flash memory may be providing status information instead of array data. Intel StrataFlash
memory family devices allow proper initialization following a system reset through the use of the
RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system
CPU.
34
Table 13 on page
33) and place it in standby mode.
. Time t
PLPH
+ t
PLPH
) before another command can be written.
IH
is
PHQV
until the
PHRH
®
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