AD9873 Analog Devices, AD9873 Datasheet

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AD9873

Manufacturer Part Number
AD9873
Description
Analog Front End Converter for Set-top Box, Cable Modem, and Other Broadband Communication Applications
Manufacturer
Analog Devices
Datasheet
a
GENERAL DESCRIPTION
The AD9873 integrates a complete 232 MHz quadrature
digital transmitter and a multichannel receiver with four high-
performance analog-to-digital converters (ADC) for various
video and digital data signals. The AD9873 is designed for cable
modem set-top box applications, where cost, size, power dissi-
pation, and dynamic performance are critical attributes. A single
external crystal is used to control all internal conversion and
data processing cycles.
The transmit section of the AD9873 includes a high-speed
direct digital synthesizer (DDS), a high-performance, high-speed
12-bit digital-to-analog converter (DAC), programmable clock
multiplier circuitry, digital filters, and other digital signal
processing functions, to form a complete quadrature digital
up-converter device.
TxDAC+ is a registered trademark of Analog Devices, Inc.
On the receiver side, two 8-bit ADCs are optimized for IQ
demodulated “out-of band” signals. An on-chip 10-bit ADC
is typically used as a direct IF input of 256 QAM modulated
signals in cable modem applications. A second direct IF input
and an auxiliary video input with automatic programmable clamp
function are multiplexed to a high-performance 12-bit video ADC.
The chip’s programmable sigma-delta modulated outputs and
an output clock may be used to control external components
such as programmable gain amplifiers (PGA) and mixer stages.
Three pins provide a direct interface to the AD8321/AD8323
programmable gain amplifier (PGA) cable driver.
The AD9873 is available in a space-saving 100-lead MQFP package.
Analog Front End Converter for
SERIAL ITF
Tx SYNC
PROFILE
Rx SYNC
Tx IQ
Rx IQ
Rx IF
Set-Top Box, Cable Modem
2
4
FUNCTIONAL BLOCK DIAGRAM
PLL
Tx
Rx
CONTROL FUNCTIONS
INTERPOLATOR
FILTER
DDS
10
12
COS
SIN
8
8
SINC
INV
12
12
ADC
ADC
ADC
ADC
12
AD9873
AD9873
DAC
3
MUX
Tx
CA
SDELTA0
SDELTA1
REF CLK
I
Q
IF10
IF12
VIDEO
IN
IN

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AD9873 Summary of contents

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... The AD9873 is designed for cable modem set-top box applications, where cost, size, power dissi- pation, and dynamic performance are critical attributes. A single external crystal is used to control all internal conversion and data processing cycles ...

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... AD9873 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 7 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . 7 EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . 7 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DEFINITIONS OF TERMS . . . . . . . . . . . . . . . . . . . . . . . 8 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 9 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . 10 REGISTER BIT DEFINITIONS . . . . . . . . . . . . . . . . . . . 12 TYPICAL PERFORMANCE CHARACTERISTICS . . . 14 Typical Power Consumption Characteristics . . . . . . . . . 14 Dual Sideband Transmit Spectrum . . . . . . . . . . . . . . . . 14 Single Sideband Transmit Spectrum . . . . . . . . . . . . . . . 15 Typical QAM Transmit Performance Characteristics . . 16 Typical ADC Performance Characteristics ...

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... Full IV Full IV Full Full II AD9873 = 216 MHz MHz SYSCLK MCLK , DAC Load) SET Min Typ Max Unit 232 MHz 3 33 MHz 100 M ...

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... AD9873–SPECIFICATIONS Parameter 8-BIT ADC CHARACTERISTICS (Continued) Dynamic Performance (A = –0 MHz) IN Effective Number of Bits (ENOB) 2 Effective Number of Bits (ENOB) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious Free Dynamic Range (SFDR) Differential Phase Differential Gain 10-BIT ADC CHARACTERISTICS ...

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... IV >80 IV >80 IV >70 N/A 200 N/A 5 III 2.8 4 III 66 III 3 III 3 III 5.2 III 0.2 III 15 III 30 III 30 III 1 III 25 III 0 III 30 AD9873 Unit dB dB Bits Bits Degree LSB LSB LSB MHz dB Bits Degree LSB Cycles MCLK t Cycles ...

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... AD9873–SPECIFICATIONS Parameter CMOS LOGIC INPUTS Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance CMOS LOGIC OUTPUTS (1 mA Load) Logic “1” Voltage Logic “0” Voltage POWER SUPPLY Analog Supply Current I ...

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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9873 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

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... AD9873 DEFINITIONS OF TERMS DIFFERENTIAL NONLINEARITY ERROR (DNL, NO MISSING CODES) An ideal converter exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 10-bit resolution indicates that all 1024 codes respectively, must be present over all operating ranges. ...

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... Noninverting IF10 Analog Input 90 IF10+ Inverting IF10 Analog Input 93 REFB12 Bottom Reference Decoupling IF 12-Bit ADC’s Reference 94 REFT12 Top Reference Decoupling IF 12-Bit ADC’s Reference 97 IF12– Inverting IF12 Analog Input 98 IF12+ Noninverting IF12 Analog Input 100 VIDEO IN Single-Ended Video Input AD9873 ...

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... DRGND DRVDD MLCK DVDD DGND TxSYNC (MSB) TxIQ(5) TxIQ(4) TxIQ(3) TxIQ(2) PIN CONFIGURATION 1 PIN 1 2 IDENTIFIER AD9873 15 TOP VIEW 16 (Pins Down AGND IN IN– 77 AGND IQ 76 ...

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... Version <3:0> Profile 0 Bypass Spectral Select <0> Inv. Sinc Inversion Tx Tx Mode Tx Filter AD9873 Default Bit 0 (Hex) Type OSC Multiplier M <0> MCLK 09 rw Divider R <0> rw 8-Bit ADC ADC ...

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... This register stores the die version of the chip. It can only be read. 0Fh, Bit 0: Single-Tone Tx Mode Active high configures the AD9873 for single-tone applications. The AD9873 will supply a single frequency output as determined by the frequency tuning word (FTW) selected by the active profile. In this mode, the Tx IQ input data pins are ignored but should be tied high or low ...

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... AD832x-family of gain programmable cable driver amplifier. This allows direct control of the cable driver’s gain via the AD9873. New data is automatically sent to the cable driver amplifier whenever a new burst profile with different gain setting becomes active or when the gain contents of an active AD8321/ AD8323 gain control register changes ...

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... AD9873 Typical Performance Characteristics [ 4], ADC Sample Rate derived directly from f TYPICAL POWER CONSUMPTION CHARACTERISTICS (20 MHz Single Tone, unless otherwise noted) 380 360 340 320 300 280 260 240 220 200 120 140 160 180 f – MHz SYSCLK DUAL SIDEBAND TRANSMIT SPECTRUM (See Table IV for Dual-Tone Generation.) 0 – ...

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... AD9873 100 FREQUENCY – MHz 100 FREQUENCY – MHz 100 FREQUENCY – MHz ...

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... AD9873 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 FREQUENCY OFFSET – MHz 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –50 –40 –30 –20 – FREQUENCY OFFSET – kHz TYPICAL QAM TRANSMIT PERFORMANCE CHARACTERISTICS (16-QAM, 2 ...

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... AD9873 ...

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... AD9873 TYPICAL ADC PERFORMANCE CHARACTERISTICS (ADC Sample Rate derived directly from f 27 MHz [13.5 MSPS for 8-bit ADCs], Single-Tone 5 MHz Input Signal, unless otherwise noted.) 70 12-BIT ADC 65 10-BIT ADC 8-BIT ADC INPUT SIGNAL FREQUENCY – MHz 70 12-BIT ADC ...

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... AD9873 13.5 FREQUENCY – MHz 13.5 FREQUENCY – MHz 13.5 FREQUENCY – MHz ...

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... AD9873 THEORY OF OPERATION To gain a general understanding of the AD9873 it is helpful to refer to Figure 1, which displays a block diagram of the device DATA ASSEMBLER HALF-BAND FILTER # SYNC MCLK IQCLK MCLK REF CLK 3 AD832x CTRL 2 BURST PROFILE CTRL 4 SERIAL INTERFACE ...

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... The AD9873 provides for a 24-bit frequency tuning word, which results in a tuning resolution of 12 216 MHz. A good rule of thumb when using the AD9873 as a frequency synthesizer is to limit the fundamental output frequency to 30 ...

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... MCLK, sampling frequency. CLOCK AND OSCILLATOR CIRCUITRY The AD9873’s internal oscillator generates all sampling clocks from a simple, low-cost, series resonance, fundamental frequency quartz crystal. Figure 2 shows how the quartz crystal is connected between OSC IN (Pin 61) and XTAL (Pin 60) with parallel resonant load capacitors as specified by the crystal manufacturer ...

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... AD9873. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9873 and the system controller. Phase 2 of the communication cycle is a transfer data bytes as determined by the instruction byte ...

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... Bit 6. The default is MSB first. When this bit is set active high, the AD9873 serial port is in LSB first format. That is, if the AD9873 is in LSB first mode, the instruction byte must be written from least significant bit to most significant bit. Multibyte data transfers in MSB format can be completed by writing an instruction byte that includes the register address of the most significant byte ...

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... Thus, in order to keep the bandwidth of the data in the flat portion of the filter passband, the user must oversample the baseband data by at least a factor of two prior to presenting it to the AD9873. Note that without oversampling, the Nyquist bandwidth of the baseband data corresponds to the f of the data bandwidth will suffer more of attenuation due to the frequency response of the digital filters ...

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... AD9873 If a particular application requires an value between 0.45 and 1, the user must oversample the baseband data by at least a factor of four –10 –20 –30 –40 –50 –60 –70 –80 0 0.1 0.2 0.3 0.4 0.5 0.6 FREQUENCY – FS –10 –20 –30 –40 –50 –60 –70 –80 0 0.1 0.2 0.3 0.4 0.5 0.6 FREQUENCY – FS/2 ...

Page 27

... ISF responses). It should be mentioned at this point that the ISF exhibits an insertion loss of 1.4 dB. Thus, signal levels at the output of the AD9873 with the ISF bypassed are 1.4 dB higher than with the ISF engaged. However, for modulated output signals, which have a relatively wide bandwidth, the ben- efits of the SINC compensation usually outweighed the 1 ...

Page 28

... Tx Throughput and Latency Data inputs effect the output fairly quickly but remain effective due to AD9873’s filter characteristics. Data transmit latency through the AD9873 is easiest to describe in terms of f clock cycles ( first seen after an input value change. Latency of I/Q data entering the data assembler (AD9873 input) to the DAC output is 119 f cycles) ...

Page 29

... AD9873. The output compliance voltage of the AD9873 is –0 +1.5 V. Any signal developed at the DAC output should not exceed +1.5 V, otherwise, signal distortion will result. Furthermore, the signal may extend below ground as much as 0.5 V without damage or signal distortion. ...

Page 30

... They saturate to full scale or zero when the input signal exceeds the input voltage range. Receive Timing The AD9873 sends multiplexed data to the Rx IQ and IF out- puts on every rising edge of MCLK. Rx SYNC frames the start of each Rx IQ data Symbol. Both 8-bit ADCs transfer their data within four MCLK cycles using 4-bit data packages (I MSB, I LSB, Q MSB and Q LSB) ...

Page 31

... Analog Devices’ latest amplifier product offerings. ADC Differential Inputs The AD9873 uses 1 V p-p input span for the 8-bit ADC inputs and 2 V p-p for the 10- and 12-bit ADCs. Since not all applica- tions have a signal preconditioned for differential operation, there is often a need to perform a single-ended-to-differential conver- sion ...

Page 32

... IQ-ADC signal path. One com- mon ground underneath the chip connects all ground splits and assures short distances for ground pin connections. Figure 24 AGND 0.1 F 0 0.1 F AD9873 MQFP TOP VIEW 10 F 0.1 F (Pins Down 0 ...

Page 33

... The AD9873- evaluation board for the AD9873 analog front end converter. Careful attention to layout and circuit design allow the user to easily and effectively evaluate the AD9873 in any application where high-resolution, and high-speed conversion is required. This board allows the user flexibility to operate the AD9873 in various configurations ...

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... MAX 0.742 (18.85) TYP 80 81 0.486 TOP VIEW (12.35) (PINS DOWN) TYP PIN 1 100 1 0.029 (0.73) 0.015 (0.35) 0.009 (0.25) 0.023 (0.57) SEATING 0.041 (1.03) 0.004 PLANE (0.10) 0.031 (0.78) MAX CONTROLLING DIMENSIONS ARE IN MILLIMETERS AD9873 51 50 0.555 (14.10) 0.551 (14.00) 0.547 (13.90) 0.685 (17.4) 0.669 (17. 0.110 (2.80) 0.102 (2.60) 0.010 (0.25) MIN ...

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