AM79C985JC Advanced Micro Devices, AM79C985JC Datasheet
AM79C985JC
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AM79C985JC Summary of contents
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... This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice ...
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BLOCK DIAGRAM . Am79C985 20651B-1 ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am79C985 J Valid Combinations Am79C985 JC, KC ...
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RELATED PRODUCTS Part No. Am7990 Local Area Network Controller for Ethernet (LANCE) Am7992B Serial Interface Adapter (SIA) Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE) Am79C98 Twisted Pair Ethernet Transceiver (TPEX) Am79C100 Twisted Pair Ethernet ...
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TABLE OF CONTENTS DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AUI Port Interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CONNECTION DIAGRAMS (PL 084 REXT 12 13 AVSS DI+ 14 DI– 15 VDD 16 17 CI+ CI– 18 AVSS 19 DO DO– AMODE 22 23 STR DVSS 24 CRS_I 25 SI_D 26 27 VDD RST 28 ...
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CONNECTION DIAGRAMS (PQR100) RXD3– REXT 5 AVSS 6 DI+ 7 DI– 8 VDD 9 CI+ 10 CI– 11 AVSS 12 DO+ 13 DO– 14 AMODE 15 STR 16 DVSS 17 CRS_I 18 SI_D ...
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LOGIC SYMBOL Expansion Port Test and Management Port LOGIC DIAGRAM LED Port Control Port Twisted Pair Port DAT TXD+ JAM TXD– ACK RXD+ COL RXD– SELO ...
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PIN DESIGNATIONS (PL 084) Listed by Pin Number Pin No. Pin Name Pin No. 1 TXD3+ 2 TXD3- 3 VDD 4 RXD0+ 5 RXD0- 6 RXD1+ 7 RXD1- 8 RXD2+ 9 RXD2- 10 RXD3+ 11 RXD3- 12 REXT 13 AVSS ...
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PIN DESIGNATIONS (PQR100) Listed by Pin Number Pin No. Pin Name Pin No. 1 RXD3 REXT 6 AVSS 7 DI+ 8 DI- 9 VDD 10 CI+ 11 CI- 12 AVSS 13 DO+ 14 ...
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PIN DESCRIPTION AUI Port DI+, DI– Data In Differential Input DI are differential, Manchester receiver pins. The signals comply with IEEE 802.3, Section 7. DO+, DO– Data Out Differential Output DO are differential, Manchester output driver pins. The signals comply ...
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COL is an I/O and must be pulled to VDD via a minimum equivalent resistance eIMR+ device expansion port is configured for IMR+ mode, COL is an input driven by an external arbiter. Management Port AMODE ...
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LED Interface LDA , LDB 0-4 0-4 LED Drivers Output, Open Drain LDA and LDB drive LED Bank A and LED Bank B, 0-4 0-4 respectively. LDA and LDB indicate the status of the 0 0 AUI port; LDA and ...
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FUNCTIONAL DESCRIPTION The Am79C985 eIMR+ device is a single-chip imple- mentation of an IEEE 802.3/Ethernet repeater (or hub offered with four integral 10BASE-T ports plus one RAUI port comprising the basic repeater. The eIMR+ device is also expandable, ...
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Once a network port is partitioned, the eIMR+ device will reconnect that port, according to the selected re- connection algorithm, as follows: 1. Standard reconnection algorithm—A data packet longer ...
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Connection to Alternate Media The eIMR+ device can be connected to the AUI port of any MAU device. Thus, it can support 10BASE-2, 10BASE-5, and 10BASE-FL. To connect to an alternate media type, on-chip filtering should be disabled. This can ...
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Table 2. LED Attribute-Monitoring Program Options LED Control Global LEDs LDC LDC LDC LDGA CRS CRS CRS 260-ms blk ...
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Network Activity Display The eIMR+ status port can drive up to eight LEDs to in- dicate the network-utilization level as a percentage of bandwidth. The status port uses eight dedicated out- puts (ACT ) to drive a series of LEDs. ...
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Expansion Bus Interface The eIMR+ device expansion bus allows multiple eIMR+ devices to be interconnected. The expansion bus supports two modes of operation: internal arbitration mode and IMR+ mode. The internal arbitration mode uses a modified daisy-chain scheme to eliminate ...
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SELI_0 SELO SELI_1 SELI_0 SELO SELI_1 SELI_0 SELO SELI_1 SELI_0 SELO SELI_1 Figure 5. Internal Arbitration—eIMR+ Devices in Cascade Management Functions The eIMR+ device receives management commands in the form of byte-length data on the serial input ...
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Interconnection The eIMR+ device interfaces directly to the HIMIB de- vice for full repeater manageability. To this end, the eIMR+ device has a management port and a serial out- put that allows the HIMIB device to monitor port activity. ...
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When two eIMR+ devices are connected to one HIMIB device, the secondary device transmits the status of its TP ports, then transmits the status of the primary eIMR+ TP ports and AUI port (CRS and CI). Note that the sec- ...
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Secondary One eIMR+ Device * Shows actual output stream to secondary device. Figure 8. Port Activity Signals with Am79C987 HIMIB Device Management Commands The following section details the operation of each management commands available in the eIMR+ de- vice. In ...
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Table 6. Management Port Command Summary Commands Set (Write Commands) eIMR+ Chip Programmable Options Alternate AUI Partitioning Algorithm Alternate TP Partitioning Algorithm Primary AUI Port Disable Secondary AUI Port Disable Primary AUI Port Enable Secondary AUI Port Enable TP Port ...
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SET (Write Commands) Chip Programmable Options SI Data 0000 1CSA SO Data (Pri) None SO Data (Sec) None The eIMR+ chip programmable options can be enabled (or disabled) by setting (or resetting) one or more of the C, S, and ...
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TP Port Disable SI Data 0010 0### SO Data (Pri) None SO Data (Sec) None This command disables the TP port designated by the three least-significant bits of the command byte. Sub- sequently the eIMR+ chip will ignore all inputs ...
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Enable Automatic Receiver Polarity Reversal (Per TP Port) SI Data 0111 0### SO Data (Pri) None SO Data (Sec) None This command enables the Automatic Receiver Polarity Reversal function for the TP port designated by the three least-significant bits in ...
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Enable Software Override of Bank-B LEDs (Per Port - AUI and TP, Global) SI Data 1100 #### SO Data (Pri) None SO Data (Sec) None This command forces the LEDs in Bank B to blink. In- dividual LEDs and combinations ...
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TP Port Partitioning Status SI Data 1000 0000 SO Data (Sec) 0000 P3..P0, P7..P0 (output to HIMIB) SO Data (Pri) 0000 P7..P4 SO Data (Single) 0000 P3.. Port Partitioned port ...
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SYSTEMS APPLICATIONS eIMR Port Connection The eIMR+ device provides a system solution to designing non-managed multiport repeaters. The eIMR+ device connects directly to AC coupling mod- ules for a 10BASE-T hub. Figure 9 shows the simpli- fied connection. ...
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RXD+ 100 RXD– MAC Interface The eIMR+ device can be connected directly to a MAC through the AUI port. This requires that the AUI port be configured in the reverse mode and connected as shown in Figure 12a. Notice that ...
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V DD (Note multiple eIMR+ system, the reset signal must be synchronized to CLK.) 74LS74 RST MHz OSC Figure 13. eIMR+ Internal Arbitration Mode Connection eIMR+ SELI_0 ...
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Visual Status Display LDA/B[4:0] and LDGA/B provide visual status indicators for the eIMR+. LDA/B[4:0] displays Link, Carrier Sense, Collision, and Partition information for the TP and AUI ports. LDGA/B display global Carrier Sense, Collision, and Jabber information multiple ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . – +150 C Ambient Temperature Under Bias . . . . +70 C Supply Voltage referenced ...
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DC CHARACTERISTICS (continued) Parameter Symbol Parameter Description Twisted Pair Ports (Continued) RXD Positive Squelch Threshold V TSQ+ (peak) RXD Negative Squelch Threshold V TSQ– (peak) RXD Post-Squelch Positive V THS+ Threshold (peak) RXD Post-Squelch Negative V THS– Threshold (peak) RXD ...
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SWITCHING CHARACTERISTICS Parameter Symbol Parameter Description Clock and Reset Timing t CLK Clock Period CLK t CLK Clock High CLKH t CLK Clock Low CLKL t CLK Rise Time CLKR t CLK Fall Time CLKF t Reset Pulse Width after ...
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SWITCHING CHARACTERISTICS (continued) Parameter Symbol Parameter Description Twisted Pair Port Timing t CLK Rising Edge to TXD Transition Delay TXTD t Transmit End of Transmission TETD RXD Pulse Width Maintain/Turn-off t PWKRD Threshold t Idle Signal Period PERLP t Idle ...
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KEY TO SWITCHING WAVEFORMS WAVEFORM SWITCHING WAVEFORMS CLK INPUTS OUTPUTS Must be Will be Steady Steady May Will be Change Changing from from H to ...
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SWITCHING WAVEFORMS (continued) SCLK SI/SI_D SO CLK RST TCLK Note: TCLK represents internal eIMR+ timing AMODE, SELI[0], SI_D, CRS_I RST SCLK t t SCLKH SCLKL t t ...
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SWITCHING WAVEFORMS (continued) CLK TCLK SELO ACK COL DAT/JAM Note: TCLK represents internal eIMR+ timing CLK TCLK SELO ACK COL DAT/JAM Note: TCLK represents internal eIMR+ timing DJSET ...
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SWITCHING WAVEFORMS (continued) CLK TCLK SELO ACK COL IN DAT/JAM Note: TCLK represents internal eIMR+ timing Figure 22. Expansion Bus Collision Timing CLK D0+ D0- t PWKDI (t PWKCI DI+ ( ASQ t PWODI (t ) PWOCI 42 ...
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SWITCHING WAVEFORMS (continued CLK t TXTD TXD+ TXD– Figure 25. TP Ports Output Timing Diagram t PWLP V TSQ+ RXD+/– V TSQ– t PWKRD ...
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SWITCHING TEST CIRCUIT Pin Test Point V SS Figure 28. Switching Test Circuit Am79C985 20651B-33 20650A-32 ...
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PHYSICAL DIMENSIONS PL 084 84-Pin Plastic Leaded Chip Carrier (measured in inches) 1.185 1.195 1.150 1.156 Pin 1 I.D. 1.185 1.195 1.150 1.156 .026 .050 REF .032 TOP VIEW ...
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PQR100 100-Pin Plastic Quad Flat Pack Pin 100 12.35 REF Pin 1 I.D. Pin 30 2.70 2.90 0.25 MIN 17.00 17.40 13.90 14.10 18.85 REF Pin 50 0.65 ...
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Appendix A Security EAVESDROP PROTECTION The eIMR+/HIMIB devices are capable of providing network eavesdrop protection. This feature is protected by a software key. An application note containing the necessary software key and implementation details is available from AMD. A brief ...
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... Hardware Implemented Management Information Base (HIMIB), Integrated Multiport Repeater (IMR) Integrated Multiport Repeater Plus (IMR+), Basic Integrated Multiport Repeater (bIMR), and enhanced Multiport Repeater Plus (eIMR+) are trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...