KM416V4104BS-5 Samsung, KM416V4104BS-5 Datasheet

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KM416V4104BS-5

Manufacturer Part Number
KM416V4104BS-5
Description
4M x 16bit CMOS dynamic RAM with extended data out, 3.3V power supply, 50ns
Manufacturer
Samsung
Datasheet
KM416V4004B, KM416V4104B
This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), power consumption(Normal
or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh
capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated using Sam-
sung s advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Part Identification
• Active Power Dissipation
• Refresh Cycles
* Access mode & RAS only refresh mode
• Performance Range
KM416V4004B*
KM416V4104B
Speed
CAS-before-RAS & Hidden refresh mode
- KM416V4004B/B-L(3.3V, 8K Ref.)
- KM416V4104B/B-L(3.3V, 4K Ref.)
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
-45
-5
-6
Speed
-45
-5
-6
Part
NO.
50ns
50ns
60ns
t
RAC
Refresh
cycle
8K
4K
12ns
13ns
15ns
4M x 16bit CMOS Dynamic RAM with Extended Data Out
t
360
324
288
8K
CAC
Normal
64ms
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
104ns
74ns
84ns
Refresh time
t
RC
Unit : mW
468
432
396
4K
128ms
L-ver
17ns
20ns
25ns
t
HPC
DESCRIPTION
(A0~A11)*1
(A0~A9)*1
UCAS
LCAS
A0~A12
RAS
A0~A8
W
FUNCTIONAL BLOCK DIAGRAM
• Extended Data Out Mode operation
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• Self-refresh capability (L-ver only)
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic TSOP(II) packages
• +3.3V 0.3V power supply
Note) *1 : 4K Refresh
Control
Clocks
Row Address Buffer
Col. Address Buffer
Refresh Counter
Refresh Control
Refresh Timer
VBB Generator
Column Decoder
4,194,304 x 16
Memory Array
Row Decoder
Cells
CMOS DRAM
Vcc
Vss
Data out
Data out
Data in
Data in
Lower
Buffer
Lower
Buffer
Upper
Buffer
Upper
Buffer
OE
DQ15
DQ0
DQ7
DQ8
to
to

Related parts for KM416V4104BS-5

KM416V4104BS-5 Summary of contents

Page 1

... SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. DESCRIPTION • Extended Data Out Mode operation • 2 CAS Byte/Word Read/Write operation • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability • Fast parallel test mode capability • ...

Page 2

KM416V4004B, KM416V4104B PIN CONFIGURATION (Top Views) •KM416V40(1)04BS ¡Û DQ0 3 48 DQ1 4 47 DQ2 5 46 DQ3 DQ4 8 43 DQ5 9 42 DQ6 10 41 DQ7 ...

Page 3

KM416V4004B, KM416V4104B ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Voltage on V supply relative Storage Temperature Power Dissipation Short Circuit Output Current * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" ...

Page 4

KM416V4004B, KM416V4104B DC AND OPERATING CHARACTERISTICS Symbol Power I Don t care CC1 Normal I Don t care CC2 L I Don t care CC3 I Don t care CC4 Normal I Don t care CC5 L I Don t ...

Page 5

KM416V4004B, KM416V4104B CAPACITANCE (T = Parameter Input capacitance [A0 ~ A12] Input capacitance [RAS, UCAS, LCAS, W, OE] Output capacitance [DQ0 - DQ15] AC CHARACTERISTICS ( Test condition : V =3.3V 0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V CC ...

Page 6

KM416V4004B, KM416V4104B AC CHARACTERISTICS (Continued) Parameter Data hold time Refresh period (Normal) Refresh period (L-ver) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS set-up time (CAS -before-RAS ...

Page 7

KM416V4004B, KM416V4104B TEST MODE CYCLE Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time ...

Page 8

KM416V4004B, KM416V4104B NOTES An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles 1. before proper device operation is achieved. V (min) and V (max) are reference levels for measuring timing ...

Page 9

KM416V4004B, KM416V4104B t is specified from W falling edge to the earlier CAS rising edge. 16. CWL t 17. is referenced to the earlier CAS falling edge before RAS transition low. CSR 18 referenced to the later CAS ...

Page 10

KM416V4004B, KM416V4104B WORD READ CYCLE RAS UCAS LCAS ASR ADDRESS ...

Page 11

KM416V4004B, KM416V4104B LOWER BYTE READ CYCLE NOTE : D = OPEN RAS UCAS LCAS ASR ...

Page 12

KM416V4004B, KM416V4104B UPPER BYTE READ CYCLE NOTE : D = OPEN RAS CRP UCAS CRP LCAS ASR V ...

Page 13

KM416V4004B, KM416V4104B WORD WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS UCAS LCAS ASR ...

Page 14

KM416V4004B, KM416V4104B LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP LCAS V - ...

Page 15

KM416V4004B, KM416V4104B UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP LCAS V - ...

Page 16

KM416V4004B, KM416V4104B WORD WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP LCAS V - ...

Page 17

KM416V4004B, KM416V4104B LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D = OPEN OUT RAS UCAS LCAS ...

Page 18

KM416V4004B, KM416V4104B UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP LCAS V ...

Page 19

KM416V4004B, KM416V4104B WORD READ - MODIFY - WRITE CYCLE RAS CRP UCAS CRP LCAS ASR ROW ...

Page 20

KM416V4004B, KM416V4104B LOWER-BYTE READ - MODIFY - WRITE CYCLE RAS CRP UCAS CRP LCAS ASR ROW ...

Page 21

KM416V4004B, KM416V4104B UPPER-BYTE READ - MODIFY - WRITE CYCLE RAS CRP UCAS CRP LCAS ASR ROW ...

Page 22

KM416V4004B, KM416V4104B HYPER PAGE MODE WORD READ CYCLE RAS CRP UCAS CRP LCAS ASR RAH ...

Page 23

KM416V4004B, KM416V4104B HYPER PAGE MODE LOWER BYTE READ CYCLE RAS CRP UCAS LCAS ASR RAH ROW ...

Page 24

KM416V4004B, KM416V4104B HYPER PAGE MODE UPPER BYTE READ CYCLE RAS CRP UCAS CRP LCAS ASR ...

Page 25

KM416V4004B, KM416V4104B HYPER PAGE MODE WORD WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP LCAS ...

Page 26

KM416V4004B, KM416V4104B HYPER PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP ...

Page 27

KM416V4004B, KM416V4104B HYPER PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP ...

Page 28

KM416V4004B, KM416V4104B HYPER PAGE MODE WORD READ - MODIFY - WRITE CYCLE RAS CRP UCAS CRP LCAS RAD t ...

Page 29

KM416V4004B, KM416V4104B HYPER PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE RAS CRP UCAS CRP LCAS RAD ...

Page 30

KM416V4004B, KM416V4104B HYPER PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE RAS CRP UCAS CRP LCAS RAD ...

Page 31

KM416V4004B, KM416V4104B HYPER PAGE READ AND WRITE MIXED CYCLE RAS UCAS LCAS t RAD RAH t ASR ...

Page 32

KM416V4004B, KM416V4104B RAS - ONLY REFRESH CYCLE NOTE : Don t care OPEN OUT RAS CRP UCAS CRP ...

Page 33

KM416V4004B, KM416V4104B HIDDEN REFRESH CYCLE ( READ ) RAS CRP UCAS CRP LCAS ASR ADDRESS ...

Page 34

KM416V4004B, KM416V4104B HIDDEN REFRESH CYCLE ( WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP LCAS ...

Page 35

KM416V4004B, KM416V4104B CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : Don t care RAS UCAS LCAS V - ...

Page 36

KM416V4004B, KM416V4104B PACKAGE DIMENSION 50 TSOP(II) 400mil 0.034 (0.875) 0.841 (21.35) MAX 0.821 (20.85) 0.829 (21.05) 0.0315 (0.80) 0.002 (0.05) MIN 0.010 (0.25) 0.018 (0.45) CMOS DRAM Units : Inches (millimeters) 0.004 (0.10) 0.010 (0.25) 0.047 (1.20) 0.010 (0.25) MAX ...

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