ST16C2552CJ Exar Corporation, ST16C2552CJ Datasheet
ST16C2552CJ
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ST16C2552CJ Summary of contents
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SEPTEMBER 2003 GENERAL DESCRIPTION The ST16C2552 (2552) is asynchronous receiver and transmitter (UART). The ST16C2552 is an improved version of the PC16552 UART. The 2552 provides enhanced UART functions with 16 byte FIFOs, a modem control interface, and data rates ...
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... XTAL1 11 12 GND XTAL2 CHSEL 17 INTB ORDERING INFORMATION ART UMBER ACKAGE ST16C2552CJ 44-Lead PLCC ST16C2552IJ 44-Lead PLCC ST16C2552 34 44-pin PLCC PERATING EMPERATURE ANGE 0°C to +70°C -40°C to +85°C 2 á ...
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REV. 4.2 PIN DESCRIPTIONS Pin Description 44-PLCC N T AME YPE DATA BUS INTERFACE Address data lines [2:0]. These 3 address lines select one of the internal registers in UART ...
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ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO Pin Description 44-PLCC N T AME YPE MFA Multi-Function Output Channel A. This output pin can function as the OP2A#, BAUD- OUTA#, or RXRDYA# pin. One ...
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REV. 4.2 Pin Description 44-PLCC N T AME YPE RIA UART channel A Ring-Indicator (active low) or general purpose input. This input should be connected to VCC when not used. This ...
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ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO 1.0 PRODUCT DESCRIPTION The 2552 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial ...
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REV. 4.2 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The 2552 data interface supports ...
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ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO 2.4 Channel A and B Internal Registers Each UART channel in the 2552 has a set of enhanced registers for controlling, monitoring and data loading and unloading. The configuration register set ...
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REV. 4.2 2.7 INTA and INTB Ouputs The INTA and INTB interrupt outputs change according to the operating mode and enahnced features setup. Tables 3 and 4 summarize the operating behavior for the transmitter and receiver. ...
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ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO 2.9 Programmable Baud Rate Generator A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel control. The programmable Baud Rate Generator is capable of operating ...
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REV. 4.2 Table 5 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling rate. When using a non-standard frequency crystal or external clock, the divisor value can be ...
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ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO IGURE RANSMITTER PERATION IN NON Data Byte 16X Clock Transmit Shift Register (TSR) 2.10.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with ...
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REV. 4.2 reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the ...
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ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO 2.12 Internal Loopback The 2552 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular ...
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REV. 4.2 3.0 UART INTERNAL REGISTERS Each of the UART channel in the 2552 has its own set of configuration registers selected by address lines A0, A1 and A2 with CS# and CHSEL selecting the channel. ...
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ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO . T ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit-7 0 ...
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REV. 4.2 4.3 Baud Rate Generator Divisors (DLL and DLM) - Read/Write The Baud Rate Generator (BRG 16-bit counter that generates the data rate for the transmitter. The rate is programmed through registers DLL ...
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ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO IER[3]: Modem Status Interrupt Enable Logic 0 = Disable the modem status register interrupt (default). Logic 1 = Enable the modem status register interrupt. IER[7:4]: Reserved 4.5 Interrupt Status Register (ISR) ...
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REV. 4.2 ISR[7:6]: FIFO Enable Status These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are enabled. 4.6 FIFO Control Register (FCR) ...
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ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received. BIT LCR[2]: TX and RX Stop-bit Length Select ...
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REV. 4.2 LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. LCR[5] = logic 0, parity is not forced (default). LCR[5] = logic 1 and LCR[4] ...
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ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO MCR[3]: OP2# Output OP2# is available as an output pin on the 2552 when AFR[2:1] = ‘00’. In the Loopback Mode, MCR[3] is used to write the state of the modem ...
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REV. 4.2 LSR[7]: Receive FIFO Data Error Flag Logic FIFO error (default). Logic global indicator for the sum of all error bits in the RX FIFO. At least one parity ...
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ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO 4.12 Baud Rate Generator Registers (DLL and DLM) - Read/Write The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the baud ...
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REV. 4.2 T 11: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS DLL DLM AFR RHR THR IER FCR ISR LCR MCR LSR MSR SPR I/O SIGNALS TX MF# RTS# DTR# TXRDY# INT 2.97V ...
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ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (44-PLCC) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS O U ...
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REV. 4.2 AC ELECTRICAL CHARACTERISTICS TA (-40 + FOR INDUSTRIAL GRADE PACKAGE LOAD WHERE APPLICABLE S YMBOL - Crystal Frequency CLK Clock Pulse Duration ...
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ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO AC ELECTRICAL CHARACTERISTICS TA (-40 + FOR INDUSTRIAL GRADE PACKAGE LOAD WHERE APPLICABLE S P YMBOL N Baud Rate ...
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REV. 4 IGURE ATA US EAD IMING A0-A2 Valid Address T AS CSA#/ CSB# IOR# T RDV D0- IGURE ATA US RITE IMING A0-A2 ...
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ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO F 16 IGURE ECEIVE EADY AND NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY ...
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REV. 4 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX S D0:D7 S D0:D7 Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO IOR# (Reading data out ...
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ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO F 20 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX S D0:D7 (Unloading) IER[1] ISR is read enabled INT* T WRI Data in TX FIFO ...
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REV. 4.2 PACKAGE DIMENSIONS (44 PIN PLCC Note: The control dimension is the millimeter column SYMBOL ...
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ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO 34 áç áç áç áç REV. 4.2 ...
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... September 2003 4.2 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...