NE564 Philips Semiconductors, NE564 Datasheet
NE564
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NE564 Summary of contents
Page 1
... ANALOG OUT 4 13 FREQ. SET CAP 5 12 FREQ. SET CAP 6 11 VCO OUT GND VCO OUT TTL 8 9 TOP VIEW SR01025 Figure 1. Pin Configuration ORDER CODE DWG # NE564D SOT109-1 NE564N SOT38-4 SE564N SOT38-4 14 SCHMITT TRIGGER 16 15 SR01026 853-0908 13720 ...
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... OUT I = 6mA, Pins 16, 9 0.4 OUT 2 Product specification NE/SE564 RATING UNITS 600 +70 C -55 to +125 C -65 to +150 C LIMITS NE564 UNITS MAX MIN TYP MAX 45 60 MHz 1500 o 600 PPM/ C 800 500 6 3 ...
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... Philips Semiconductors Phase-locked loop TYPICAL PERFORMANCE CHARACTERISTICS Lock Range vs Signal Input 1000 PIN 100 0.7 0.8 0.9 NORMALIZED LOCK RANGE Typical Noirmalized VCO Frequency as a Function of Pin 2 Bias Current FREQUENCY: 50MHz 1.01 1.00 0.99 0.98 0.97 0.96 –600 A –400 –200 0 +200 BIAS CURENT ( A), PIN 2 1994 Aug 31 ...
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... Philips Semiconductors Phase-locked loop TYPICAL PERFORMANCE CHARACTERISTICS (Continued) V – PHASE COMPARATOR’S D OUTPUT VOLTAGE IN mV 800 600 800 A BIAS 400 200 40 60 100 –200 –400 –600 –800 Variation of the Comparator’s Output Voltage vs Phase Error and Bias Current (K Figure 4. Typical Performance Characteristics (cont.) ...
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... The use of Schottky clamped transistors and optimized device geometries extends the frequency of operation to greater than 50MHz. In addition to the classical PLL applications, the NE564 can be used as a modulator with a controllable frequency deviation. The output of the PLL can be written as shown in the following ...
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... Philips Semiconductors Phase-locked loop EQUIVALENT SCHEMATIC FM INPUT f = 5MHz 1kHz M BIAS FILTER 1994 Aug 31 Figure 6. Equivalent Schematic LOCK RANGE ADJUSTMENT I 2 0.01 F LOOP FILTER 0. 0. 564 . 0 80pF f = 5MHz O FREQUENCY SET CAP Figure 7. FM Demodulator at 5V ...
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... Modulation Techniques The NE564 phase-locked loop can be modulated at either the loop filter ports (Pins 4 and 5) or the input port (Pin 6) as shown in Figure 9. The approximate modulation frequency can be determined from the frequency conversion gain curve shown in Figure 10 ...
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... V BIAS 0.22 F 0.22 F ADJ +5V 10k 10k 1.2k 2k HYSTERESIS ADJUST 0 0 NE564 3 510 9 12 *510 33pF 11 13 300pF 300pF Figure 10. 10.8MHz FSK Decoder Using the 564 8 Product specification NE/SE564 lines. CC FSK OUTPUT 10 F/8V 0–20pF SR01034 ...
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... Philips Semiconductors Phase-locked loop Figure 11. Phase Comparator (Pins 4 and 5) and FSK (Pin 16) Outputs INPUT SIGNAL *NOTE: Use R only if rise time is critical. 9-11 Figure 12. NE564 Phase-Locked Frequency Multiplier 1994 Aug 31 +5V BIAS ADJUST .47 F 10k CER .47 F CER LOOP ...