W981616AH-6 Winbond, W981616AH-6 Datasheet
W981616AH-6
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W981616AH-6 Summary of contents
Page 1
... Using pipelined architecture and 0.20 W981616AH delivers a data bandwidth 332M bytes per second (-6). For different applications the W981616AH is sorted into the following speed grades: -6, -7, and -8. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length full page when a bank and row is selected by an ACTIVE command ...
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... Ground for input buffers and logic circuit inside DRAM. Power (+3.3V) Separated power from V for I/O buffer improve noise immunity. Ground for I/O Separated ground from V buffer to improve noise immunity. No Connection No connection - 2 - W981616AH DESCRIPTION , and define the operation to CAS WE , used for output buffers used for output buffers SS ...
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... CELL ARRAY D BANK # SENSE AMPLIFIER DATA CONTROL CIRCUIT COLUMN DECODER CELL ARRAY D E BANK # SENSE AMPLIFIER Note: The cell array configuration is 2048 * 256 * 16 Publication Release Date: February 2000 - 3 - W981616AH DQ0 DQ BUFFER DQ15 LDQM UDQM Revision A2 ...
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... Write Commands can also be issued to the same bank or between active banks on every clock cycle. and V Q pins must be ramp up simultaneously to the CC CC supplies. After power up, an initial pause of 200 The maximum time that each bank can be held RRD - 4 - W981616AH has RSC ). RC delay. WE pin voltage RCD ...
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... A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst W981616AH Publication Release Date: February 2000 - 5 - ...
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... W981616AH Burst Length Bust Length ...
Page 7
... Power Down mode longer than the Refresh period (t device. ) has been satisfied. Issue of Auto-Precharge command is RP and t DPL = When using the Auto-precharge Command, the interval DPL W981616AH . The bank DPL are satisfied. This is referred REF Publication Release Date: February 2000 Revision the ...
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... While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one-clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. . The input buffers need (min (min). CES W981616AH ...
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... W981616AH A10 A9-0 CS RAS CAS ...
Page 10
... OPR -55 150 STG T 260 SOLDER OUT SYM. MIN. TYP. V 3.0 3 3 SYM W981616AH UNIT NOTES °C 1 °C 1 ° MAX. UNIT NOTES MIN. MAX. UNIT - 4 pf ...
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... CKE = CC3 CKE = CC3P (Power Down mode min CC4 (t = min CC5 (CKE = 0.2V) I CC6 SYM O( W981616AH - UNIT MAX. MAX. 100 130 110 100 ...
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... 1.5 CKS t 1 CKH t 1.5 CMS t 1 CMH t 64 REF t 12 RSC - 12 - W981616AH -7 -8 MIN. MAX. MIN. MAX 100000 48 100000 1000 10 1000 7 1000 8 1000 5 ...
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... HZ to output level PARAMETER output ohms AC TEST LOAD and W981616AH CONDITIONS 1.4V/1.4V See diagram below 2.4V/0. 1.4V 1 ohms 30pF Publication Release Date: February 2000 Revision A2 ...
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... Command Input Timing V IH CLK RAS CAS WE A0-A10 CKS CKH CKE CMS CMH t t CMS CMH t t CMS CMH t t CMS CMH CKH t CKS CKS - 14 - W981616AH CMH CMS t CKH ...
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... Read Timing CLK CS RAS CAS WE A0-A10 BA DQ Read Command Read CAS Latency Valid Data-Out Burst Length Publication Release Date: February 2000 - 15 - W981616AH Valid Data-Out Revision A2 ...
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... Valid Valid Data-Out Data-Out CKH CKS CKH CKS Valid Data-Out - 16 - W981616AH Valid Valid Data-in Data- Valid Valid Data-in Data- ...
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... Interleave CAS Latency Reserved Reserved Reserved Single Write Mode Burst read and Burst write 0 Burst read and single write 1 Publication Release Date: February 2000 - 17 - W981616AH next Revision A2 ...
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... RAS t t RCD RCD RBb RAc CBx RBb RAc t AC bx1 aw0 aw1 aw2 aw3 bx0 t t RRD Precharge Active Precharge Active Read - 18 - W981616AH RAS RAS t RCD RBd CAy RBd CBz t AC ...
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... RAS t RCD t RCD RAc CBx RAc aw0 aw1 aw2 aw3 bx0 bx1 t RRD AP* Active Read - 19 - W981616AH RAS RAS t RCD RBd RAe CBz CAy RAe RBd ...
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... RAS RAS t RCD RBb RBb CBy ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 t RRD Precharge Active Read - 20 - W981616AH RAS RCD RAc RAc CAz t AC by1 by4 by5 by6 by7 CZ0 ...
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... RAS RP t RCD RBb RBb CBy CAC ax3 ax4 ax0 ax2 ax5 ax6 ax7 ax1 t RRD AP* Read Active * AP is the internal precharge start timing - 21 - W981616AH RAS t t RAS RP t RCD RAc CAz RAc t CAC ...
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... RC RAS t RCD RBb RBb CBy ax4 ax5 ax6 ax7 by0 by1 by2 by3 t RRD Precharge Active Write - 22 - W981616AH RAS RP t RAS t RCD RAc RAc CAz by4 by5 by6 by7 CZ0 CZ1 Active ...
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... RC t RAS t RCD RBb CBy RBb ax4 by2 ax5 ax6 ax7 by0 by1 t RRD AP* Active Write * AP is the internal precharge start timing - 23 - W981616AH RAS t RCD RAb CAz RAb by5 by3 by4 by6 by7 CZ0 Write ...
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... CCD t RAS t RAS CAm CBx CAy bx0 bx1 Ay0 Ay1 Ay2 Read Read Read * AP is the internal precharge start timing - 24 - W981616AH CBz am0 am1 am2 bz0 bz1 bz2 bz3 ...
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... Read Bank # RAS CAy ax5 ay1 ax0 ax1 ax3 ay0 ax2 ax4 Write - 25 - W981616AH ay2 ay4 ay3 Precharge Publication Release Date: February 2000 Revision A2 23 ...
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... Active Read Bank # RCD RAb RAb AC aw0 aw1 aw2 aw3 AP* Active * AP is the internal precharge start timing - 26 - W981616AH RAS CAx t AC bx0 bx1 bx2 Read AP bx3 ...
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... Bank # RCD RAb RAb CAx bx0 aw3 Active Write AP the internal precharge start timing - 27 - W981616AH RAS RP RAc RAc bx1 bx3 bx2 Active AP* Publication Release Date: February 2000 Revision A2 ...
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... AutoRefresh Cycle (CLK = 100 MHz CLK RAS CAS WE BA A10 A0-A9 DQM CKE DQ All Banks Auto Prechage Refresh W981616AH Auto Refresh (Arbitrary Cycle) ...
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... RP RAS CAS WE BA A10 A0-A9 DQM t CKE t CKS DQ All Banks Self Refresh Precharge Entry CKS SB Self Refresh Cycle - 29 - W981616AH CKS Operation Cycle Arbitrary Cycle Publication Release Date: February 2000 Revision A2 23 ...
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... CBv DQM CKE Read Active Bank #0 Bank # CBw CBx CBy av0 av1 av3 aw0 ax0 ay0 av2 Single Write - 30 - W981616AH CBz t AC az1 az2 az3 az0 Read 23 ...
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... When CKE goes high, command input must be No operation at next CLK rising edge CAa t CKS ax0 ax1 ax2 ax3 Precharge Read - 31 - W981616AH RAa RAa CAx CKS NOP Active Precharge Standby Power Down mode ...
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... Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. (min). RAS - 32 - W981616AH Act Act AP Act ...
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... Act Act Act t RP Act represents the start of internal precharging W981616AH Act Act Publication Release Date: February 2000 Revision A2 11 Act ...
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... Write cycle Write Command Note: BST Read Read Read Q0 Q1 Read BST BST BST represents the Burst stop command - 34 - W981616AH ...
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... Commad DQM CAS latency = 3 Write Commad DQM Note: PRCG PRCG PRCG PRCG PRCG represents the Precharge command - 35 - W981616AH Publication Release Date: February 2000 Revision A2 11 ...
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... External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM DQM MASK ( DQM MASK ( CKE MASK ( W981616AH CKE MASK CKE MASK ...
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... External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE W981616AH Open Open Open Publication Release Date: February 2000 Revision A2 ...
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... All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode and Self Refresh mode NOP Command (min (min)+t (min) CKS CK NOP Command Input Buffer Enable (min (min)+t (min) CKS CK Command Input Buffer Enable Represents the No-Operation command Represents one command - 38 - W981616AH (min (min) CKS CK ...
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... E 0.80 e 0.031 0.50 0.60 0.40 0.016 0.020 L 0.80 0.031 0.10 0.88 0.031 W981616AH MAX. 0.047 0.006 0.043 0.018 0.008 0.830 0.405 0.471 0.024 0.004 o 10 Publication Release Date: February 2000 Revision A2 ...
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... TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 - 40 - W981616AH ...