W77E58-40 Winbond, W77E58-40 Datasheet
W77E58-40
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W77E58-40 Summary of contents
Page 1
... ABSOLUTE MAXIMUM RATINGS ................................................................................................................75 DC ELECTRICAL CHARACTERISTICS ......................................................................................................76 AC ELECTRICAL CHARACTERISTICS........................................................................................................77 TYPICAL APPLICATION CIRCUITS .............................................................................................................82 Expanded External Program Memory and Crystal......................................................................................82 Expanded External Data Memory and Oscillator ........................................................................................83 PACKAGE DIMENSIONS..............................................................................................................................83 40-pin DIP...................................................................................................................................................83 44-pin PLCC ...............................................................................................................................................84 44-pin QFP .................................................................................................................................................84 Preliminary W77E58 8 BIT MICROCONTROLLER Publication Release Date: March 1999 - 1 - Revision A1 ...
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... Giving the same throughput with lower clock speed, power consumption has been improved. Consequently, the W77E58 is a fully static CMOS design; it can also be operated at a lower crystal clock. The W77E58 contains 32 KB flash Multiple-Time Programmable(MTP) ROM, and provides operating voltage from 4.5V to 5.5V. All W77E58 types also support on-chip 1 KB SRAM without external memory component and glue logic, saving more I/O pins for users ’ ...
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... INT0, P3.2 PSEN 13 28 P2.7, A15 INT1, P3 P2.6, A14 T0, P3.4 T1, P3 P2.5, A13 WR, P3 P2.4, A12 17 24 P2.3, A11 RD, P3.7 XTAL2 18 23 P2.2, A10 XTAL1 19 22 P2. VSS 21 P2.0, A8 44-Pin QFP (W77E58F P0.4, AD4 INT3, P1.5 39 INT4, P1.6 38 P0.5, AD5 INT5, P1.7 37 P0.6, AD6 36 RST P0 ...
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... RXD1(P1.2): Serial port 2 RXD TXD1(P1.3): Serial port 2 TXD INT2(P1.4): External Interrupt 2 INT3 (P1.5): External Interrupt 3 INT4(P1.6): External Interrupt 4 INT5 (P1.7): External Interrupt 5 I/O P2.0 P2.7 PORT 2: Port bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. Preliminary W77E58 DESCRIPTIONS - 4 - ...
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... RD (P3.7) : External Data Memory Read Strobe I/O PORT 4: Port 4-bit bi-directional I/O port. The P4.0 also provides the P4.0 P4.3 alternate function WAIT which is the wait state control signal. * Note: TYPE I: input, O: output, I/O: bi-directional. DESCRIPTIONS : Timer 0 External Input : Timer 1 External Input - 5 - Preliminary W77E58 Publication Release Date: March 1999 Revision A1 ...
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... Timer 1 2 UARTs Port 3 Port P3.0 Latch 3 P3.7 Port 4 Latch P4.0 Port 4 Oscillator P4.3 XTAL1 XTAL2 Preliminary W77E58 ACC B T1 Register T2 Register Stack PSW Pointer ALU SFR RAM Address Instruction Decoder & Sequencer 256 bytes RAM & SFR 1KB SRAM Bus & lock Controller Reset Block ...
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... I/O Ports: The W77E58 has four 8-bit ports and one extra 4-bit port. Port 0 can be used as an Address/Data bus when external program is running or external memory/device is accessed by MOVC or MOVX instruction. In these cases, it has strong pull-ups and pull-downs, and does not need any external pull- ups ...
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... Program Memory: The Program Memory on the W77E58 can Kbytes long. There is also on-chip ROM which can be used similarly to that of the 8052, except that the ROM size is 32 Kbytes. All instructions are fetched for execution from this memory area. The MOVC instruction can also access this memory region ...
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... Data Memory: The W77E58 can access up to 64Kbytes of external Data Memory. This memory region is accessed by the MOVX instructions. Unlike the 8051 derivatives, the W77E58 contains on-chip 1K bytes MOVX SRAM of Data Memory, which can only be accessed by MOVX instructions. These 1K bytes of SRAM are between address 0000H and 03FFH. Access to the on-chip MOVX SRAM is optional under software control ...
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... Bank 3 18h 17h Bank 2 10h 0Fh Bank 1 08h 07h Bank 0 00h Figure 2. Scratchpad RAM/Register Addressing Preliminary W77E58 ...
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... The SFRs that are bit addressable are those whose addresses end The W77E58 contains all the SFRs present in the standard 8052. However, some additional SFRs have been added. In some cases unused bits in the original 8052 have been given new functions ...
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... This is the low byte of the standard 8052 16-bit data pointer. DATA POINTER HIGH Bit: 7 DPH.7 Mnemonic: DPH This is the high byte of the standard 8052 16-bit data pointer. DATA POINTER LOW1 Bit: 7 DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0 Mnemonic: DPL1 Preliminary W77E58 P0.6 P0.5 P0.4 P0 SP.6 SP ...
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... This is the low byte of the new additional 16-bit data pointer that has been added to the W77E58. The user can switch between DPL, DPH and DPL1, DPH1 simply by setting register DPS = 1. The instructions that use DPTR will now access DPL1 and DPH1 in place of DPL and DPH. If they are not required they can be used as conventional register locations by the user ...
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... TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set Timer or Counter Select: When cleared, the timer is incremented by internal clocks. When set , the timer counts high-to-low edges of the Tx pin. Preliminary W77E58 TR1 TF0 ...
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... TIMER 1 LSB Bit: 7 TL1.7 Mnemonic: TL1 TL1.7-0:Timer 1 LSB TIMER 0 MSB Bit: 7 TH0.7 Mnemonic: TH0 TH0.7-0:Timer 0 MSB TIMER 1 MSB Bit: 7 TH1.7 Mnemonic: TH1 TH1.7-0:Timer 1 MSB Preliminary W77E58 TL0.6 TL0.5 TL0.4 TL0 TL1.6 TL1.5 TL1.4 TL1 TH0.6 TH0 ...
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... Stretch value MOVX duration machine cycles machine cycles (Default machine cycles machine cycles machine cycles machine cycles machine cycles machine cycles - 16 - Preliminary W77E58 T0M MD2 MD1 Address: 8Eh 17 + 512 20 + 512 23 + 512 26 + 512 0 MD0 ...
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... Mode. Setting this bit allows device operating from RC oscillator when a resume from Power Down Mode. When this bit is cleared, the device will hold operation until the crystal oscillator has warmed-up following a resume from Power Down Mode. This bit is cleared to 0 after a power-on reset and unchanged by other forms of reset. Preliminary W77E58 ...
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... However the restrictions of SM2 apply to this bit. This bit can be cleared only by software SM1 SM2 REN Mode Description Length 0 Synchronous 8 1 Asynchronous 10 2 Asynchronous 11 3 Asynchronous Preliminary W77E58 TB8 RB8 TI Address: 98h Baud rate 4/12 Tclk variable 64/32 Tclk variable 0 RI ...
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... Global enable. Enable/disable all interrupts except for PFI. ES1: Enable Serial Port 1 interrupt. ET2: Enable Timer 2 interrupt. ES: Enable Serial Port 0 interrupt. ET1: Enable Timer 1 interrupt EX1: Enable external interrupt 1 ET0: Enable Timer 0 interrupt EX0: Enable external interrupt 0 Preliminary W77E58 P2.6 P2.5 P2.4 P2 ...
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... Strobe for read from external RAM Strobe for write to external RAM Timer/counter 1 external count input Timer/counter 0 external count input External interrupt 1 External interrupt 0 Serial port 0 output Serial port 0 input PS1 PT2 Preliminary W77E58 Address: A9h Address: AAh P3.3 P3.2 P3.1 P3 ...
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... When used as FE_1, this bit will be set to indicate an invalid stop bit. This bit must be manually cleared in software to clear the FE_1 condition SM1_1 SM2_1 REN_1 - 21 - Preliminary W77E58 Address: B9h Address: BAh TB8_1 RB8_1 TI_1 ...
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... Any read access gets data from the receive data buffer, while write accesses are to the transmit data buffer. ROMMAP Bit Mnemonic: ROMMAP Description Length 0 Synchronous 8 1 Asynchronous 10 2 Asynchronous 11 3 Asynchronous Preliminary W77E58 Baud rate 4/12 Tclk variable 64/32 Tclk variable Address: C1h Address: C2h ...
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... DME0: This bit determines the on-chip MOVX SRAM to be enabled or disabled. Set this bit to 1 will enable the on-chip 1KB MOVX SRAM CD0 SWB - XTOFF CD1, CD0 clocks/machine cycle 0 0 Reserved 1024 1 = ALE expression is disable - 23 - Preliminary W77E58 ALE-OFF - DME0 Address: C4h Publication Release Date: March 1999 Revision A1 0 ...
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... AAH to the TA. This must be immediately followed by a write of 55H to TA. Now a window is opened in the protected bits for three machine cycles, during which the user can write to these bits HIP LIP XTUP SPTA1 TA.6 TA.5 TA Preliminary W77E58 SPRA1 SPTA0 SPRA0 Address: C5h TA.3 TA.2 TA.1 TA.0 Address: C7h 0 ...
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... Bit: 7 HC5 Mnemonic: T2MOD EXF2 RCLK TCLK EXEN2 / 2 , EXEN2 and DCEN bits. If set by a negative HC4 HC3 HC2 - 25 - Preliminary W77E58 TR2 Address: C8h T2CR - T2OE DCEN Address: C9h Publication Release Date: March 1999 Revision ...
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... TIMER 2 LSB Bit: 7 TL2.7 Mnemonic: TL2 TL2: Timer 2 LSB RCAP2L.6 RCAP2L.5 RCAP2L TL2.6 TL2.5 TL2 Preliminary W77E58 RCAP2L.3 RCAP2L.2 RCAP2L.1 Address: CAh Address: CBh TL2.3 TL2.2 TL2.1 Address: CCh 0 RCAP2L TL2.0 ...
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... TH2.5 TH2 RS1 Register bank Address 0 00-07h 1 08-0Fh 2 10-17h 3 18-1Fh POR - - - 27 - Preliminary W77E58 TH2.3 TH2.2 TH2.1 TH2.0 Address: CDh RS0 OV F1 Address: D0h WDIF WTRF EWT RWT Address: D8h Publication Release Date: March 1999 Revision A1 ...
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... EXTENDED INTERRUPT ENABLE Bit Mnemonic: EIE EIE.7-5:Reserved bits, will read high EWDI: Enable Watchdog timer interrupt EX5: External Interrupt 5 Enable. EX4: External Interrupt 4 Enable. EX3: External Interrupt 3 Enable. EX2: External Interrupt 2 Enable. Preliminary W77E58 ACC.6 ACC.5 ACC.4 ACC ...
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... Also, in the W77E58 there is only one fetch per machine cycle i.e. 4 clocks per fetch, while in the standard 8032 there can be two fetches per machine cycle, which works out to 6 clocks per fetch. ...
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... MUL 0 X DIV RRC A X RLC A X SETB "X" indicates that the modification is as per the result of instruction. Table 3. Instruction Timing for W77E58 Instruction HEX Op-Code NOP 00 ADD ADD ADD ADD ADD A, R4 ...
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... Table 3. Instruction Timing for W77E58, continued Instruction HEX Op-Code ADDC A, @R0 36 ADDC A, @R1 37 ADDC A, direct 35 ADDC A, #data 34 ACALL addr11 71,91,B1, 11,31,51, D1,F1 AJMP ADDR11 01,21,41, 61,81,A1, C1,E1 ANL ANL ANL ANL ANL ANL ANL ANL ANL A, @R0 56 ANL A, @R1 ...
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... Table 3. Instruction Timing for W77E58, continued Instruction HEX Op-Code CLR A E4 CPL A F4 CLR C C3 CLR bit C2 CPL C B3 CPL bit B2 DEC A 14 DEC R0 18 DEC R1 19 DEC R2 1A DEC R3 1B DEC R4 1C DEC R5 1D DEC R6 1E DEC R7 1F DEC @R0 16 ...
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... Table 3. Instruction Timing for W77E58, continued Instruction HEX Op-Code INC R6 0E INC R7 0F INC @R0 06 INC @R1 07 INC direct 05 INC DPTR A3 JMP @A+DPTR 73 JZ rel 60 JNZ rel 70 JC rel 40 JNC rel 50 JB bit, rel 20 JNB bit, rel 30 JBC bit, rel 10 LCALL addr16 ...
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... Table 3. Instruction Timing for W77E58, continued Instruction HEX Op-Code MOV R1, direct A9 MOV R2, direct AA MOV R3, direct AB MOV R4, direct AC MOV R5, direct AD MOV R6, direct AE MOV R7, direct AF MOV R0, #data 78 MOV R1, #data 79 MOV R2, #data 7A MOV R3, #data 7B MOV R4, #data 7C MOV R5, #data 7D MOV R6, #data 7E MOV R7, #data 7F MOV @R0 ...
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... Table 3. Instruction Timing for W77E58, continued Instruction HEX Op-Code MOVX A, @R0 E2 MOVX A, @R1 E3 MOVX A, @DPTR E0 MOVX @R0 MOVX @R1 MOVX @DPTR MOV C, bit A2 MOV bit ORL ORL ORL ORL ORL ORL ORL A, R6 ...
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... Table 3. Instruction Timing for W77E58, continued Instruction HEX Op-Code SUBB SUBB SUBB SUBB SUBB SUBB SUBB A, @R0 96 SUBB A, @R1 97 SUBB A, direct 95 SUBB A, #data 94 XCH XCH XCH XCH XCH XCH A, R5 ...
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... However, in the W77E58 each machine cycle is made of only 4 clock periods compared to the 12 clock periods for the standard 8032. Therefore, even though the number of categories has increased, each instruction is at least 1 ...
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... CLK ALE PSEN PC AD7-0 PORT 2 Instruction Fetch CLK ALE PSEN A7-0 OP-CODE AD7-0 PORT 2 Address A15-8 Figure 5. Three Cycle Instruction Timing Preliminary W77E58 Operand Fetch OP-CODE PC+1 Address A15-8 Figure 4. Two Cycle Instruction Timing Operand Fetch A7-0 OPERAND Address A15 ...
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... Address A15-8 Address A15-8 Figure 6. Four Cycle Instruction Timing Operand Fetch OPERAND A7-0 A7-0 OPERAND Address A15-8 Address A15-8 Figure 7. Five Cycle Instruction Timing - 39 - Preliminary W77E58 Operand Fetch OPERAND A7-0 OPERAND Address A15-8 Operand Fetch Operand Fetch ...
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... SFR. In the MOVX @DPTR type, the full 16-bit address is supplied by the Data Pointer. Since the W77E58 has two Data Pointers, DPTR and DPTR1, the user has to select between the two by setting or clearing the DPS bit. The Data Pointer Select bit (DPS) is the LSB of the DPS SFR, which exists at location 86h ...
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... Machine cycles in W77E58 = 10 + (26 * CNT) If CNT = 50 Clock cycles in standard 8032= ((10 + (26 *50 (10 + 1300 15720 Clock cycles in W77E58 = ((10 + ( (10 + 1300 5240 Block Move with Two Data Pointers in W77E58 and SL are the high and low bytes of Source Address ; DH and DL are the high and low bytes of Destination Address ...
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... A0-A7 D0-D7 D0-D7 A0-A7 Next Inst. MOVX Data Address Address . MOVX Inst Next Inst. Read A15-A8 A15-A8 Figure 8. Data Memory Write with Stretch Value = Preliminary W77E58 strobe width strobe width @ 25 MHz @ 40 MHz 160 nS 100 nS 320 nS 200 nS 480 nS 300 nS 640 nS ...
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... CLK ALE PSEN WR D0-D7 A0-A7 A0-A7 PORT 0 MOVX Inst. Next Inst. Address Address MOVX Inst. PORT 2 A15-A8 Figure 9. Data Memory Write with Stretch Value = 1 Preliminary W77E58 Second Third Machine Cycle Machine Cycle MOVX instruction cycle D0-D7 D0-D7 A0-A7 MOVX Data MOVX Data out Address Next Inst ...
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... Wait State Control Signal Either with the software using stretch value to change the required machine cycle of MOVX instruction, the W77E58 provides another hardware signal WAIT to implement the wider duration of external data access timing. This wait state control signal is the alternate function of P4.0 such that it can only be invoked to 44-pin PLCC/QFP package type ...
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... original rising edge Extended duration sample WAIT Third Second Machine Machine Cycle Cycle MOVX Instruction Preliminary W77E58 Wait-State Cycle sample WAIT Fourth Wait-State Machine Cycle Cycle ...
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... Watchdog timer in order to preempt the reset which will occur after 512 clock periods of the time-out. When the W77E58 is exiting from an Idle mode with a reset, the instruction following the one which put the device into Idle mode is not executed. So there is no danger of unexpected writes. ...
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... ALE and PSEN pins are pulled low. The port pins output the values held by their respective SFRs. The W77E58 will exit the Power Down mode with a reset external interrupt pin enabled as level detect. An external reset can be used to exit the Power down state. The high on RST pin terminates the Power Down mode, and restarts the clock ...
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... The W77E58 can be woken from the Power Down mode by forcing an external interrupt pin activated, provided the corresponding interrupt is enabled, while the global enable(EA) bit is set and the external input has been set to a level detect mode. If these conditions are met, then the low level on the external pin re-starts the oscillator ...
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... PCON 00xx0000b TCON 00000000b TMOD 00000000b TL0 00000000b TL1 00000000b TH0 00000000b TH1 00000000b CKCON 00000001b P1 11111111b Preliminary W77E58 falls below approximately 2V, as this is the minimum DD SFR Name IE SADDR P3 IP SADEN T2CON T2MOD RCAP2L RCAP2H TL2 TH2 TA PSW WDCON ACC ...
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... EWT bit. INTERRUPTS The W77E58 has a two priority level interrupt structure with 12 interrupt sources. Each of the interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the interrupts can be globally enabled or disabled. ...
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... Timer 2 Overflow Serial Port 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 Watchdog Timer Flag Priority level IE0 1(highest) TF0 2 IE1 3 TF1 TF2 + EXF2 6 RI_1 + TI_1 7 IE2 8 IE3 9 IE4 10 IE5 11 WDIF 12 (lowest Preliminary W77E58 Publication Release Date: March 1999 Revision A1 ...
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... Timer 2 Interrupt 002Bh External Interrupt 2 0043h External Interrupt 4 0053h Watchdog Timer 0063h The vector table is not evenly spaced; this is to accommodate future expansions to the device family. Preliminary W77E58 Source Vector Address External Interrupt 0 0003h External Interrupt 1 0013h Serial Port 0023h Serial Port 1 ...
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... If the polling cycle is not the last machine cycle of the instruction being executed, then an additional delay is introduced. The maximum response time (if no other interrupt is in service) occurs if the W77E58 is performing a write to IE, IP, EIE or EIP and then executes a MUL or DIV instruction. From the time an interrupt source is activated, the longest reaction time is 12 machine cycles ...
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... W77E58 and the standard 8051 can be matched. This is the default mode of operation of the W77E58 timers. The user also has the option to count in the turbo mode, where the timers will increment at the rate of 1/4 clock speed. This will straight-away increase the counting speed three times ...
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... Tn. Timer 1 functions are shown in brackets C/T = TMOD.2 1 (C/T = TMOD. TL0 (TL1) Figure 11. Timer/Counter Mode 0 & Mode Preliminary W77E58 M1,M0 = TMOD.1,TMOD.0 (M1,M0 = TMOD.5,TMOD. TH0 (TH1) Interrupt TFx TF0 ...
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... The clock is then enabled when TR2 and disabled when TR2 Timer 1 functions are shown in brackets C/T = TMOD.2 1 (C/T = TMOD.6) (TL1 TH0 (TH1) Figure 12. Timer/Counter Mode GATE, TR0, INT0 and TF0. The TL0 can be used to count clock - 56 - Preliminary W77E58 TL0 Interrupt 7 TFx TF0 (TF1) 7 ...
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... T2EX pin will cause the value in the TL2 and TH2 register to be captured by the RCAP2L and RCAP2H registers. This action also causes the EXF2 bit in T2CON to be set, which will also generate an interrupt. Setting the T2CR bit (T2MOD.3), the W77E58 allows hardware to reset timer 2 automatically after the value of TL2 and TH2 have been captured. ...
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... A reload will also toggle the EXF2 bit. However, the EXF2 bit can not generate an interrupt while in this mode. 1 C/T2 = T2CON TL2 1 RCAP2L Figure 15. 16-Bit Auto-reload Mode, Counting Preliminary W77E58 / 2 bit in the T2CON register T2CON.7 TH2 TF2 Timer 2 Interrupt RCAP2H EXF2 T2CON.6 ...
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... TL2 TH2 1 RCAP2L RCAP2H Up Counting Reload Value DCEN = 1 Figure 16. 16-Bit Auto-reload Up/Down Counter C/T = T2CON.1 0 TL2 1 RCAP2L Figure 17. Baud Rate Generator Mode - 59 - Preliminary W77E58 .7 T2CON Timer 2 TF2 Interrupt EXF2 T2CON.6 Timer 2 TH2 overflow RCAP2H Timer 2 EXF2 Interrupt T2CON.6 Publication Release Date: March 1999 ...
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... The interrupt will occur if the individual interrupt enable and the global enable are set. The interrupt and reset functions are independent of each other and may be used separately or together depending on the users software. input osc/2 osc/32 TL2 RCAP2L Figure 18. Programmable Clock-Out Mode - 60 - Preliminary W77E58 1/2 TH2 T2=P1.0 RCAP2H Timer 2 EXF2 Interrupt T2CON.6 ...
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... The interrupt feature is enabled in this case. Every time the time-out occurs an interrupt will occur if the global interrupt enable EA is set. 16 WD1,WD0 Time-out Enable Watchdog timer reset EWT(WDCON.1) Figure 19. Watchdog Timer - 61 - Preliminary W77E58 Interrupt WDIF EWDI(EIE.4) WTRF 512 clock delay Publication Release Date: March 1999 Revision A1 Reset ...
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... Setting this bit to 0 will disable the Watchdog timer reset function, but will leave the timer running. Number of Time Clocks @ 1.8432 MHz 131072 71.11 mS 1048576 568.89 mS 8388608 4551.11 mS 67108864 36408. Preliminary W77E58 Time Time @ 10 MHz @ 25 MHz 13.11 mS 5.24 mS 104.86 mS 41.94 mS 838.86 mS 335.54 mS 6710.89 mS 2684.35 mS ...
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... The TxD line is used to output the shift clock. The shift clock is used to shift data into and out of the W77E58 and the device at the other end of the line. Any instruction that causes a write to SBUF will start the transmission. The shift clock will be activated and data will be shifted out on the RxD pin till all 8 bits are transmitted ...
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... Transmit Shift Register TI SERIAL RI CONTROLLE SHIFT CLOCK LOAD SBUF RX SHIFT CLOCK PAROUT SIN Receive Shift Register Figure 20. Serial Port Mode Preliminary W77E58 RXD SOUT P3.0 Alternate Output Function Serial Port Interrupt TXD P3.1 Alternate Output function Read SBUF SBUF Internal SBUF Data Bus ...
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... If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set. Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to looking for a 1-to-0 transition on the RxD pin. Preliminary W77E58 Publication Release Date: March 1999 - 65 - ...
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... TX SHIFT TX CLOCK TI SERIAL RI CONTROLLER RX CLOCK LOAD RX SBUF START RX SHIFT CLOCK PAROUT BIT SIN DETECTOR Receive Shift Register Figure 21. Serial Port Mode Preliminary W77E58 STOP PARIN SOUT TXD START LOAD CLOCK Serial Port Interrupt Read SBUF SBUF D8 RB8 Internal Data Bus ...
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... TI SERIAL CONTROLLER RI RX CLOCK LOAD RX START SBUF RX SHIFT CLOCK PAROUT BIT SIN DETECTOR Receive Shift Register Figure 22. Serial Port Mode Preliminary W77E58 D8 STOP PARIN TXD SOUT START LOAD CLOCK Transmit Shift Register Serial Port Interrupt Read SBUF Internal SBUF D8 RB8 ...
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... Figure 23. Serial Port Mode 3 Baud Clock Frame size bits CLKS Timer bits bits T CLKS Timer bits - 68 - Preliminary W77E58 D8 PARIN SOUT TXD START LOAD CLOCK Serial Port Interrupt Read SBUF Internal SBUF D8 RB8 Start ...
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... A Frame Error occurs when a valid stop bit is not detected. This could indicate incorrect serial data communication. Typically the frame error is due to noise and contention on the serial communication line. The W77E58 has the facility to detect such framing errors and set a flag which can be checked by software. ...
Page 70
... Power on/fail reset flag, which are crucial to proper operation of the system. If left unprotected, errant code may write to the Watchdog control bits resulting in incorrect operation and loss of control. In order to prevent this, the W77E58 has a protection scheme which controls the write access to critical bits. This protection scheme is done using a timed access. ...
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... TA occurs 4 machine cycles after the first write, therefore the timed access window in not opened at all, and the write to the protected bit fails. ON-CHIP MTP ROM CHARACTERISTICS The W77E58 has several modes to program the on-chip MTP ROM. All these operations are configured by the pins RST, ALE, PSEN PSEN, A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2), OECTRL(P3.3), CE (P3.6), OE (P3.7), A0(P1.0) and V P1 ...
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... P3.6 and P3.7 pins, the individual chips may have common inputs. COMPANY/DEVICE ID READ OPERATION This operation is supported for MTP ROM programmer to get the company ID or device ID on the W77E58. (12.5V) level, CE set to low, and OE set to high erasing or programming of non-targeted chips is inhibited. So Preliminary W77E58 is reach (14.5V high and PP EP ...
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... PGM DATA P0 A0-A7 EA/Vpp ALE RST PSEN A8-A15 P2 Programming Verification - 73 - Preliminary W77E58 P2, (A15..A0) (D7..D0 Address Data Out 1 X Hi-Z V Address Data Address Data Out CP V A0:0, Data In EP others: X 0FFH V Address Data Out ...
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... Until the code inside the MTP ROM is confirmed OK, the code can be protected. The protection of MTP ROM and those operations on it are described below. The W77E58 has several Special Setting Registers, including the Security Register and Company/Device ID Registers, which can not be accessed in normal mode. These registers can only be accessed from the MTP ROM operation mode ...
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... B0:Lock bit This bit is used to protect the customer's program code in the W77E58. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the MTP ROM data and Special Setting Registers can not be accessed again. ...
Page 76
... IL1 V 0 0.8 IL2 V 0 0.8 IL3 V 2.4 V +0.2 IH1 DD V 3.5 V +0.2 IH2 DD V 3.5 V +0.2 IH3 0.45 OL1 V - 0.45 OL2 V 2.4 - OH1 V 2.4 - OH2 - 76 - Preliminary W77E58 TEST CONDITIONS UNIT load V = RST = 5. Idle mode V = 5.5V DD Power-down mode 0<V < 5. 0V<V < ...
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... CLOCK MIN 1/t 0 CLCL t 1.5t LHLL CLCL t 0.5t AVLL CLCL t 0.5t LLAX1 CLCL t 0.5t LLAX2 CLCL t LLIV t 0.5t LLPL CLCL t 2.0t PLPH CLCL - 77 - Preliminary W77E58 CHCX MAX. UNITS NOTES - VARIABLE UNITS CLOCK MAX 40 MHz - 2. CLCL - Publication Release Date: March 1999 Revision ...
Page 78
... CLCL MCS t 2. WLWH CLCL MCS t 2.0t RLDV t MCS t 0 RHDX t t RHDZ CLCL 2.0t t 2.5t LLDV t MCS t 3.0t AVDV1 2. Preliminary W77E58 VARIABLE UNITS CLOCK MAX 2. CLCL CLCL 3. CLCL 3. CLCL CLCL 0. CLCL VARIABLE UNITS STRECH ...
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... MOVX Cycles 0 2 machine cycles 1 3 machine cycles 0 4 machine cycles 1 5 machine cycles 0 6 machine cycles 1 7 machine cycles 0 8 machine cycles 1 9 machine cycles - 79 - Preliminary W77E58 VARIABLE UNITS STRECH CLOCK MAX + CLCL MCS + 5 t CLCL MCS nS t MCS ...
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... PROGRAM MEMORY READ CYCLE t LHLL ALE t AVLL PSEN ADDRESS PORT 0 A0-A7 PORT 2 A Address D Input Data L Logic level low P PSEN R RD signal W WR signal Z Tri-state t LLIV t PLPH t PLIV t LLPL t PLAZ t PXIX t LLAX1 INSTRUCTION IN t AVIV1 t AVIV2 ADDRESS A8-A15 - 80 - Preliminary W77E58 t PXIZ ADDRESS A0-A7 ADDRESS A8-A15 ...
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... LLWL t RLRH t LLAX1 t RLDV t AVLL t RLAZ t AVWL1 ADDRESS DATA A0-A7 t AVDV1 t AVDV2 ADDRESS A8-A15 t LLWL t WLWH t LLAX2 t AVLL t AVWL1 t QVWX ADDRESS DATA OUT A0-A7 t AVDV2 ADDRESS A8-A15 - 81 - Preliminary W77E58 t WHLH t RHDZ t RHDX ADDRESS IN A0-A7 t WHLH t WHQX ADDRESS A0-A7 Publication Release Date: March 1999 Revision A1 ...
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... P2.2 24 A11 P2.3 25 A12 P2.4 26 A13 P2.5 27 A14 P2.6 28 A15 P2 PSEN 30 ALE 11 TXD 10 RXD Figure A C1 30P 30P 15P 15P 10P 10P Preliminary W77E58 ...
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... P2.7 28 P1 P1.3 29 P1.4 PSEN 30 P1.5 ALE 11 P1.6 TXD 10 P1.7 RXD W77E58 Figure Base Plane A 1 Seating Plane Preliminary W77E58 AD0 AD1 AD2 AD3 ...
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... Detail Preliminary W77E58 Dimension in inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. A 0.185 4.699 A 0.020 0.508 1 A 0.145 0.150 3.683 3.81 3.937 0.155 2 b 0.026 0.028 0.032 ...
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... No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. Preliminary W77E58 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U ...