IDT723631L30PF Integrated Device Technology, Inc., IDT723631L30PF Datasheet
IDT723631L30PF
Related parts for IDT723631L30PF
IDT723631L30PF Summary of contents
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... SEN FS 1/ MBF2 The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 1997 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 • ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 DESCRIPTION (CONTINUED) stored in memory. Communication between each port may take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 PIN CONFIGURATION (CONTINUED GND ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 PIN DESCRIPTION Symbol Name A0-A35 Port-A Data AE Almost-Empty Flag AF Almost-Full Flag. B0-B35 Port-B Data. CLKA Port-A Clock CLKB Port-B Clock CSA Port-A Chip Select CSB Port-B ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 PIN DESCRIPTION (CONTINUED) Symbol Name MBF2 Mail2 Register Flag OR Output-Ready Flag RFM Read From Mark RST Reset RTM Retransmit Mode Port-A Write/Read Select W ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED) Symbol V Supply Voltage Range CC (2) V Input Voltage Range I V (2) Output Voltage Range ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE Symbol Parameter f Clock Frequency, CLKA or CLKB S t Clock Cycle Time, CLKA or ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 ELECTRICAL CHARACTERISTICS Symbol Parameter f Clock Frequency, CLKA or CLKB S t Access Time, CLKB to B0-B35 A t Propagation Delay Time, CLKA to IR PIR t ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 SIGNAL DESCRIPTION RESET The IDT723631/723641/723651 is reset by taking the RST reset ( ) input LOW for at least four port-A clock (CLKA) and four port-B (CLKB) LOW-to-HIGH ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 impedance control of the data outputs port enable is LOW during a clock cycle, the port chip select and write/read select may change states during the ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 ready flag is HIGH, a memory location is free in the SRAM to write new data. No memory locations are free when the input- ready flag is LOW ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 SYNCHRONOUS RETRANSMIT The synchronous retransmit feature of the IDT723631/ 723641/723651 allows FIFO data to be read repeatedly starting at a user-selected position. The FIFO is first put into ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 CLKA CLKB t RSTS RST FS1,FS0 RSF AE t RSF AF t RSF MBF1 , MBF2 Figure 1. FIFO Reset Loading X and Y with ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 CLKA 4 RST IR t FSS SEN FS1/ t FSH t FSS FS0/SD NOTE not necessary to program offset register bits on consecutive clock cycles. ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 CLKA CSA LOW HIGH t t ENS2 ENH2 MBA t t ENS1 ENH1 ENA HIGH A35 W1 t ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 CLK t t CLKH CLKL CLKB CSB LOW W /RB HIGH MBB LOW t ENS1 ENB HIGH OR B0 -B35 Previous Word in FIFO Output Register CLKA ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 CLKA t t ENH1 ENS1 ENA t PAF AF (2) [Depth -(Y+1)] Words in FIFO CLKB ENB NOTES: 1. tSKEW2 is the minimum time between a rising CLKA ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 CLKA IR FIFO Filled to First Restransmit Word CLKB t RMS RTM NOTE: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 CLKA t ENS2 CSA MBA ENA A0 - A35 CLKB MBF1 CSB W /RB MBB ENB B35 FIFO Output Register t ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 CLKB t ENS2 CSB W /RB MBB ENB B0 - B35 CLKA MBF2 CSA MBA ENA A35 t ENH2 t DH ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 250 f = 1/2 f data 0pF L 200 150 100 CALCULATING POWER DISSIPATION The I (f) ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 PARAMETER MEASUREMENT INFORMATION From Output Timing 1.5 V Input t S Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1 PLZ ...
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IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 ORDERING INFORMATION IDT XXXXXX X Device Type Power Speed Package Process/ Temperature Range COMMERCIAL TEMPERATURE RANGE BLANK Commercial ( + Thin ...