M95010-WBN6P STMicroelectronics, M95010-WBN6P Datasheet
M95010-WBN6P
Related parts for M95010-WBN6P
M95010-WBN6P Summary of contents
Page 1
... More than 40-Year Data Retention Table 1. Product List Reference Part Number M95040 M95040 M95040-W M95040-R M95020 M95020 M95020-W M95020-R M95010 M95010 M95010-W M95010-R October 2004 M95020, M95010 With High Speed Clock Figure 1. Packages 8 1 PDIP8 (BN SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width M95040 1/37 ...
Page 2
... M95040, M95020, M95010 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Serial Data Output ( Serial Data Input ( Serial Clock ( Chip Select ( Hold (HOLD Write Protect (W) ...
Page 3
... Table 20. AC Characteristics (M950x0-W, Device Grade Table 21. AC Characteristics (M950x0-W, Device Grade Table 22. AC Characteristics (M950x0- Figure 16.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 17.Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 18.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 19.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 32 M95040, M95020, M95010 3/37 ...
Page 4
... M95040, M95020, M95010 Table 23. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 32 Figure 20.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 33 Table 24. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data 33 Figure 21.TSSOP8 – ...
Page 5
... The M95040 Kbit (512 x 8) electrically eras- able programmable memory (EEPROM), access high speed SPI-compatible bus. The other members of the family (M95020 and M95010) are identical, though proportionally smaller (2 and 1 Kbit, respectively). Each device is accessed by a simple serial inter- face that is SPI-compatible ...
Page 6
... M95040, M95020, M95010 SIGNAL DESCRIPTION During all operations, V must be held stable and CC within the specified valid range (max). CC All of the input and output signals can be held High or Low (according to voltages specified in Table 13. OL signals are described next. Serial Data Output (Q). This output signal is used to transfer data serially out of the device ...
Page 7
... MCU SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the others being high impedance SPI Memory SPI Memory Device Device HOLD W M95040, M95020, M95010 SPI Memory Device S HOLD W HOLD AI03746D 7/37 ...
Page 8
... M95040, M95020, M95010 SPI Modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: – CPOL=0, CPHA=0 – CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data Figure 5 ...
Page 9
... The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C) already being Low. Figure 6. and falling edges are not timed to coincide with Serial Clock (C) being Low. Hold Condition M95040, M95020, M95010 . also shows what happens if the rising Hold Condition Figure AI02029D 9/37 ...
Page 10
... M95040, M95020, M95010 Status Register Figure 7. shows the position of the Status Register in the control logic of the device. This register con- tains a number of control bits and status bits, as shown in Table 3.. Bits b7, b6, b5 and b4 are always read as 1. WIP bit. The Write In Progress bit is a volatile read-only bit that is automatically set and reset by the internal logic of the device ...
Page 11
... MEMORY ORGANIZATION The memory is organized as shown in Figure 7. Block Diagram HOLD W Control Logic Address Register and Counter Figure 7.. High Voltage Generator I/O Shift Register Data Register 1 Page X Decoder M95040, M95020, M95010 Status Register Size of the Read only EEPROM area AI01272C 11/37 ...
Page 12
... M95040, M95020, M95010 INSTRUCTIONS Each instruction starts with a single-byte code, as summarized in Table 5 invalid instruction is sent (one not contained in Table 5.), the device automatically deselects it- self. 12/37 Table 5. Instruction Set Instruc Description tion WREN Write Enable WRDI Write Disable RDSR Read Status Register ...
Page 13
... Power-up – WRDI instruction execution – WRSR instruction completion – WRITE instruction completion – Write Protect (W) line being held Low Instruction High Impedance AI03790D M95040, M95020, M95010 8., to send this instruction to 13/37 ...
Page 14
... M95040, M95020, M95010 Read Status Register (RDSR) One of the major uses of this instruction is to allow the MCU to poll the state of the Write In Progress (WIP) bit. This is needed because the device will not accept further WRITE or WRSR instructions when the previous Write cycle is not yet finished. ...
Page 15
... Select (S) being driven High, after the eighth bit, b0, of the data byte has been latched in – if Write Protect (W) is Low Instruction Status Register High Impedance MSB M95040, M95020, M95010 Table 18. to Table AI01445B 22.), at 15/37 ...
Page 16
... M95040, M95020, M95010 Read from Memory Array (READ) As shown in Figure 12., to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte and address byte are then shifted in, on Serial Data Input (D). For the M95040, the most significant address bit, A8, is in- ...
Page 17
... Protect (BP1 and BP0) bits Byte Address Table 6., the most significant address bits are Don’t Care. M95040, M95020, M95010 Data Byte AI01442D 17/37 ...
Page 18
... M95040, M95020, M95010 Figure 14. Page Write (WRITE) Sequence Data Byte Note: Depending on the memory size, as shown in 18/ Instruction Byte Address ...
Page 19
... Write In Progress (WIP) is reset to 0 The BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits). M95040, M95020, M95010 Initial Delivery State The device is delivered with the memory array set at all 1s (FFh). The Block Protect (BP1 and BP0) bits are initialized to 0 ...
Page 20
... M95040, M95020, M95010 MAXIMUM RATING Stressing the device outside the ratings listed in Table 7. may cause permanent damage to the de- vice. These are stress ratings only, and operation of the device at these, or any other conditions out- side those indicated in the Operating sections of Table 7. Absolute Maximum Ratings ...
Page 21
... Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. Parameter Parameter Parameter Parameter Input Levels Timing Reference Levels 0.8V CC 0.2V CC M95040, M95020, M95010 Min. Max. 4.5 5.5 –40 85 –40 125 Min. Max. 2.5 5.5 – ...
Page 22
... M95040, M95020, M95010 Table 12. Capacitance Symbol Parameter C Output Capacitance (Q) OUT C Input Capacitance (D) IN Input Capacitance (other pins) Note: Sampled only, not 100% tested Table 13. DC Characteristics (M950x0, Device Grade 6) Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current ...
Page 23
... Previous Product 2 Present Product 1 –0 M95040, M95020, M95010 Min. Max. Unit ± 2 ± 0.3 V –0. 0.4 0 Min. Max. Unit ± ...
Page 24
... M95040, M95020, M95010 Table 16. DC Characteristics (M950x0-W, Device Grade 3) Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current CC Supply Current I CC1 (Standby Power mode) V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH Note: 1 ...
Page 25
... Value guaranteed by characterization, not 100% tested in production. 3. Previous product: identified by Process Identification letter K. 4. Present product: identified by Process Identification letter Table 11. and Parameter Min. D.C. 100 (max) C M95040, M95020, M95010 Table Max. Min. Max ...
Page 26
... M95040, M95020, M95010 Table 19. AC Characteristics (M950x0, Device Grade 3) Test conditions specified in Symbol Alt Clock Frequency C SCK Active Setup Time SLCH CSS1 Not Active Setup Time SHCH CSS2 Deselect Time SHSL Active Hold Time CHSH ...
Page 27
... Value guaranteed by characterization, not 100% tested in production. 3. Previous product: identified by Process Identification letter K. 4. Present product: identified by Process Identification letter Table 11. and Parameter Min. D.C. 200 200 200 200 200 200 200 140 (max) C M95040, M95020, M95010 Table Max. Min. Max 100 ...
Page 28
... M95040, M95020, M95010 Table 21. AC Characteristics (M950x0-W, Device Grade 3) Test conditions specified in Symbol Alt Clock Frequency C SCK Active Setup Time SLCH CSS1 Not Active Setup Time SHCH CSS2 Deselect Time SHSL Active Hold Time CHSH ...
Page 29
... Value guaranteed by characterization, not 100% tested in production. 3. Preliminary data: Product under development. Please contact your nearest ST sales office for information. Table 11. and Table 10. Parameter (max) C M95040, M95020, M95010 Min. Max. Unit D.C. 2 MHz 200 ns 200 ns ...
Page 30
... M95040, M95020, M95010 Figure 16. Serial Input Timing S tCHSL C tDVCH D High Impedance Q Figure 17. Hold Timing HOLD 30/37 tSLCH tCHSH tCHDX tCLCH MSB IN tHLCH tCHHL tCHHH tHLQZ tSHSL tSHCH tCHCL LSB IN AI01447C tHHCH tHHQV AI02032B ...
Page 31
... Figure 18. Output Timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D tCH tCLQV tQLQH tQHQL M95040, M95020, M95010 tCL tSHQZ LSB OUT AI01449D 31/37 ...
Page 32
... M95040, M95020, M95010 PACKAGE MECHANICAL Figure 19. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline Note: Drawing is not to scale. Table 23. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data Symb. Typ 3.30 b 0.46 b2 1.52 c 0.25 D 9.27 E 7.87 E1 6.35 e 2. 3.30 32/37 b2 ...
Page 33
... Min. Max. 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 – – 5.80 6.20 0.25 0.50 0.40 0.90 0° 8° 8 0.10 M95040, M95020, M95010 h x 45˚ inches Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 0.050 – 0.228 0.010 0.016 0° 8 Max. 0.069 0.010 0.020 0.010 0.197 0.157 – 0.244 0.020 0.035 8° ...
Page 34
... M95040, M95020, M95010 Figure 21. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline A CP Note: Drawing is not to scale. Table 25. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data Symbol Typ 1.000 3.000 e 0.650 E 6.400 E1 4.400 L 0.600 L1 1.000 ...
Page 35
... Table 27. How to Identify Present and Previous Products by the Process Identification Letter Markings on Present Products 95040W6 AYWWW (or AYWWG) M95040 – -free and TBBA-free 2 3 device, please contact your nearest ST Sales Of- fice. 1 M95040, M95020, M95010 Markings on Previous Products 95040W6 AYWWK 35/37 ...
Page 36
... M95040, M95020, M95010 REVISION HISTORY Table 28. Document Revision History Date Version 10-May-2000 2.2 s/issuing three bytes/issuing two bytes/ in the 2nd sentence of the Byte Write Operation Human Body Model meets JEDEC std (Table 2). Minor adjustments to Figs 7,9,10,11 & Tab 16-Mar-2001 2.3 9. Wording changes, according to the standard glossary ...
Page 37
... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com M95040, M95020, M95010 37/37 ...