K7R323684M-FC25 Samsung, K7R323684M-FC25 Datasheet
K7R323684M-FC25
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K7R323684M-FC25 Summary of contents
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... K7R323684M K7R321884M Document Title 1Mx36-bit, 2Mx18-bit QDR Revision History Rev. No. History 0.0 1. Initial document. 0.1 1. Package dimension modify. P.20 from 13mmx15mm to 15mmx17mm 0.2 1. Pin name change from DLL to Doff. 2. Vddq range change from 1.5V to 1.5V~1.8V. 3. Update JTAG test conditions. 4. Reserved pin for high density name change from NC to Vss/SA 5 ...
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... QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung techno logy. 1Mx36 & 2Mx18 QDR II b4 SRAM TM Organization X36 X18 72(or 36) 72(or 36) WRITE DRIVER 18 1Mx36 (2Mx18) MEMORY ARRAY SELECT OUTPUT CONTROL - SRAM Part Cycle Access Number Time Time K7R323684M-FC25 4.0 0.45 K7R323684M-FC20 5.0 0.45 K7R323684M-FC16 6.0 0.50 K7R321884M-FC25 4.0 0.45 K7R321884M-FC20 5.0 0.45 K7R321884M-FC16 6.0 0.50 72 144 (or 36) 36 (or 18) (or 72) Q(Data Out) 72 ...
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... 5F,7F,5G,7G,5H,7H,5J,7J,5K, 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L DDQ 2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M TMS TDI TCK TDO NC Notes cannot be set to V REF 2. When ZQ pin is directly connected Not connected to chip pad internally. 1Mx36 & 2Mx18 QDR K7R323684M(1Mx36 ...
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... K7R323684M K7R321884M PIN CONFIGURATIONS (TOP VIEW) K7R321884M(2Mx18 /SA D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H Doff V V REF DDQ D14 Q14 L NC Q15 D15 D16 N NC ...
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... The K7R323684M and K7R321884M are37,748,736-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 1,048,576 words by 36bits for K7R323684M and 2,097,152 words by 18 bits for K7R321884M. The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports with the same cycle ...
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... And "late writed" data is presented to the device on every rising edge of both K and K clocks. The device disregards input data presented on the same cycle W disabled. When the W is disabled after a read operation, the K7R323684M and K7R321884M will first complete burst read operation before entering into deselect mode at the next K clock rising edge. ...
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... K7R323684M K7R321884M READ NOP READ LOAD NEW D count=2 READ ADDRESS D count=0 ALWAYS DDR READ D count=D count+1 READ D count=1 INCREMENT READ ADDRESS Notes : 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1. 2. "READ" refers to read active status with R=Low, "READ" refers to read inactive status with R=high. "WRITE" and "WRITE" are the same case. ...
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... K7R323684M K7R321884M TRUTH TABLES SYNCHRONOUS TRUTH TABLE D(A1) Previous Stopped X X state Din K(t+1) Notes means "Don t Care". 2. The rising edge of clock is symbolized Before enter into clock stop status, all pending read and write operations will be completed. ...
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... K7R323684M K7R321884M ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on V Supply Relative Voltage on V Supply Relative to V DDQ Voltage on Input Pin Relative Storage Temperature Operating Temperature Storage Temperature Range Under Bias *Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati ng sections of this specification is not implied ...
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... K7R323684M K7R321884M AC ELECTRICAL CHARACTERISTICS PARAMETER Input High Voltage Input Low Voltage Notes: 1. This condition is for AC function test only, not for AC parameter test maintain a valid level, the transitioning edge of the input must : a) Sustain a constant slew rate from the current AC level through the target AC level, V ...
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... K7R323684M K7R321884M AC TIMING CHARACTERISTICS PARAMETER Clock Clock Cycle Time ( Clock Phase Jitter ( Clock High Time ( Clock Low Time ( Clock to Clock ( Clock to data clock ( DLL Lock Time ( Static to DLL reset ...
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... K7R323684M K7R321884M PIN CAPACITANCE PRMETER Address Control Input Capacitance Input and Output Capacitance Clock Capacitance Note: 1. Parameters are tested with RQ=250 2. Periodically sampled and not 100% tested. THERMAL RESISTANCE PRMETER Junction to Ambient Junction to Case Junction to Pins Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site thermal impedance ...
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... K7R323684M K7R321884M TIMING WAVE FORMS OF READ AND NOP READ t KHKH t KLKH KHKL IVKH KHIX R Q (Data Out) t KHKH t KLKH KHKL Note : 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0. ...
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... K7R323684M K7R321884M TIMING WAVE FORMS OF READ, WRITE AND NOP READ D(Data In) D(Data Out Note address A3=A2, data Q3-1=D2-1, data Q3-2=D2-2 , data Q3-3=D2-3, data Q3-4=D2-4 Write data is forwarded immediately as read results. 2.BWx ( NWx ) assumed active. 1Mx36 & 2Mx18 QDR WRITE READ A2 A3 ...
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... K7R323684M K7R321884M IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control ...
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... K7R323684M K7R321884M SCAN REGISTER DEFINITION Part Instruction Register 1Mx36 3 bits 2Mx18 3 bits ID REGISTER DEFINITION Revision Number Part (31:29) 1Mx36 000 2Mx18 000 Note : Part Configuration /def=010 for 36Mb, /wx=11 for x36, 10 for x18 /t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O ...
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... K7R323684M K7R321884M JTAG DC OPERATING CONDITIONS Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage(I =-2mA) OH Output Low Voltage(I =2mA) OL Note: 1. The input level of SRAM pin is to follow the SRAM DC specification JTAG AC TEST CONDITIONS Parameter Input High/Low Level ...
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... K7R323684M K7R321884M 165 FBGA PACKAGE DIMENSIONS 15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array Symbol Value Units 0.1 C 1.3 0.1 D 0.35 0.05 1Mx36 & 2Mx18 QDR Note Symbol SRAM B Top View Side View ...