W83877AF Winbond, W83877AF Datasheet
W83877AF
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W83877AF Summary of contents
Page 1
... PIN DESCRIPTION................................................................................................................................5 1.1 HOST INTERFACE ...........................................................................................................................5 1.2 SERIAL PORT INTERFACE .............................................................................................................6 1.3 GAME PORT/POWER DOWN INTERFACE ....................................................................................8 1.4 MULTI-MODE PARALLEL PORT....................................................................................................9 1.5 IDE AND FDC INTERFACE ...........................................................................................................17 2.0 FDC FUNCTIONAL DESCRIPTION ...................................................................................................19 2.1 W83877AF FDC...............................................................................................................................19 2.2 REGISTER DESCRIPTIONS ...........................................................................................................33 3.0 IDE..........................................................................................................................................................45 3.1 IDE DECODE DESCRIPTION ........................................................................................................45 4.0 UART PORT ..........................................................................................................................................45 4.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B)....................45 4.2 REGISTER ADDRESS.....................................................................................................................45 4.3 IR PORT...........................................................................................................................................52 5 ...
Page 2
... FDC..............................................................................................................................................149 10.2 IDE...............................................................................................................................................150 10.3 UART/PARALLEL.......................................................................................................................151 11.0 APPLICATION CIRCUITS...............................................................................................................160 11.1 PARALLEL PORT EXTENSION FDD ........................................................................................160 11.2 PARALLEL PORT EXTENSION 2FDD ......................................................................................161 11.3 PARALLEL PORT JOYSTICK MODE ........................................................................................162 11.4 FOUR FDD MODE ......................................................................................................................162 12.0 ORDERING INFORMATION ..........................................................................................................163 13.0 PACKAGE DIMENSIONS ................................................................................................................163 - II - W83877AF Publication Release Date: Dec. 1996 PreliminaryVersion 0.52 ...
Page 3
... The JOYSTICK mode allows a joystick to be connected to a parallel port with a signal switching cable. The W83877AF supports two embedded hard disk drive (IDE AT bus) interfaces and a game port with decoded read/write output. The configuration registers support mode selection, function enable/disable, and power down function selection ...
Page 4
... Fully programmable serial-interface characteristics 8-bit characters Even, odd or no parity bit generation/detection 1, 1 stop bits generation Internal diagnostic capabilities: Loop-back controls for communications link fault isolation Break, parity, overrun, framing error simulation Publication Release Date: Dec. 1996 - 2 - Preliminary Version 0.52 W83877AF ...
Page 5
... Immediate or automatic power-down mode for power management All hardware power-on settings have internal pull-up or pull-down resistors as default value Package: 100-pin QFP (W83877AF), and 100-pin TQFP (W83877AD) Compatible with IEEE 1284 specification Compatible with IEEE 1284 specification Publication Release Date: Dec. 1996 ...
Page 6
... W83877AF RIB 50 X DCDB DSRB X CTSB ...
Page 7
... IR module mode select 1. 12t IR module mode select 2. 12t System address bus enable CPU I/O read signal CPU I/O write signal DMA request signal B 12t DMA Acknowledge signal B DMA request signal C 12t DMA Acknowledge signal W83877AF FUNCTION Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 8
... UART. Data Carrier Detect. An active low indicates the modem or data set has detected a data carrier. Ring Indicator. An active low indicates that a ring signal is being received by the modem or data set W83877AF FUNCTION FUNCTION Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 9
... During power-on reset, this pin is pulled down internally and is defined as PGOIQSEL, which provides the power-on value for CR16 bit 4 (GOIQSEL pull up at power-on reset W83877AF is recommended when is recommended when intends is recommended when intends is recommended when intends is recommended when intends Publication Release Date: Dec ...
Page 10
... CRA (PDCHACT). Default is high active. DMA acknowledge signal D. IR module mode select 1. 12t When input pin, high speed IR received terminal. When as output pin, IR module mode select 0. Input or output are definied in high speed IR register W83877AF FUNCTION Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 11
... EXTENSION ADAPTER MODE: XDRQ DMA request generated by the Extension Adapter. An active high input. EXTENSION 2FDD MODE: DSB2 This pin is for Extension FDD A and B; this function of this pin is the same as that of the DSB pin. JOYSTICK MODE: NC pin W83877AF Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 12
... EXTENSION ADAPTER MODE: XA1 12t This pin is system address A1 for the Extension Adapter. EXTENSION 2FDD MODE: WE2 This pin is for Extension FDD A and B; this function of this pin is the same as that of the WE pin. JOYSTICK MODE: NC pin W83877AF FUNCTION Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 13
... This pin is the DMA terminal count for the Extension Adapter. The count is sent by TC directly. EXTENSION 2FDD MODE: STEP2 This pin is for Extension FDD A and B; its function is the same as that of the STEP pin. JOYSTICK MODE: V for joystick. DD 12t - 11 - W83877AF FUNCTION Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 14
... Extension Adapter can latch the same base address. EXTENSION 2FDD MODE: RWC2 This pin is for Extension FDD A and B; its function is the same as that of the RWC pin. JOYSTICK MODE: V for joystick. DD 12t - 12 - W83877AF FUNCTION Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 15
... EXTENSION 2FDD MODE: INDEX2 This pin is for Extension FDD A and B; this function of this pin is the same as INDEX pin. This pin is pulled high internally. JOYSTICK MODE: JP0 This pin is the paddle 0 input for joystick W83877AF FUNCTION for joystick. Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 16
... This pin is system data bus D2 for the Extension Adapter. EXTENSION. 2FDD MODE: WP2 This pin is for Extension FDD A and B; this function of this pin is the same as that of the WP pin. This pin is pulled high internally. JOYSTICK MODE: NC pin - 14 - W83877AF Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 17
... EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION ADAPTER MODE: XD5 This pin is system data bus D5 for the Extension Adapter. EXTENSION 2FDD MODE: This pin is a tri-state output. JOYSTICK MODE: JB1 This pin is the button 1 input for the joystick W83877AF Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 18
... EXTENSION ADAPTER MODE: XD7 This pin is system data bus D7 for the Extension Adapter. EXTENSION 2FDD MODE: DSA2 This pin is for Extension FDD A; its function is the same as that of the DSA pin. JOYSTICK MODE: NC pin - 16 - W83877AF Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 19
... FDD function is enabled, and the pin will have a different definition. Refer to the EN3MODE bit in CR9. Write data. This logic low open drain writes precompensation serial data to the selected FDD. An open drain output W83877AF FUNCTION Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 20
... Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. Drive Select B. When set to 0, this pin enables disk drive B. This is an open drain output. +5 Volt power supply for the digital circuitry Ground - 18 - W83877AF Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 21
... FDC FUNCTIONAL DESCRIPTION 2.1 W83877AF FDC The floppy disk controller of the W83877AF integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports up to data rate 1 M bits/sec ...
Page 22
... A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk. Publication Release Date: Dec. 1996 - 20 - Preliminary Version 0.52 W83877AF ...
Page 23
... Tape Drive The W83877AF supports standard tape drives (1 Mbps, 500 Kbps, 250 Kbps) and new fast tape drive (2M bps). When working bps, you need to change the crystal to 48 MHz. 2.1.7 FDC Core The W83877AF FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor ...
Page 24
... Relative Cylinder Number R/W: Read/Write SC: Sector/per cylinder SK: Skip deleted data address mark SRT: Step Rate Time ST0: Status Register 0 ST1: Status Register 1 ST2: Status Register 2 ST3: Status Register 3 WG: Write gate alters timing of WE Publication Release Date: Dec. 1996 - 22 - Preliminary Version 0.52 W83877AF ...
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... R ---------------------- R ------------------------ R ---------------------- N ------------------------ HDS - 23 - W83877AF D1 D0 REMARKS 1 0 Command codes DS1 DS0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: Dec. 1996 ...
Page 26
... R ------------------------ R ---------------------- N ------------------------ HDS - 24 - W83877AF D1 D0 REMARKS 0 0 Command codes DS1 DS0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: Dec. 1996 ...
Page 27
... HDS DS1 - 25 - W83877AF D0 REMARKS 0 Command codes DS0 Sector ID information prior to command execution Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT Status information after command execution Sector ID information after command execution Publication Release Date: Dec ...
Page 28
... HDS HDS - 26 - W83877AF D1 D0 REMARKS 1 0 Command codes DS1 DS0 The first correct ID information on the cylinder is stored in Data Register Status information after command execution Disk status after the command has been completed D1 D0 REMARKS ...
Page 29
... HDS - 27 - W83877AF D1 D0 REMARKS 0 0 Command codes 0 0 Enhanced controller D1 D0 REMARKS 0 1 Command codes DS1 DS0 Sector ID information prior to Command execution Data transfer between the FDD and system Status information after ...
Page 30
... HDS DS1 - 28 - W83877AF D0 REMARKS 1 Command codes DS0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 31
... ST2 ----------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- HDS - 29 - W83877AF D1 D0 REMARKS 0 1 Command codes DS1 DS0 Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters Status information after command execution Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 32
... HDS DS1 ------ FIFOTHR ----| EFIFO POLL - 30 - W83877AF D1 D0 REMARKS 1 1 Command codes DS1 DS0 Head retracted to Track 0 Interrupt D1 D0 REMARKS 0 0 Command codes Status information at the end of each seek operation D1 D0 REMARKS 1 1 Command codes ...
Page 33
... LOCK W83877AF D1 D0 REMARKS 1 1 Command codes DS1 DS0 D1 D0 REMARKS Registers placed in FIFO REMARKS 1 0 Command code GAP REMARKS 0 0 Command code 0 0 Publication Release Date: Dec. 1996 ...
Page 34
... PHASE R Command W ------------- Invalid Codes ----------------- Result R -------------------- ST0 ---------------------- 2.2 Register Descriptions There are several status, data, and control registers in W83877AF. These registers are defined below: ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 7 2.2.1 Status Register A (SA Register) (Read base address + 0) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes ...
Page 35
... This bit indicates the value of INDEX output. WP (Bit 1): 0disk is write-protected 1disk is not write-protected DIR (Bit 0) This bit indicates the direction of head movement. 0 outward direction 1 inward direction In PS/2 Model 30 mode, the bit definitions for this register are as follows: Publication Release Date: Dec. 1996 - 33 - Preliminary Version 0.52 W83877AF ...
Page 36
... This bit indicates the complement of INDEX output. WP (Bit 1): 0 disk is not write-protected 1 disk is write-protected DIR (Bit 0) This bit indicates the direction of head movement. 0 inward direction 1 outward direction DIR WP INDEX HEAD TRAK0 STEP F/F INIT PENDING - 34 - W83877AF DRQ Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 37
... In PS/2 Model 30 mode, the bit definitions for this register are as follows W83877AF MOT EN A MOT RDATA Toggle WDATA Toggle Drive SEL0 DSC DSD WE F/F RDATA F/F WD F/F DSA DSB DRV2 Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 38
... DMA and INT Enable Active high enable DRQ/IRQ Motor Enable A. Motor A on when active high Motor Enable B. Motor B on when active high Motor Enable C. Motor C on when active high Motor Enable D. Motor D on when active high - 36 - W83877AF Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 39
... TAPE SEL 0 DRIVE SELECTED W83877AF Tape sel 0 Tape sel 1 Tape Sel 0 Tape Sel 1 Floppy boot drive 0 Floppy boot drive 1 Drive type ID0 Drive type ID1 Media ID0 Media ID1 None Publication Release Date: Dec. 1996 ...
Page 40
... If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor W83877AF DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 41
... KB/S (MFM), 250 KB/S (FM), RWC = 1. 01 300 KB/S (MFM), 150 KB/S (FM), RWC = 0. 10 250 KB/S (MFM), 125 KB/S (FM), RWC = MB/S (MFM), Illegal (FM), RWC = 1. PRECOMPENSATION DELAY Default Delays 41.67 nS 83.34 nS 125.00 nS 166.67 nS 208.33 nS 250.00 nS 0.00 nS (disabled) DEFAULT PRECOMPENSATION DELAYS 125 nS 125 nS 125 nS 41.67 nS Publication Release Date: Dec. 1996 - 39 - W83877AF Preliminary Version 0.52 ...
Page 42
... This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83877AF, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. ...
Page 43
... Reserved for the hard disk controller x During a read of this register, these bits are in tri-state DSKCHG - 41 - W83877AF US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready WP Write Protected FT Fault Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 44
... Bit 6-4: These bits are always a logic 1 during a read. DMAEN (Bit 3): This bit indicates the value of DO REGISTER bit W83877AF HIGH DENS DRATE0 DRATE1 DSKCHG 0 DRATE0 DRATE1 NOPREC DMAEN DSKCHG Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 45
... This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC Reserved - 43 - W83877AF 0 DRATE0 DRATE1 DRATE0 DRATE1 NOPREC Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 46
... Error Register Write-Precomp Sector Count Sector Count Sector Number Sector Number Cylinder LOW Cylinder LOW Cylinder HIGH Cylinder HIGH SDH Register SDH Register Status Register Command Register Alternate Status Fixed Disk Control Publication Release Date: Dec. 1996 - 44 - W83877AF WRITE Preliminary Version 0.52 ...
Page 47
... CTS DSR RI Falling Toggling Toggling Edge (TCTS) (TDSR) (FERI) Bit 0 Bit 1 Bit 2 Bit 0 Bit 1 Bit 2 Bit 8 Bit 9 Bit W83877AF Data RX Data RX Data Bit 3 Bit 4 Bit 5 TX Data TX Data TX Data Bit 3 Bit 4 Bit 5 HSR 0 0 Interrupt Enable ...
Page 48
... Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB W83877AF Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 49
... RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI W83877AF Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 50
... Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR . Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable CTS, Loopback RI input ( bit 2 of HCR) DCD . - 48 - W83877AF Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 51
... Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB W83877AF Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 52
... Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below W83877AF 0 if interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 53
... RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI W83877AF Clear Interrupt - Read USR 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR 1. Write data into TBR 2 ...
Page 54
... The percentage error for all baud rates, except where indicated otherwise, is 0.16%. Decimal divisor used to Percent error difference between generate 16X clock 2304 1536 1047 857 768 384 192 W83877AF 16 -1. The output frequency of desired and actual ** ** 0.18% 0.099 0.53 Publication Release Date: Sep. 1996 ...
Page 55
... IR Port In the W83877AF includes two serial ports, that is UART A and UART B. The second serial port, UART B, also has built in the Infrared (IR) functions which include IrDA 1.0 SIR, IrDA 1.1 MIR (1.152M bps), IrDA FIR (4M bps), SHARP ASK-IR, and remote control (that support NEC, RC-5, advanced RC-5, and RECS-80 protocol) ...
Page 56
... Note that two DMA channel are defined in config register CR2A which select DMA channel or disable DMA channel. If enable RX DMA channel and disable TX DMA channel, then the single DMA channel will be selected. Sets Description Register Description Publication Release Date: Sep. 1996 - 54 - Preliminary Version 0.50 W83877AF ...
Page 57
... Write to 1, enable transmitter buffer register empty interrupt. ERBRI - Enable RDR (Receiver Buffer Register) Interrupt Bit 0: Write to 1, enable receiver buffer register interrupt EHSRI ETXTHI EDMAI EHSRI - 55 - W83877AF EUSRI ETBREI ERDRI EUSRI/ ETBREI ERXTHI TXURI Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 58
... Set to 1 when overrun, or parity bit, or stop bit, or silent byte detected error in the UART Status Register (USR) sets to 1. Clear to 0 when USR is read. MIR, FIR modes IID2 TXTH_I DMA_I HS_I W83877AF IID1 IID0 IP USR_I/ TXEMP_I RXTH_I FEND_I Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 59
... TXFTL1 TXFTL0 0 (MSB) (LSB FIFO Threshold Level RX FIFO Threshold Level (FIFO Size: 16-byte W83877AF Bit 2 Bit 1 Bit 0 TXF_RST RXF_RST EN_FIFO TXF_RST RXF_RST EN_FIFO 0 0 (FIFO Size: 32-byte Publication Release Date: Sep. 1996 Preliminary Version 0.50 0 ...
Page 60
... XLOOP EN_IRQ TX_WT W83877AF TX FIFO Threshold Level (FIFO Size: 32-byte Selected Set Set 0 Set1 Set 2 Set 3 Set 4 Set 5 Set 6 Set LP_RI RTS EN_DMA RTS Publication Release Date: Sep ...
Page 61
... TX FIFO. That is in order to avoid Underrun. Other modes: Not used. Selected Mode Advanced UART Low speed MIR (0.576M bps) Advanced ASK-IR Advanced SIR High Speed MIR (1.152M bps) FIR (4M bps) Consumer IR Reserved Publication Release Date: Sep. 1996 - 59 - W83877AF Preliminary Version 0.50 ...
Page 62
... SET4.Reg6 and Reg5.If this bit is set to 1, the receiver will not receive any data to RX FIFO. MIR, FIR modes: Bit 3: PHY_ERR - Physical Layer Error TBRE SBD NSER TBRE MX_LEX PHY_ERR CRC_ERR W83877AF PBER OER RDR OER RDR Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 63
... B3 DSR CTS TDCD DSR CTS TDCD Bit 5 Bit 4 Bit 3 Bit 5 Bit 4 Bit 3 RX_BSY/ LST_FE/ S_FEND RX_IP RX_PD W83877AF FERI TDSR TCTS FERI TDSR TCTS Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 0 LB_SF RX_TO Publication Release Date: Sep. 1996 ...
Page 64
... Set to 1 that indicates one or more than one frame end still stay in receiver FIFO. MIR, FIR, Remote IR modes: Bit 0: RX_TO - Receiver FIFO or Frame Status FIFO time-out Set to 1 when receiver FIFO or frame status FIFO occurs time-out Publication Release Date: Sep. 1996 - 62 - Preliminary Version 0.50 W83877AF ...
Page 65
... SIR/ASK-IR. 4.3.3.2 Set1.Reg 2~7 This registers is defined as same as Set 0 registers. Register Description Advanced Mode DIS_BACK=¡Ñ Bit 7~5 Bit Bit 2, 3 Publication Release Date: Sep. 1996 - 63 - W83877AF Legacy Mode DIS_BACK=0 - Bit Preliminary Version 0.50 ...
Page 66
... If use signal DMA channel in MIR/FIR mode, then the DMA channel can be swapped. D_CHSW Write to 1, then enable output data during the ALOOP=1. Register Description Bit 5 Bit 4 Bit 3 EN_LOUT D_CHSW ALOOP DMA Channel Selected 0 Receiver (Default) 1 Transmitter - 64 - W83877AF - Bit 2 Bit 1 Bit 0 DMATHL DMA_F ADV_SL Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 67
... Write it to select other register Set. 16 Bit 5 Bit 4 Bit 3 SSR5 SSR4 SSR3 Bit 5 Bit 4 Bit 3 PR_DIV1 PR_DIV0 RX_FSZ1 RX_FSZ0 TX_FSZ1 TXFSZ0 W83877AF RX FIFO Threshold (16/32-Byte Bit 2 Bit 1 SSR2 SRR1 SRR0 0 0 Bit 2 Bit Publication Release Date: Sep. 1996 Preliminary Version 0 ...
Page 68
... RX FIFO Size 16-Byte 32-Byte Reserved TX FIFO Size 16-Byte 32-Byte Reserved Bit 5 Bit 4 Bit 3 TXFD5 TXFD4 TXFD3 W83877AF 115.2K bps 921.6K bps 230.4K bps 1.5M bps Bit 2 Bit 1 Bit 0 TXFD2 TXFD1 TXFD1 Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 69
... Reg1 - Mapped UART Control Register (MP_UCR) Read only. Read this register that returns UART Control Register value of Set 0. Bit 5 Bit 4 Bit 3 RXFD5 RXFD4 RXFD3 Register Description - - - - - 67 - W83877AF Bit 2 Bit 1 Bit 0 RXFD2 RXFD1 RXFD1 Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 70
... Write it to select other register Set. 16 Bit 5 Bit 4 Bit 3 SSR5 SSR4 SSR3 Register Description Bit 5 Bit 4 Bit IR_MSL1 IR_MSL0 TMR_TST EN_TMR W83877AF Bit 2 Bit 1 Bit 0 SSR2 SRR1 SRR0 ms. Bit 2 Bit 1 Bit Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 71
... Bit 5 Bit 4 Bit 3 SSR5 SSR4 SSR3 Bit 5 Bit 4 Bit 3 bit 5 bit 4 bit3 bit 12 bit W83877AF Bit 2 Bit 1 Bit 0 SSR2 SRR1 SRR0 Bit 2 Bit 1 Bit 0 bit 2 bit 1 bit bit 10 bit 9 bit Publication Release Date: Sep. 1996 ...
Page 72
... FCBLL/FCBHL are loaded to advanced baud rate divisor latch (ADBLL/ADBHL). Bit 5 Bit 4 Bit 3 bit 5 bit 4 bit bit 12 bit Register Description - 70 - W83877AF Bit 2 Bit 1 Bit 0 bit 2 bit 1 bit bit 10 bit 9 bit Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 73
... Bit 4 Bit 3 - FC_DSW Next Mode After Flow Control Occurred Receiver Channel Transmitter Channel Bit 5 Bit 4 Bit 3 SSR5 SSR4 SSR3 W83877AF Bit 2 Bit 1 Bit 0 EN_FD EN_BRFC EN_FC Bit 2 Bit 1 Bit 0 SSR2 SRR1 SRR0 Publication Release Date: Sep. 1996 ...
Page 74
... Bit 5 Bit 4 Bit 3 FEND_M AUX_RX - Status FIFO Threshold Level 2 4 Bit 5 Bit 4 Bit 3 - MX_LEX PHY_ERR CRC_ERR RX_OV W83877AF Bit 2 Bit 1 Bit 0 - IRHSSL IR_FULL Bit 2 Bit 1 Bit 0 FSF_OV Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 75
... RFLFH will pop-up another frame status and frame length if FSFDR=1 (Set5.Reg4.Bit7). Bit 5 Bit 4 Bit 3 Bit 5 Bit 4 Bit Bit 12 Bit W83877AF Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit Bit 10 Bit 9 Bit Publication Release Date: Sep. 1996 ...
Page 76
... SHDM_N - ASK-IR Demodulation Disable Bit 6: SHDM_N Register Description Bit 5 Bit 4 Bit Modulation Mode 0 SOUT modulate 500K Hz Square Wave 1 Demodulation Mode 0 Demodulation 500K W83877AF - - - Bit 2 Bit 1 - INV_CRC DIS_CRC Re-rout SOUT Re-rout SIN Publication Release Date: Sep. 1996 Preliminary Version 0.50 Bit ...
Page 77
... Bit 4 Bit 3 - M_PW4 M_PW3 0 0 MIR Pulse Width (1.152M bps 20.83 ns 41.66 (==20.83*2) ns ... 20.83 ... 645 W83877AF CRC Type 16-bit CRC 32-bit CRC CRC Type 16-bit CRC 32-bit CRC Bit 2 Bit 1 M_PW2 M_PW1 MIR Output Width (0.576M bps 41.66 ns 83.32 (==41.66*2) ns ... ...
Page 78
... SIR Output Pulse Width 3/16 bit time of UART 1.6 us 1.6 us Bit 5 Bit 4 Bit 3 SSR5 SSR4 SSR3 Bit 5 Bit 4 Bit 3 M_FG1 M_FG0 F_FL3 W83877AF Bit 2 Bit 1 Bit 0 S_PW2 S_PW1 S_PW0 Bit 2 Bit 1 Bit 0 SSR2 SRR1 SRR0 Bit 2 Bit 1 ...
Page 79
... These bits define the number of transmitter Preamble Flag in FIR. Note that the number of FIR start flag should be equal to sixteen which is defined in IrDA 1.1 physical layer. The default value is 16. Beginning Flag Number Reserved 1 2 (Default Reserved Publication Release Date: Sep. 1996 - 77 - W83877AF Preliminary Version 0.50 ...
Page 80
... Infrared Module (Front End) Select 1 5 IRM_SL2 Infrared Module Select 2 6 IRM_SL3 Infrared Module Select 3 7 IRM_CR Infrared Module Control Register Beginning Flag Number Reserved (Default Reserved Register Description Publication Release Date: Sep. 1996 - 78 - W83877AF Preliminary Version 0.50 ...
Page 81
... Note that the other non-defined values are reserved. Bit 5 Bit 4 Bit 3 RX_FR0 RX_FSL4 RX_FSL3 RX_FSL2 RX_FSL1 RX_FSL0 RX_FR2~0 (Low Frequency) 010 Max. Min. Max. 29.6 24.7 31.7 32.0 26.7 34.3 33.3 27.8 35.7 34.0 28.4 36.5 35.6 29.6 38.1 36.4 30.3 39.0 37.2 31.0 39.8 38.1* 31.7 40.8 39.0 32.5 41.8 41.0 34.2 44.0 42.1 35.1 45.1 43.2 36.0 46.3 45.7 38.1 49.0 47.1 39.2 50.4 48.5 40.4 51.9 50.0 41.7 53.6 51.6 43.0 55.3 55.2 46.0 59.1 57.1 47.6 61.2 61.5 51.3 65 W83877AF Bit 2 Bit 1 Bit 011 Min. Max. 23.4 34.2 25.3 36.9 26.3 38.4 26.9 39.3 28.1 41.0 28.7 42.0 29.4 42.9 30.1 44.0 30.8 45.0 32.4 47.3 33.2 48.6 34.1 49.9 36.1 52n.7 37.2 54.3 38.3 56.0 39.5 57.7 40.7 59.6 43.6 63.7 45.1 65.9 48.6 71.0 Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 82
... RX_FSL4~0 (SHARP ASK-IR) 010 011 100 436.4 600.0 417.4 640.0 Bit 5 Bit 4 Bit Low Frequency 10 W83877AF Max. 457.1 489.8 527.4 101 110 400.0 685.6 384.0 738.5 Bit 2 Bit 1 Bit High Frequency 0.7 s 0 ...
Page 83
... Write to 1 then directly use programmed baud rate to do over-sampling. Low Frequency 30K Hz 31K HZ ... 56K Hz High Frequency 400K Hz 450K Hz 480K Hz Bit 5 Bit 4 Bit 3 RXCFS - TX_CFS 0 0 (Number of bits Bit value - 81 - W83877AF Bit 2 Bit 1 RX_DM TX_MM1 TX_MM0 Publication Release Date: Sep. 1996 Preliminary Version 0.50 Bit 0 0 ...
Page 84
... Bit 5 Bit 4 Bit 3 Bit 5 Bit 4 Bit Write this register then switch to other Set. 16 Bit 5 Bit 4 Bit W83877AF Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit Bit 2 Bit 1 Bit 0 AIR_SL2 AIR_SL1 AIR_SL0 Publication Release Date: Sep. 1996 ...
Page 85
... Bit 6 IRM_SL3 - LRC_SL2 LRC_SL1 LRC_SL0 default Value 0 0 Bit 5 Bit 4 Bit 3 FIR_SL1 FIR_SL0 - Bit 5 Bit 4 Bit W83877AF Bit 2 Bit 1 Bit 0 MIR_SL2 MIR_SL1 MIR_SL0 Bit 2 Bit 1 Bit 0 HRC_SL2 HRC_SL1 HRC_SL0 Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 86
... Select function for IRRXH or IRSL0 because they are common pin and different input/output direction. IRSL0_D Bit 5 Bit 4 Bit 3 IRSL0D RXINV TXINV 0 0 Receiver Pin selected 0 IRRX (Low/High Speed) 1 IRRXH (High Speed W83877AF Bit 2 Bit Function IRRXH (I/P) IRSL0 (O/P) Publication Release Date: Sep. 1996 Preliminary Version 0.50 Bit ...
Page 87
... TXINV - Transmitting Signal Invert Bit 3: Write to 1, Invert the transmitting signal. Reserved, write 0. Bit 2~0: AUX_RX High Speed Publication Release Date: Sep. 1996 - 85 - W83877AF Selected IR Pin IRRX IRRXH IRRX IRRXH IRRX Reserved IRRX Reserved Preliminary Version 0.50 ...
Page 88
... Printer Interface Logic The parallel port of the W83877AF makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83877AF supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD), Extension Adapter mode (EXTADP), and JOYSTICK mode on the parallel port ...
Page 89
... I/O I/O PD5 I/O I/O PD6 I/O I/O PD7 I/O I nACK I I BUSY SLCT O O nAFD O I nERR O O nINIT O O nSLIN W83877AF EXT2FDD PIN EXTFDD ATTRIBUTE I DSKCHG2 DSKCHG2 --- --- --- MOA2 --- DSA2 OD DSB2 OD MOB2 OD WD2 WD2 OD WE2 WE2 OD RWC2 RWC2 OD NERR2 OD DIR2 DIR2 OD STEP2 EXTADP PIN ...
Page 90
... EPP address port (R/W) 0 EPP data port 0 (R/W) 1 EPP data port 1 (R/W) 0 EPP data port 2 (R/W) 1 EPP data port 2 (R/ W83877AF NOTE TMOUT ERROR SLCT PE ACK BUSY Publication Release Date: Dec. 1996 Preliminary Version 0. ...
Page 91
... Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be present for a minimum of 0.5 microseconds before and after the strobe pulse STROBE AUTO FD INIT SLCT IN IRQ ENABLE DIR - 89 - W83877AF Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 92
... CPU auses an EPP address write cycle to be performed, and the W83877AF 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Publication Release Date: Dec ...
Page 93
... IRQEN 1 1 DIR IRQ PD6 PD5 PD4 PD6 PD5 PD4 PD6 PD5 PD4 PD6 PD5 PD4 PD6 PD5 PD4 EPP DESCRIPTION - 91 - W83877AF PD3 PD2 PD1 1 1 TMOUT ERROR SLIN INIT AUTOFD STROBE SLIN INIT AUTOFD STROBE PD3 PD2 PD1 PD3 ...
Page 94
... Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte repeated. Hardware support for compression is optional. For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA Interface Standard. Publication Release Date: Dec. 1996 - 92 - W83877AF Preliminary Version 0.52 ...
Page 95
... ECP FIFO (Address) R All Status Register R/W All Control Register R/W 010 Parallel Port Data FIFO R/W 011 ECP FIFO (DATA) R/W 110 Test FIFO R 111 Configuration Register A R/W 111 Configuration Register B R/W All Extended Control Register DESCRIPTION Publication Release Date: Dec. 1996 - 93 - W83877AF FUNCTION Preliminary Version 0.52 ...
Page 96
... Bit 2-0: These three bits are not implemented and are always logic one during a read W83877AF 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Address or RLE Address/RLE 1 nFault Select PError nAck nBusy Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 97
... When the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to the system W83877AF Strobe Autofd nInit Select In AckInt En Direction Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 98
... IRQ10 100 IRQ11 101 IRQ14 110 IRQ15 111 IRQ5 Bit 2-0: These five bits are at high level during a read and can be written IRQ resource - 96 - W83877AF IRQx 0 IRQx 1 IRQx 2 intrValue compress . Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 99
... Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted (interrupt) an interrupt will be generated and this bit is written from Bit 3: Read/Write 1 Enables DMA. 0 Disables DMA unconditionally Empty Full Service Intr DMA En nErrIntr En MODE MODE MODE - 97 - W83877AF Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 100
... These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO PD5 PD4 PD3 PError Select nFault Directio ackIntEn SelectIn nErrIntrEn dmaEn serviceIntr - 98 - W83877AF NOTE PD2 PD1 PD0 nInit autofd strobe ...
Page 101
... ECP Mode. O This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. O This signal is always deasserted in ECP mode W83877AF DESCRIPTION Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 102
... PeriphAck is low. The most significant bit of the command is always zero. Data Compression The W83877AF supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo ...
Page 103
... I/O will empty or fill the FIFO using the appropriate direction and mode. 5.4 Extension FDD Mode (EXTFDD) In this mode, the W83877AF changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 5-1 ...
Page 104
... The operation of EXTADP mode is described below: 1. Set the W83877AF to EXTADP mode by programming bit 7 of CR7 as low and bit 3 and bit 2 of CR0 as high and low, respectively. 2. The W83877AF CR2 is an address register that records the address of the extension adapter. ...
Page 105
... GMWR pin is low active. 7.0 PLUG AND PLAY CONFIGURATION A powerful new plug-and-play function has been built into the W83877AF to help simplify the task of setting up a computer environment. With appropriate support from BIOS manufacturers, the system designer can freely allocate Winbond I/O devices (i.e., the FDC, PRT, UART, IDE, and game port) in the PC's I/O space (100H - 3FFH) ...
Page 106
... MR = 1). A warm reset will not affect the configuration registers. 8.1 Extended Functions Enable Registers (EFERs) After a power-on reset, the W83877AF enters the default operating mode. Before the W83877AF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers ...
Page 107
... ECP Mode and EPP Mode, PRTMOD2 = PRTMODS0 (BIT 2 OF CR0 105 - W83877AF OCSS0 OCSS1 PRTMODS0 PRTMODS1 Reserved Reserved Reserved Reserved SPP EXTFDC EXTADP EXT2FDD JOYSTICK EPP/SPP ECP ECP/EPP Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 108
... W83877AF must wait 128 mS for the oscillator to stabilize. 10 Standby for automatic power-down (APD), OSCS2 = 0 When bit 1 is set to 1 and bit 0 is set to 0, the W83877AF will stand by for automatic power-down. A power-down will occur when the following conditions obtain: FDC not busy ...
Page 109
... XD1-XD7. After the base address is latched into CR2, a subsequent read/write cycle to this same base address will generate an XRD or XWR signal. If CEA is set to 0, then the W83877AF will compare system addresses SA9-SA3 with EA9-EA3 to generate a compare-equal signal for this read/write command to access the Extension adapter. If CEA is set to 1, then only EA9-EA4 are used in this comparison ...
Page 110
... EPPVER (Bit 5): This bit selects the EPP version of parallel port: 0 Selects the EPP 1.9 version 1 Selects the EPP 1.7 version (default) Bit 7-bit 6: Reserved 108 - W83877AF SUBMIDI SUAMIDI Reserved Reserved GMODS EPPVER GMENL Reserved Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 111
... The output pins of the game port will not be tri-stated when game port is in power- down mode. (default) 1 The output pins of the game port will be tri-stated when game port is in power-down mode. URATRI (Bit 1 109 - W83877AF URBTRI URATRI GMTRI PRTTRI URBPWD URAPWD GMPWD PRTPWD Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 112
... When the device is in Extended Function mode and EFIR is 06H, the CR6 register can be accessed through EFDR. The bit definitions are as follows 110 - W83877AF ECPFTHR0 ECPFTHR1 ECPFTHR2 ECPFTHR3 Reserved Reserved Reserved Reserved IDETRI FDCTRI IDEPWD FDCPWD FIPURDWM SEL4FDD OSCS2 Reserved Publication Release Date: Dec. 1996 ...
Page 113
... Bit 7: Reserved OSCS2 (Bit 6): This bit and OSCS1, OSCS0 (bit CR0) select one of the W83877AF's power- down functions. Refer to descriptions of CR0. (Default SEL4FDD (Bit 5): Selects four FDD mode 0 Selects two FDD mode (default, see Table 8-2) 1 Selects four FDD mode DSA , DSB , MOA and MOB output pins are encoded as show in Table 8-3 to select four drives ...
Page 114
... RWC= 1, the data transfer rate is 500 Kb/s. Three mode FDD select (EN3MODE = 1; Bit 5 of CR9 = 1 FDD A type 0 FDD A type 1 FDD B type 0 FDD B type 1 FDD C type 0 FDD C type 1 FDD D type 0 FDD D type 1 - 112 - W83877AF Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 115
... Don't care RWC, selects 720 KB double-density FDD. 8.2.9 Configuration Register 8 (CR8), default = 00H When the device is in Extended Function mode and EFIR is 08H, the CR8 register can be accessed through EFDR. The bit definitions are as follows: , selects 720 KB double-density FDD. - 113 - W83877AF Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 116
... Normal, use WP to determine whether the FDD is write-protected or not 1 FDD is always write-protected Media ID 1 Media ID 0 (Bit 3, 2 Floppy Boot Drive 0 Floppy Boot Drive 1 Media ID 0 Media ID 1 SWWP DISFDDWR APDTMS2 APDTMS1 - 114 - W83877AF Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 117
... This bit enables or disables the reading and writing of all configuration registers. 0 Enables the reading and writing of CR0-CR29 1 Disables the reading and writing of CR0-CR29 (locks W83877AF extension functions) EN3MODE (Bit 5): This bit enables or disables three mode FDD selection. When this bit is high, it enables the read/write 3F3H register. ...
Page 118
... These four bits are read-only bits that contain chip identification information. The value is 0BH for W83877AF during a read. 8.2.11 Configuration Register A (CRA), default = 1FH When the device is in Extended Function mode and EFIR is 0AH, the CRA register can be accessed through EFDR. The bit definitions are as follows: ...
Page 119
... ENIFCHG (Bit 4): This bit is active high. When active, it enables host interface mode change, which is determined by IDENT (Bit 3) and MFM (Bit 2 117 - W83877AF DRV2EN INVERTZ MFM IDENT ENIFCHG RXW4C TXW4C DSPRTPU Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 120
... Configuration Register C (CR0C), default = 28H When the device is in Extended Function mode and EFIR is 0CH, the CR0C register can be accessed through EFDR. The bit definitions are as follows: INTERFACE Model 30 mode PS/2 mode AT mode AT mode Publication Release Date: Dec. 1996 - 118 - W83877AF Preliminary Version 0.52 ...
Page 121
... W83877AF TX2INV RX2INV Reserved URIRSEL ENBKIRSL HEFERE TURB TURA Publication Release Date: Dec. 1996 ...
Page 122
... IRMODE2 (bit 2): IR function mode selection bit IRTX output on pin disabled IRTX1 (pin 43) IRTX2 (pin 95) disabled IRRX input on pin disabled IRRX1 (pin 42) IRRX2 (pin 94) disabled - 120 - W83877AF IRMODE0 IRMODE1 IRMODE2 HDUPLX SIRRX0 SIRRX1 SIRTX0 SIRTX1 Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 123
... IRDA 0 0 MUX 0 1 MUX IRMODE0 1 MUX (CRD.bit0) IRMODE2 (CRD.bit2) 1 URIRSEL (CRC,bit3) 0 MUX IRMODE0 (CRD.bit0) - 121 - W83877AF IRRX high Demodulation into SINB Demodulation into SINB routed to SINB routed to SINB Demodulation into SINB Demodulation into SINB IRRX1 SIN2 01 00 +5V IRRX2 NCS0 (default) ...
Page 124
... GIOP0 pin compare GIO0AD10-GIO0AD0 with SA10-SA0 compare GIO0AD10-GIO0AD1 with SA10-SA1 compare GIO0AD10-GIO0AD2 with SA10-SA2 compare GIO0AD10-GIO0AD3 with SA10-SA3 - 122 - W83877AF 0 GIO0AD0 GIO0AD1 GIO0AD2 GIO0AD3 GIO0AD4 GIO0AD5 GIO0AD6 GIO0AD7 0 GIO0AD8 GIO0AD9 GIO0AD10 Reserved Reserved Reserved G0CADM0 G0CADM1 Publication Release Date: Dec ...
Page 125
... GIOP1 pin compare GIO1AD10-GIO1AD0 with SA10-SA0 compare GIO1AD10-GIO1AD1 with SA10-SA1 compare GIO1AD10-GIO1AD2 with SA10-SA2 compare GIO1AD10-GIO1AD3 with SA10-SA3 - 123 - W83877AF 0 GIO1AD0 GIO1AD1 GIO1AD2 GIO1AD3 GIO1AD4 GIO1AD5 GIO1AD6 GIO1AD7 0 GIO1AD8 GIO1AD9 GIO1AD10 Reserved Reserved Reserved G1CADM0 G1CADM1 Publication Release Date: Dec ...
Page 126
... GIO0AD10-0), the value of SD0 will be present on GIOP0 When (AEN = L) AND (nIOR = L) AND (SA10-0 = GIO0AD10-0), the value of GIOP0 will be present on SD0 Chip Select pin, the pin will be active at (AEN = L) AND (SA10-0 = GIO0AD10-0) OR (nIOR = L) OR (nIOW = L) - 124 - W83877AF 0 GDA0IPI GDA0OPI GCS0IOW GCS0IOR GIO0CSH GIOP0MD0 GIOP0MD1 ...
Page 127
... When the device is in Extended Function mode and EFIR is 15H, the CR15 register can be accessed through EFDR. The bit definitions are as follows: 7 GIOP1MD2-GIOP1MD0 (bit 7-bit 5): GIOP1 pin mode selection 125 - W83877AF GDA0IPI GDA0OPI GCS0IOW GCS0IOR GIO0CSH GIOP0MD0 GIOP0MD1 GIOP0MD2 Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 128
... GIOP1 functions as a Chip Select pin, and will be active when (AEN = L) AND (SA10-0 = GIO1AD10-0) AND (nIOR = L) GIOP1 functions as a Chip Select pin, and will be active when (AEN = L) AND (SA10-0 = GIO1AD10-0) AND (nIOW = L OR nIOR = L) - 126 - W83877AF GIOP1 pin Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 129
... GIOP1 functions as a data pin, and GIOP1 SD1, inverse SD1 GIOP1 GIOP1 functions as a data pin, and inverse GIOP1 SD1 GIOP1 127 - W83877AF SD1, inverse 0 HEFRAS IRIDE PNPCVS GMDRQ GOIQSEL Reserved Reserved Reserved Publication Release Date: Dec. 1996 ...
Page 130
... EFDR. The bit definitions are as follows: PNPCVS = 0 81H 00H FCH 00H 7CH 00H FDH 00H DEH 00H FEH 00H BEH 00H 23H 00H 05H 00H 43H 00H 60H 00H IRIDE = 1 IRQ_G IRQ_H IRRX2 IRTX2 - 128 - W83877AF Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 131
... When the device is in Extended Function mode and EFIR is 1EH, the CR1E register can be accessed through EFDR. Default = 81H if CR16 bit default = 00H if CR16 bit The bit definitions are as follows 129 - W83877AF DSUBLGRQ DSUALGRQ DSPRLGRQ DSFDLGRQ PRIRQOD Reserved Reserved Reserved Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 132
... When the device is in Extended Function mode and EFIR is 21H, the CR21 register can be accessed through EFDR. Default = 7CH if CR16 bit default = 00H if CR16 bit The bit definitions are as follows 130 - W83877AF 0 GMAS0 GMAS1 GMAD2 GMAD3 GMAD4 GMAD5 GMAD6 GMAD7 0 Reserved Reserved FDCAD2 FDCAD3 FDCAD4 ...
Page 133
... When the device is in Extended Function mode and EFIR is 23H, the CR23 register can be accessed through EFDR. Default = DEH if CR16 bit default = 00H if CR16 bit The bit definitions are as follows 131 - W83877AF 0 Reserved Reserved IDE0AD2 IDE0AD3 IDE0AD4 IDE0AD5 IDE0AD6 IDE0AD7 0 Reserved Reserved IDE1AD2 IDE1AD3 IDE1AD4 ...
Page 134
... When the device is in Extended Function mode and EFIR is 25H, the CR25 register can be accessed through EFDR. Default = BEH if CR16 bit default = 00H if CR16 bit The bit definitions are as follows 132 - W83877AF 0 PRTAD0 PRTAD1 PRTAD2 PRTAD3 PRTAD4 PRTAD5 PRTAD6 PRTAD7 0 Reserved URAAD1 URAAD2 URAAD3 URAAD4 ...
Page 135
... EFDR. Default = 05H if CR6 bit default = 00H if CR16 bit The bit definitions are as follows DMA selected None DMA_A DMA_B DMA_C - 133 - W83877AF 0 Reserved URBAD1 URBAD2 URBAD3 URBAD4 URBAD5 URBAD6 URBAD7 0 PRTDQS0 PRTDQS1 PRTDQS2 PRTDQS3 FDCDQS0 FDCDQS1 FDCDQS2 FDCDQS3 Publication Release Date: Dec. 1996 ...
Page 136
... IRQ resource IRQ selected None IRQ_A IRQ_B IRQ_C IRQ_D IRQ_E IRQ_F IRQ_G IRQ_H - 134 - W83877AF 0 PRTIQS0 PRTIQS1 PRTIQS2 PRTIQS3 Reserved ECPIRQx0 ECPIRQx1 ECPIRQx2 Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 137
... EFDR. This register default value The bit definitions are as follows 135 - W83877AF 0 URBIQS0 URBIQS1 URBIQS2 URBIQS3 URAIQS0 URAIQS1 URAIQS2 URAIQS3 0 IQNIQS0 IQNIQS1 IQNIQS2 IQNIQS3 FDCIQS0 FDCIQS1 FDCIQS2 FDCIQS3 IRRXDRQSL0 IRRXDRQSL1 IRRXDRQSL2 IRRXDRQSL3 IRTXDRQSL0 ...
Page 138
... PIN2FUN1 PIN2FUN0 The bit definitions are as follows Pin 1 0 IRQ_G 1 nRESIDE 0 DRQ_D 1 IRSL2 Pin 2 0 nCS 1 nDACK_D 0 IRSL1 1 IRSL2 - 136 - W83877AF 0 PIN93FUN0 PIN93FUN1 PIN3FUN0 PIN3FUN1 PIN2FUN0 PIN2FUN1 PIN1FUN0 PIN1FUN1 Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 139
... Pin 93 0 IRQIN 1 DRQ_D 0 IRSL2 1 IRRXH/IRSL0 . The bit definitions are as follows PIN91FUN(CR2C. 137 - W83877AF 0 Reserved EMULFUN CLKINSEL ENBNKSEL APEDCRC PIN91FUN0 PIN91FUN1 PIN91FUN2 Pin 91 0 IRQ_H 1 nDBENL 0 IRSL2 1 IRRXH/IRSL0 0 DACK_D Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 140
... These two bits combining with data rate selection bits in Data Rate Register select the operational data rate for FDD A as follows The bit definitions are as follows 138 - W83877AF , the CR2D register can be accessed DRTA0 DRTA1 DIS_PRECOMP0 DRTB0 DRTB1 DIS_PRECOMP1 Reserved Reserved Publication Release Date: Dec. 1996 Preliminary Version 0.52 ...
Page 141
... Data Rate DRATE1 DRATE0 139 - W83877AF Operational Data Rate MFM FM 1M --- 500K 250K 300K 150K 250K 125K 1M --- 500K 250K 500K 250K 250K 125K 1M --- 500K 250K 2M --- 250K 125K Publication Release Date: Dec. 1996 ...
Page 142
... URBAD4 FDCDQS2 FDCDQS1 FDCDQS0 ECPIRQx1 ECPIRQx0 0 URAIQS2 URAIQS1 URAIQS0 FDCIQS2 FDCIQS1 FDCIQS0 IRTXDSL2 IRTXDSL1 IRTXDSL0 PIN1FUN0 PIN2FUN1 PIN2FUN0 PIN91FN1 PIN91FN0 APEDCRC - 140 - W83877AF PRTMODS1 PRTMODS0 OSCS1 RA5 RA4 RA3 0 0 SUAMIDI PRTTRI GMTRI URATRI ECPFTHR3 ECPFTHR2 ECPFTHR1 FDCPWD IDEPWD ...
Page 143
... 2 LIH I LIL LIH I LIL LIH I LIL - 141 - W83877AF UNIT V +0 MAX. UNI CONDITIONS 0 ...
Page 144
... LIH I -10 LIL V 0.3xV IL V 0.7xV +10 LIH I -10 LIL V 1.3 1 3.. +10 LIH I -10 LIL - 142 - W83877AF UNIT CONDITIONS ...
Page 145
... MCY 260/430 AA /510 143 - W83877AF TYP. MAX. (NOTE 360/570 /675 0 0 360/570 /675 Publication Release Date: Sep. 1996 Preliminary Version 0.50 UNIT ...
Page 146
... SYM. TEST CONDITIONS T MRW T 135/220 TC T 1.8/3/3. RST T 0.5/0.9 IDX T 1.0/1.6 DST T 24/40/48 STD T 6.8/11.5 STP T Note 100/185 WDD T 100/138 WPC - 144 - W83877AF MIN. TYP. MAX. (NOTE 1) 6/12 /20/24 /260 5 /1.0 /2.0 7/11.7 7.2/11.9 /13.8 /14 /14.2 Note 2 Note 2 125/210 150/235 /225 /250 /275 125/210 150/235 /225 /250 /275 SYMBOL MAX ...
Page 147
... Loading IAD T 100 pF Loading IID N 100 pF Loading SYM. TEST MIN. CONDITIONS tx1 tx2 tx3 50 tx4 0 tx5 tx6 tx7 tx8 Publication Release Date: Sep. 1996 - 145 - W83877AF MIN. MAX. UNIT 9/16 Baud Rate 1 S 1/16 8/16 Baud Rate 175 nS 9/16 16/16 Baud Rate 1/2 Baud Rate 250 ...
Page 148
... Publication Release Date: Sep. 1996 - 146 - W83877AF MAX. UNIT 100 105 nS 300 nS 105 nS MAX. UNIT 160 185 nS 190 ...
Page 149
... Publication Release Date: Sep. 1996 - 147 - W83877AF MAX. UNIT 195 nS 180 MAX. UNIT 160 185 nS 185 ...
Page 150
... SYMBOL MIN Publication Release Date: Sep. 1996 - 148 - W83877AF MAX. UNIT MAX. UNIT 500 nS MAX. UNIT 180 nS 180 nS nS 200 nS nS 180 nS MAX ...
Page 151
... IOW or IOR TMW (IOW) TMR (IOR) TRA TRR TDH TDF TR TWA TWW TWD TDW TWI DIR TMCY TAA STEP - 149 - W83877AF Write Date WD TWDD Index INDEX TIDX TIDX Terminal Count TC TTC Reset RESET TRST Drive Seek operation TSTP TDST TSTD TSC Publication Release Date: Sep ...
Page 152
... IDE SA<0:9> IOR IOW DATA READ IDED7 D7 DATA WRITE IDED7 D7 CS0 CS1 IOCS16 DBENL DBENH 150 - W83877AF Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 153
... SERIAL OUT (SOUT) THRS IRQ3 or IRQ4 THR IOW (WRITE THR) IOR (READ TIR) Receiver Timing STAR DATA BITS (5-8) PARITY Transmitter Timing STAR DATA (5-8) PARITY THR TSI - 151 - W83877AF STOP TSINT TRINT STAR STOP (1-2) TSTI TIR Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 154
... Printer Interrupt Timing ¢x ¢x ¢x ¢ ¢x ¡÷ ¡ö ¢x TLAD ¢x ¢x ¢x ¢x ¢ ¢x ¢x - 152 - W83877AF ¢x ¢x ¢x ¡÷ ¡ö TMWO ¢x ¢ ¢x ¢x ¢x ¢x ¢ ¡ö TSIM ¢x ¢x ¢ ...
Page 155
... Parallel Port 10.4.1 Parallel Port Timing IOW INIT, STROBE AUTOFD, SLCTIN PD<0:7> ACK IRQ (SPP) IRQ (EPP or ECP) nFAULT (ECP) ERROR (ECP) IRQ 153 - W83877AF Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 156
... EPP Data or Address Read Cycle (EPP Version 1.9) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 PD<0:7> t22 t23 t24 ADDRSTB DATASTB WAIT t18 t17 t21 t25 t27 t26 - 154 - W83877AF t15 t19 t20 t28 Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 157
... EPP Data or Address Write Cycle (EPP Version 1.9) A10-A0 SD<0:7> t1 IOW IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT t22 PBDIR t10 t11 t13 t15 t16 t17 t18 t19 t20 - 155 - W83877AF t12 t14 t21 Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 158
... EPP Data or Address Read Cycle (EPP Version 1.7) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 t17 PD<0:7> t22 t23 ADDRSTB t24 DATASTB WAIT t18 t21 t25 t26 t27 - 156 - W83877AF t15 t19 t20 t28 Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 159
... IOW IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT 10.4.6 Parallel Port FIFO Timing PD<0:7> nSTROBE BUSY t10 t11 t13 t15 t16 t17 t18 t19 t20 t1 t2 >| t6 >| - 157 - W83877AF t22 t22 t4 >| t3 >| t5 > >| Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 160
... ECP Parallel Port Forward Timing nAUTOFD PD<0:7> nSTROBE BUSY 10.4.8 ECP Parallel Port Reverse Timing PD<0:7> nACK nAUTOFD 158 - W83877AF Publication Release Date: Sep. 1996 Preliminary Version 0.50 ...
Page 161
... Extension Adapter Mode Command Cycle IOR IOW XRD XWR tx1 SA<0:2> XA<0:2> tx2 XD<0:7> 10.4.10 Extension Adapter Mode Interrupt Cycle XIRQ IRQ7 tx3 tx5 Publication Release Date: Sep. 1996 - 159 - W83877AF tx4 Preliminary Version 0.50 ...
Page 162
... RDD2/PD3 5 17 STEP2/SLIN 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram tx6 tx7 tx8 JP13 - 160 - W83877AF JP 13A DCH2 34 33 HEAD2 32 31 RDD2 30 29 WP2 28 27 TRK02 26 25 WE2 24 23 WD2 22 21 STEP2 20 ...
Page 163
... DCH2/PD4 18 RDD2/PD3 5 STEP2/SLIN 17 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension 2FDD Connection Diagram JP13 - 161 - W83877AF JP 13A DCH2 34 33 HEAD2 32 31 RDD2 30 29 WP2 28 27 TRK02 26 25 WE2 24 23 WD2 22 21 STEP2 20 19 DIR2 ...
Page 164
... Joystick 15-pin connector 74LS139 7407(2) G1 1Y0 A1 1Y1 B1 1Y2 1Y3 2Y0 2Y1 G2 2Y2 2Y3 A2 B2 Publication Release Date: Sep. 1996 - 162 - W83877AF Joystick Printer Port 15-pin 25-pin Connector Connector VDD 1,8,9,15 1,14,15,16,17 GND 4,5,12 18~ ...
Page 165
... ORDERING INFORMATION Part No. W83877AF 100-pin QFP W83877AD 100-pin TQFP 13.0 PACKAGE DIMENSIONS W83877AF (100-pin QFP 100 See Detail F Seating Plane Package Detail F - 163 - W83877AF Dimension in inches Dimension in mm Symbol Min. Nom. Max. ...
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... Detail F Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 - 164 - W83877AF Dimension in inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max 0.05 0.10 0.002 0.004 0.006 ...
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... Differences pin assignment between W83877AF and W83877F F B eature rief W83877F: W83777F + Plug and Play + IR W83877AF: W83877F + Plug and Play + FIR D escription Illustrates the pins that have different functionality on the W83877F and the W83877AF. The following table lists the pins that differ. Pin W83877F 1 nRESIDE/IRQ_G 2 nCS 3 ...
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... W83877AF Application Note 2 June 11, 1996 F B eature rief W83877AF: W83877F + FIR 4Mbps + MIR 1.15Mbps + Consumer IR D escription 1. Illustrates the pins that have different functinality on the 877 and 877A. Pin W83877F 1 IRQ_G/nRESIDE 2 nCS 3 PDCIN 38 SOUTA/IRIDE 91 nIDBEN/IRQ_H 93 IRQIN 2. W83877AF Power-on Setting Pin No. Pin Name Function Name Default ...
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Bit 5 : RXW4C SIR of UART B will receving data immediately when tranmitting changing to receving SIR of UART B will wait for 4 characters time when transmitting changing to receving. CR0C(Default 0x28) Bit 7-5, ...
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Bit 3-2: PIN3FUN PIN3FUN(CR2B. Bit 1-0: PIN93FUN PIN93FUN(CR2B. CR2C(Default 10H) Bit 7-5 : PIN91FUN PIN91FUN PIN91FUN (CR2C.7) (CR2C. Note: The IRSL0/IRRXH selection ...
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Drive Rate Table DRTA1 DIS_PRECOMP0 (bit 2): This bit controls if precompensation is enabled for FDD A. =0 enable precompensation for FDD A =1 disable precompensation for FDD ...