IDT7133SA35PFI Integrated Device Technology, Inc., IDT7133SA35PFI Datasheet
IDT7133SA35PFI
Related parts for IDT7133SA35PFI
IDT7133SA35PFI Summary of contents
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... CE L NOTE: 1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor. IDT7143 (SLAVE): BUSY is input. ©2000 Integrated Device Technology, Inc. HIGH SPEED DUAL-PORT SRAM BUSY output flag on IDT7133; BUSY input on IDT7143 Fully asynchronous operation from either port Battery backup operation–2V data retention TTL-compatible ...
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IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and I/O pins that permit independent, asynchronous ...
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IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM 10L R/W L LLB (1) R/W ...
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IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM Symbol Rating Commercial & Industrial (2) V Terminal Voltage -0.5 to +7.0 TERM with Respect to GND T Temperature -55 to +125 BIAS Under Bias T Storage -65 to +150 STG Temperature ...
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IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM Symbol Parameter Dynamic Operating CC , Outputs Disabled IL Current (3) (Both Ports Active MAX CE and CE I Standby Current SB1 L R (Both ...
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IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM Symbol Parameter V V for Data Retention Data Retention Current CCDR (3) t Chip Deselect to Data Retention Time CDR (3) t Operation Recovery Time R NOTES: 1. Vcc ...
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IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Enable Access Time ACE t Output Enable Access Time AOE t Output Hold from Address Change ...
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IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE ADDRESS DATA PREVIOUS DATA VALID OUT BUSY OUT TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE CE OE DATA OUT t I ...
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IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM Symbol Parameter WRITE CYCLE (3) t Write Cycle Time WC t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW t Address Set-up Time AS t Write Pulse Width WP ...
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IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM Symbol BUSY TIMING (For MASTER 71V33) BUSY Access Time from Address t BAA BUSY Disable Time from Address t BDA BUSY Access Time from Chip Enable t BAC BUSY Disable Time from ...
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IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM ADDRESS ( (9) R DATA OUT DATA IN CE ADDRESS CE ( (9) R/W DATA IN NOTES must be HIGH ...
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IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM ADDR "A" R/W "A" DATA IN"A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins ...
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IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM BUSY ADDR "A" AND "B" CE "A" t (2) APS CE "B" BUSY "B" t ADDR "A" ADDRESSES MATCH t APS ADDR "B" BUSY "B" NOTES: 1. All timing is the same ...
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IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM The IDT7133/43 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7133/43 has an automatic power down ...
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IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM LEFT OR RIGHT PORT CE OE R/W R ...
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... Page 4 Increased storage temperature parameters Clarified T A Page 5 DC Electrical parameters–changed wording from "open" to "disabled" CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 The IDT logo is a registered trademark of Integrated Device Technology, Inc. Military, Industrial and Commercial Temperature Ranges X X Process/ Temperature Range ...