IDT79R3051-25J Integrated Device Technology, Inc., IDT79R3051-25J Datasheet
IDT79R3051-25J
Available stocks
Related parts for IDT79R3051-25J
IDT79R3051-25J Summary of contents
Page 1
... Bus Interface Unit 4-deep 4-deep DMA Write Read Arbiter Control Buffer Buffer Address/ DMA Rd/Wr Data Ctrl Ctrl Figure 1. R3051 Family Block Diagram 5.3 IDT79R3051 , 79R3051E IDT79R3052 , 79R3052E BrCond(3:0) Integer CPU Core (32 x 32) ALU Shifter PC Control 32 BIU SysClk SEPTEMBER 1995 2874 drw 01 DSC-3000/5 1 ...
Page 2
... The CPU core contains a five stage pipeline and 32 orthogonal 32-bit registers. The IDT79R3051 family imple- ments the MIPS ISA. In fact, the execution engine of the IDT79R3051 family is the same as the execution engine of the IDT79R3000A (and IDT79R3001). Thus the IDT79R3051 family is binary-compatible with those CPU engines. ...
Page 3
... Figure 3. Virtual-to-Physical Mapping of Extended Architecture Versions The base versions of the architecture (the IDT79R3051 and IDT79R3052) remove the TLB and institute a fixed address mapping for the various segments of the virtual address space. The base processors support distinct kernel and user mode operation without requiring page management software, leading to a simpler software model ...
Page 4
... PALs can be used to control the various data path elements, and to control the handshake between the memory devices and the CPU. DEVELOPMENT SUPPORT The IDT79R3051 family is supported by a rich set of development tools, ranging from system simulation tools through prom monitor support, logic analysis tools, and sub- system modules. ...
Page 5
... Microsoft TrueImage Page Description Language on top of PeerlessPage Ad- vanced Printer Controller BIOS. • Adobe PostScript Page Description Language, ported to the R3000 instruction set, runs on the IDT79R3051 family. • The IDT Prom Monitor, which implements a full prom monitor (diagnostics, remote debug support, peek/poke, etc.). ...
Page 6
... IDT79R3051/79R3052 INTEGRATED RISControllers Clk2xIn I/O Controller PROM I/O IDT79R3051 Family RISController Address/ Data Control R3051 Family Local Bus DRAM Controller I/O DRAM IDT73720 Bus Exchanger Figure 6. R3051 Family Chip Set Based System 5.3 COMMERCIAL TEMPERATURE RANGE DRAM (2) 2874 drw 06 6 ...
Page 7
... IDT79R3051/79R3052 INTEGRATED RISControllers System Architecture Evaluation Cache-R305x Benchmarks Evaluation Board Laser Printer System System Development Phase Software SABLE Simulator DBG Debugger PIXIE Profiler MIPS Compiler Suite Stand-Alone Libraries Floating Point Library Cross Development Tools Adobe PostScript PDL MicroSoft TrueImage PDL Ada ...
Page 8
... IDT79R3051 family, allows operation at speeds to 25MHz. However, at higher speeds, additional thermal care must be taken. For this reason, the IDT79R3051 family is also available in the MQUAD package (the "MJ" package), which is an all- aluminum package with the die attached to a normal copper lead-frame, mounted to the aluminum casing ...
Page 9
... IDT79R3051/79R3052 INTEGRATED RISControllers PIN DESCRIPTION PIN NAME I/O A/D(31:0) I/O Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction in one phase, and which is used to transmit data between the CPU and external memory resources during the rest of the transfer. Bus transactions on this bus are logically separated into two phases: during the first phase, information about the transfer is presented to the memory system to be captured using the ALE output ...
Page 10
... IDT79R3051/79R3052 INTEGRATED RISControllers PIN DESCRIPTION (Continued): PIN NAME I/O Burst/ O Burst Transfer/Write Near: On read transactions, the WrNear is requesting a block of four contiguous words from memory. This signal is asserted only in read cycles due to cache misses asserted for all I-Cache miss read cycles, and for D-Cache miss read cycles if selected at device reset time ...
Page 11
... IDT79R3051/79R3052 INTEGRATED RISControllers ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with Respect to GND T Operating Case C Temperature T Temperature BIAS Under Bias T Storage STG Temperature V Input Voltage IN NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only ...
Page 12
... IDT79R3051/79R3052 INTEGRATED RISControllers AC ELECTRICAL CHARACTERISTICS Symbol Signals BusReq Ack BusError RdCEn , t1a A/D BusReq Ack BusError RdCEn , t2a A A/D, Addr, Diag, ALE, Burst WrNear Rd DataEn / , , Wr t4 A/D, Addr, Diag, ALE, Burst WrNear Rd DataEn / , , BusGnt t5 BusGnt Burst WrNear A/D t8 ALE t9 ALE t10 A/D DataEn ...
Page 13
... IDT79R3051/79R3052 INTEGRATED RISControllers PIN CONFIGURATIONS Clk2xIn Rsvd(4) Rsvd(3) Rsvd(2) Rsvd(1) Rsvd(0) Int( Int(4) Int(3) SInt(2) SInt(1) SInt(0) SBrCond(3) SBrCond(2) BrCond( NOTE: Reserved Pins must not be connected 84-Pin PLCC/MQUAD Top View 5.3 COMMERCIAL TEMPERATURE RANGE ...
Page 14
... IDT79R3051/79R3052 INTEGRATED RISControllers t 22 Clk2xIn t 20 SysClk V CC ClkIn Reset SysClk Reset SysClk Reset SInt(n), Int( sys Figure 8. R3051 Family Clocking Figure 9. Power-On Reset Sequence t 24 Figure 10. Warm Reset Sequence Figure 11. Mode Selection and Negation of Reset 5.3 COMMERCIAL TEMPERATURE RANGE ...
Page 15
... IDT79R3051/79R3052 INTEGRATED RISControllers Run/ Fixup/ Stall Stall PhiClk SysClk Addr A/D(31: Addr(3: ALE t 9 DataEn t 7 Burst RdCEn ACK Diag(1) Cached? Diag(0) I/D Start Turn Read Bus Stall Stall t 18 Word Address Miss Address(3) Miss Address(2) ...
Page 16
... IDT79R3051/79R3052 INTEGRATED RISControllers Run/ Fixup/ Stall Stall Stall PhiClk SysClk Addr BE A/D(31: Addr(3: ALE DataEn Burst RdCEn ACK Cached? Diag(1) I/D Diag(0) Start Turn Read Bus Refill/ Stream/ Fixup Stall Word ...
Page 17
... IDT79R3051/79R3052 INTEGRATED RISControllers Stall PhiClk SysClk Rd A/D(31:0) '00' Addr(3:2) ALE DataEn Burst t 1 RdCEn ACK RdCEn Stall t 1a Word Sample RdCEn Data Figure 14 (a). Start of Throttled Quad Read 5.3 COMMERCIAL TEMPERATURE RANGE Stall t 1a Word 1 '01 Sample ...
Page 18
... IDT79R3051/79R3052 INTEGRATED RISControllers PhiClk SysClk Rd A/D(31:0) Addr(3:2) ALE DataEn Burst RdCEn t 1 ACK t 2 ACK Refill/ Stream/ Fixup Stall Word Word '01' '11 RdCEn Sample Data Figure 14 (b). End of Throttled Quad Read 5.3 COMMERCIAL TEMPERATURE RANGE Refill/ ...
Page 19
... IDT79R3051/79R3052 INTEGRATED RISControllers SysClk Addr BE A/D(31: Addr(3: ALE WrNear ACK Start Data Write Out SysClk BusReq t 1 BusGnt A/D(31:0) Addr(3:2) Diag(1: ALE Burst/ WrNear Figure 16. Request and Relinquish of R3051 Family Bus to External Master t 19 Data ...
Page 20
... IDT79R3051/79R3052 INTEGRATED RISControllers SysClk BusReq t 1 BusGnt A/D(31:0) Addr(3:2) Diag(1: ALE Burst/ WrNear Figure 17. R3051 Family Regaining Bus Mastership 5.3 COMMERCIAL TEMPERATURE RANGE 2874 drw 21 20 ...
Page 21
... IDT79R3051/79R3052 INTEGRATED RISControllers Phi SysClk SInt(n) Phi SysClk Int(n) Phi SysClk SBrCond(n) Phi SysClk BrCond( Figure 18. Synchronized Interrupt Input Timing t 30 Figure 19. Direct Interrupt Input Timing Run Cycle Figure 20. Synchronized Branch Condition Input Timing Run Cycle Figure 21 ...
Page 22
... IDT79R3051/79R3052 INTEGRATED RISControllers 84 LEAD PLCC/MQUAD (7) (SQUARE .045 NOTES: 1. All dimensions are in inches, unless otherwise noted. 2. BSC—Basic lead Spacing between Centers & not include mold flash or protutions. 4. Formed leads shall be planar with respect to one another and within .004” at the seating plane. ...
Page 23
... IDT79R3051/79R3052 INTEGRATED RISControllers ORDERING INFORMATION XXXXX - XX X IDT Device Type Speed Package VALID COMBINATIONS IDT 79R3051 - 20, 25 79R3051E - 20, 25 79R3052 - 20, 25 79R3052E - 20, 25 79R3051 - 33, 40 79R3051E - 33, 40 79R3052 - 33, 40 79R3052E - 33 Process/ Temp. Range Blank 'J' 'MJ' '20' '25' '33' '40' 79R3051 79R3051E 79R3052 ...