IDT79R3052-40MJ Integrated Device Technology, Inc., IDT79R3052-40MJ Datasheet
IDT79R3052-40MJ
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IDT79R3052-40MJ Summary of contents
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... Bus Interface Unit 4-deep 4-deep DMA Write Read Arbiter Control Buffer Buffer Address/ DMA Rd/Wr Data Ctrl Ctrl Figure 1. R3051 Family Block Diagram 5.3 IDT79R3051 , 79R3051E IDT79R3052 , 79R3052E BrCond(3:0) Integer CPU Core (32 x 32) ALU Shifter PC Control 32 BIU SysClk SEPTEMBER 1995 2874 drw 01 DSC-3000/5 1 ...
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... Translation Lookaside Buffer (TLB). This is the same MMU incorporated into the IDT79R3000A and IDT79R3001. • The IDT79R3052 also incorporates 8kB of Instruction Cache. However, the MMU is a much simpler subset of the capabili- ties of the enhanced versions of the architecture, and in fact does not use a TLB. • ...
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... Figure 3. Virtual-to-Physical Mapping of Extended Architecture Versions The base versions of the architecture (the IDT79R3051 and IDT79R3052) remove the TLB and institute a fixed address mapping for the various segments of the virtual address space. The base processors support distinct kernel and user mode operation without requiring page management software, leading to a simpler software model ...
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... The current family includes two different instruction cache sizes: the IDT79R3051 family (the IDT79R3051 and IDT79R3051E) feature 4KB of instruction cache, and the IDT79R3052 and IDT79R3052E each incorporate 8KB of Instruction Cache. For all four devices, the instruction cache is organized as a line size of 16 bytes (four words). This ...
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IDT79R3051/79R3052 INTEGRATED RISControllers • Sable, an instruction set simulator. • Optimizing compilers from MIPS, the acknowledged leader in optimizing compiler technology. • IDT Cross development tools, available in a variety of development environments. • The high-performance IDT floating point library ...
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IDT79R3051/79R3052 INTEGRATED RISControllers Clk2xIn I/O Controller PROM I/O IDT79R3051 Family RISController Address/ Data Control R3051 Family Local Bus DRAM Controller I/O DRAM IDT73720 Bus Exchanger Figure 6. R3051 Family Chip Set Based System 5.3 COMMERCIAL TEMPERATURE RANGE DRAM (2) 2874 ...
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IDT79R3051/79R3052 INTEGRATED RISControllers System Architecture Evaluation Cache-R305x Benchmarks Evaluation Board Laser Printer System System Development Phase Software SABLE Simulator DBG Debugger PIXIE Profiler MIPS Compiler Suite Stand-Alone Libraries Floating Point Library Cross Development Tools Adobe PostScript PDL MicroSoft TrueImage PDL ...
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IDT79R3051/79R3052 INTEGRATED RISControllers PERFORMANCE OVERVIEW The IDT79R3051 family achieves a very high level of performance. This performance is based on: • An efficient execution engine. The CPU performs ALU operations and store operations at a single cycle rate, and has ...
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IDT79R3051/79R3052 INTEGRATED RISControllers PIN DESCRIPTION PIN NAME I/O A/D(31:0) I/O Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction in one phase, and which is used to transmit data between the CPU and external ...
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IDT79R3051/79R3052 INTEGRATED RISControllers PIN DESCRIPTION (Continued): PIN NAME I/O Burst/ O Burst Transfer/Write Near: On read transactions, the WrNear is requesting a block of four contiguous words from memory. This signal is asserted only in read cycles due to cache ...
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IDT79R3051/79R3052 INTEGRATED RISControllers ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with Respect to GND T Operating Case C Temperature T Temperature BIAS Under Bias T Storage STG Temperature V Input Voltage IN NOTES: 1. Stresses greater than those ...
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IDT79R3051/79R3052 INTEGRATED RISControllers AC ELECTRICAL CHARACTERISTICS Symbol Signals BusReq Ack BusError RdCEn , t1a A/D BusReq Ack BusError RdCEn , t2a A A/D, Addr, Diag, ALE, Burst WrNear Rd DataEn ...
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IDT79R3051/79R3052 INTEGRATED RISControllers PIN CONFIGURATIONS Clk2xIn Rsvd(4) Rsvd(3) Rsvd(2) Rsvd(1) Rsvd(0) Int( Int(4) Int(3) SInt(2) SInt(1) SInt(0) SBrCond(3) SBrCond(2) BrCond( NOTE: Reserved Pins must not be ...
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IDT79R3051/79R3052 INTEGRATED RISControllers t 22 Clk2xIn t 20 SysClk V CC ClkIn Reset SysClk Reset SysClk Reset SInt(n), Int( sys Figure 8. R3051 Family Clocking Figure 9. Power-On Reset Sequence t 24 Figure 10. Warm ...
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IDT79R3051/79R3052 INTEGRATED RISControllers Run/ Fixup/ Stall Stall PhiClk SysClk Addr A/D(31: Addr(3: ALE t 9 DataEn t 7 Burst RdCEn ACK Diag(1) Cached? Diag(0) I/D ...
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IDT79R3051/79R3052 INTEGRATED RISControllers Run/ Fixup/ Stall Stall Stall PhiClk SysClk Addr BE A/D(31: Addr(3: ALE DataEn Burst RdCEn ACK ...
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IDT79R3051/79R3052 INTEGRATED RISControllers Stall PhiClk SysClk Rd A/D(31:0) '00' Addr(3:2) ALE DataEn Burst t 1 RdCEn ACK RdCEn Stall t 1a Word Sample RdCEn Data Figure 14 (a). Start ...
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IDT79R3051/79R3052 INTEGRATED RISControllers PhiClk SysClk Rd A/D(31:0) Addr(3:2) ALE DataEn Burst RdCEn t 1 ACK t 2 ACK Refill/ Stream/ Fixup Stall Word Word '01' '11 ...
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IDT79R3051/79R3052 INTEGRATED RISControllers SysClk Addr BE A/D(31: Addr(3: ALE WrNear ACK Start Data Write Out SysClk BusReq t 1 BusGnt A/D(31:0) Addr(3:2) Diag(1: ...
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IDT79R3051/79R3052 INTEGRATED RISControllers SysClk BusReq t 1 BusGnt A/D(31:0) Addr(3:2) Diag(1: ALE Burst/ WrNear Figure 17. R3051 Family Regaining Bus Mastership 5.3 COMMERCIAL TEMPERATURE RANGE 2874 drw 21 20 ...
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IDT79R3051/79R3052 INTEGRATED RISControllers Phi SysClk SInt(n) Phi SysClk Int(n) Phi SysClk SBrCond(n) Phi SysClk BrCond( Figure 18. Synchronized Interrupt Input Timing t 30 Figure 19. Direct Interrupt Input Timing Run Cycle Figure ...
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IDT79R3051/79R3052 INTEGRATED RISControllers 84 LEAD PLCC/MQUAD (7) (SQUARE .045 NOTES: 1. All dimensions are in inches, unless otherwise noted. 2. BSC—Basic lead Spacing between Centers & not include mold flash or protutions. 4. Formed ...
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IDT79R3051/79R3052 INTEGRATED RISControllers ORDERING INFORMATION XXXXX - XX X IDT Device Type Speed Package VALID COMBINATIONS IDT 79R3051 - 20, 25 79R3051E - 20, 25 79R3052 - 20, 25 79R3052E - 20, 25 79R3051 - 33, 40 79R3051E - 33, ...