W9816G6CH-7 Winbond, W9816G6CH-7 Datasheet
W9816G6CH-7
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W9816G6CH-7 Summary of contents
Page 1
... Self Refresh Command ................................................................................................ 10 7.17 Power Down Mode ....................................................................................................... 11 7.18 No Operation Command............................................................................................... 11 7.19 Deselect Command ...................................................................................................... 11 7.20 Clock Suspend Mode.................................................................................................... 11 8. TABLE OF OPERATING MODES ............................................................................................ 12 9. ABSOLUTE MAXIMUM RATINGS ........................................................................................... 13 10. RECOMMENDED DC OPERATING CONDITIONS................................................................. 13 11. CAPACITANCE......................................................................................................................... 13 12. DC CHARACTERISTICS.......................................................................................................... 14 512K 2 BANKS Publication Release Date: June 10, 2005 - 1 - W9816G6CH 16 BITS SDRAM Revision A0 ...
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... Autoprecharge Timing ................................................................................................. 36 14.21 Timing Chart of Write-to-Read Cycle .......................................................................... 37 14.22 Timing Chart of Burst Stop Cycle................................................................................ 37 14.23 Timing Chart of Burst Stop Cycle (Prechare Command) ............................................ 38 14.24 CKE/DQM Input Timing............................................................................................... 39 14.25 CKE/DQM Input Timing............................................................................................... 40 14.26 Self Refresh/Power Down Mode Exit Timing .............................................................. 41 15. PACKAGE DIMENSIONS ......................................................................................................... 42 15.1 50L-TSOP (II) 400 mill .................................................................................................. 42 16. REVISION HISTORY ................................................................................................................ 43 W9816G6CH - 2 - ...
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... Byte data controlled by UDQM and LDQM Auto-precharge and controlled precharge 4K refresh cycles/64 mS Interface: LVTTL Packaged in 50-pin, 400 mil TSOP II, using PB free with RoHS compliant. 3. PART NUMBER INFORMATION PART NUMBER W9816G6CH-5 W9816G6CH-6 W9816G6CH-7 SPEED (CL=3) SELF REFRESH CURRENT (MAX.) 200MHz 166MHz 143MHz - 3 - W9816G6CH m process technology, ...
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... CAS 17 34 RAS A10 W9816G6CH V SS DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 UDQM CLK CKE ...
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... Separated power from V for I/O buffer improve noise immunity. Ground for I/O Separated ground from V buffer to improve noise immunity. No connection. (NC pin should be connected to GND No Connection or floating W9816G6CH DESCRIPTION , and define the operation CAS WE , used for output buffers used for output buffers SS Publication Release Date: June 10, 2005 ...
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... COUNTER COLUMN DECODER CELL ARRAY D BANK # SENSE AMPLIFIER DATA CONTROL CIRCUIT COLUMN DECODER CELL ARRAY D E BANK # SENSE AMPLIFIER Note: The cell array configuration is 2048 * 256 * W9816G6CH DQ0 DQ BUFFER DQ15 LDQM UDQM ...
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... Commands can also be issued to the same bank or between active banks on every clock cycle. and V Q pins must be ramp up simultaneously to the CC CC supplies. After power up, an initial pause of 200 The maximum time that each bank can be held active is RRD RCD Publication Release Date: June 10, 2005 - 7 - W9816G6CH has RSC ). RC delay. WE pin voltage level Revision A0 ...
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... A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored. W9816G6CH - 8 - ...
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... (disturb addresses are A0 and A1) No address carry from (disturb addresses are A0, A1 and A2) No address carry from ACCESS ADDRESS W9816G6CH BURST LENGTH BUST LENGTH Publication Release Date: June 10, 2005 ...
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... Auto-Refresh cycles should be completed just prior to entering and just after exiting the Self-Refresh mode. ) has been satisfied. Issue of Auto-Precharge command is RP and When using the Auto-precharge Command, the interval W9816G6CH . The bank WR are satisfied. This is referred ...
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... While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one-clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. W9816G6CH . The input buffers need (min (min) ...
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... W9816G6CH A9- CAS CS RAS ...
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... STG T 260 SOLDER OUT SYM. MIN. TYP. V 3.0 3 3 SYM Publication Release Date: June 10, 2005 - 13 - W9816G6CH UNIT NOTES °C 1 °C 1 ° MAX. UNIT NOTES MIN. MAX. ...
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... CC3 IH CKE = CC3P (Power Down mode min CC4 (t = min CC5 Standrad I CC6 SYM. I I( W9816G6CH - UNIT MAX. MAX 120 110 100 60 55 ...
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... SB t 0 1.5 1 0.7 0 1.5 1 0.7 0 1.5 1.5 CKS t 0.7 0.7 CKH t 1.5 1.5 CMS t 0.7 0.7 CMH t 64 REF RSC - 15 - W9816G6CH -6 -7 UNIT NOTES MAX. MIN. MAX 100000 45 100000 20 1 tCK tCK 2 1000 10 1000 nS 1000 7 1000 2 2 5.5 5 2 0.5 1 1.5 1 1 ...
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... Input Reference Level output 8. Transition times are measured between VIH and VIL. 9. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. 1 ohms AC TEST LOAD - 16 - W9816G6CH CONDITIONS 1.4V/1.4V See diagram below 2.4V/0. 1.4V 50 ohms 30pF ...
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... IL CS RAS CAS WE A0-A10 CKS CKH CKE t t CMS CMH t t CMS CMH t t CMS CMH t t CMS CMH CKS CKH CKS - 17 - W9816G6CH CMH CMS t CKH Publication Release Date: June 10, 2005 Revision A0 ...
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... Read Tming CLK CS RAS CAS WE A0-A10 BA DQ Read Command Read CAS Latency Valid Data-Out - 18 - W9816G6CH Valid Data-Out Burst Length ...
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... Valid Valid Data-Out Data-Out CKH CKS CKH CKS Valid Data-Out - 19 - W9816G6CH Valid Valid Data-in Data- Valid Valid Data-in Data- ...
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... A1 Burst Length A2 A3 Addressing Mode A4 A5 CAS Latency "0" (Test Mode) A8 "0" Reserved Write Mode "0" A10 A0 Reserved BA "0" W9816G6CH t RSC Burst Length Sequential ...
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... RAS t t RCD RCD RBb RAc RBb CBx RAc t AC bx1 aw0 aw2 aw3 bx0 aw1 t t RRD Precharge Active Active Read Precharge - 21 - W9816G6CH RAS RAS t RCD RBd CAy RBd CBz t AC ...
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... RAS t RCD t RCD RAc CBx RAc aw0 aw1 aw2 aw3 bx0 bx1 t RRD AP* Active Read - 22 - W9816G6CH RAS RAS t RCD RAe RBd CBz CAy RAe RBd ...
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... RAS RAS t RCD RBb RBb CBy ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 t RRD Precharge Active Read - 23 - W9816G6CH RAS RCD RAc RAc CAz t AC by1 by4 by5 by6 by7 CZ0 ...
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... RAS RP t RCD RBb RBb CBy ax3 ax4 ax0 ax2 ax5 ax6 ax7 ax1 t RRD AP* Read Active * AP is the internal precharge start timing - 24 - W9816G6CH RAS t t RAS RP t RCD RAc CAz RAc t CAC t ...
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... RAS t RCD RBb RBb CBy ax4 ax5 ax6 ax7 by0 by1 by2 by3 t RRD Precharge Active Write - 25 - W9816G6CH RAS RCD RAc RAc CAz by4 by5 by6 by7 CZ0 CZ1 Active Write Precharge ...
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... RAS t RCD RBb RBb CBy ax4 ax5 ax6 ax7 by0 by1 by2 by3 t RRD Precharge Active Write - 26 - W9816G6CH RAS RCD RAc RAc CAz by4 by5 by6 by7 CZ0 CZ1 Active Write Precharge ...
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... RAS t RAS CAm CBx CAy bx0 bx1 Ay0 Ay1 Ay2 Read Read Read * AP is the internal precharge start timing - 27 - W9816G6CH CBz am0 am1 am2 bz0 bz1 bz2 bz3 Precharge ...
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... RAa CAx A0-A9 DQM CKE Bank #0 Active Read Bank # RAS CAy ax5 ay1 ax0 ax1 ax3 ay0 ax2 ax4 Write - 28 - W9816G6CH ay2 ay4 ay3 Precharge 23 ...
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... RCD RAb RAb aw0 aw1 aw2 aw3 AP* Active * AP is the internal precharge start timing - 29 - W9816G6CH RAS RP CAx t AC bx0 bx1 bx2 Read AP* Publication Release Date: June 10, 2005 Revision A0 ...
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... Bank #0 Active Write Bank #1 (CLK = 100 MHz RCD RAb RAb CAx bx0 aw3 Active Write AP the internal precharge start timing - 30 - W9816G6CH RAS RP RAc RAc bx1 bx3 bx2 AP* Active 23 ...
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... CLK RAS CAS WE BA A10 A0-A9 DQM CKE DQ All Banks Auto Prechage Refresh (CLK = 100 MHz W9816G6CH Auto Refresh (Arbitrary Cycle) Publication Release Date: June 10, 2005 Revision A0 23 ...
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... MHz CLK RAS CAS WE BA A10 A0-A9 DQM t CKE t CKS DQ All Banks Self Refresh Precharge Entry CKS SB Self Refresh Cycle - 32 - W9816G6CH CKS Operation Cycle Arbitrary Cycle 23 ...
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... Bank # CBw CBx CBy av0 av1 av3 aw0 ax0 ay0 av2 Single Write - 33 - W9816G6CH CBz t AC az0 az1 az2 az3 Read Publication Release Date: June 10, 2005 Revision A0 23 ...
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... When CKE goes high, command input must be No operation at next CLK rising edge CAa t CKS ax0 ax1 ax2 ax3 Precharge Read - 34 - W9816G6CH RAa RAa CAx CKS NOPActive Precharge Standby Power Down mode ...
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... Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. (min W9816G6CH Act Act AP Act Publication Release Date: June 10, 2005 ...
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... AP Act t RP Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. Activate - 36 - W9816G6CH Act Act ...
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... Read Read Read Q0 Q1 Read BST BST BST represents the Burst stop command - 37 - W9816G6CH Publication Release Date: June 10, 2005 Revision A0 ...
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... Commad DQ (2) Write cycle ( a ) CAS latency = 2 Write Commad DQM CAS latency = 3 Write Commad DQM Note: PRCG PRCG PRCG PRCG PRCG represents the Precharge command - 38 - W9816G6CH ...
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... CLK cycle No. External CLK Internal CKE DQM DQM MASK ( DQM MASK ( CKE MASK ( W9816G6CH CKE MASK CKE MASK Publication Release Date: June 10, 2005 Revision A0 ...
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... Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM W9816G6CH Open Open Open ...
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... Self Refresh mode NOP Represents the No-Operation command Command Represents one command (min)+t (min) CKS CK NOP Command Input Buffer Enable (min (min)+t (min) CKS CK Command Input Buffer Enable - 41 - W9816G6CH (min (min Publication Release Date: June 10, 2005 Revision A0 ...
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... NOM. 1.20 0.05 0.10 0.15 0.002 0.004 0.90 1.00 1.10 0.035 0.039 0.30 0.45 0.012 0.10 0.20 0.004 0.006 0.15 20.82 20.95 21.08 0.820 0.825 10.03 10.16 10.29 0.395 0.400 11.56 11.76 11.96 0.455 0.463 E 0.80 0.031 0.50 0.60 0.40 0.016 0.020 0.80 0.031 0.10 0.88 0.031 W9816G6CH MAX. 0.047 0.006 0.043 0.018 0.008 0.830 0.405 0.471 0.024 0.004 o 10 ...
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... TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 - 43 - W9816G6CH DESCRIPTION Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No ...