ELANSC300-25KC Advanced Micro Devices, ELANSC300-25KC Datasheet
ELANSC300-25KC
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ELANSC300-25KC Summary of contents
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... Kbyte x 8 bit or 1 Mbyte x 16 bit DRAM or SRAM as main memory This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this product without notice. – ...
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GENERAL DESCRIPTION The ÉlanSC300 microcontroller is a highly integrated, low-voltage, single-chip implementation of the Am386SXLV microprocessor plus most of the addi- tional logic needed for an AT-compatible personal com- puter ideal for embedded PC applications, such as point-of-sale ...
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CUSTOMER SERVICE The AMD customer service network includes U.S. of- fices, international offices, and a customer training cen- ter. Expert technical assistance is available from the AMD worldwide staff of field application engineers and factory support staff who can answer ...
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BLOCK DIAGRAM IOR, IOW, MEMR, MEMW, BALE A20GATE, RC MCS16, IOCS16, 8042CS, SYSCLK IOCHRDY, 0WS Bus Controller PD15–PD0 PA23–PA0 Am386SXLV CONTROL LFX X32IN Management Clock Control Unit Generators X32OUT Real-Time Clock (146818A) Programmable Interval Timer (8254 ...
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... K É LANSC300 Valid Combinations ELANSC300–25 ELANSC300–33 ELANSC300–25 ELANSC300–33 ELANSC300–25 ELANSC300– TEMPERATURE RANGE C = Commercial ( Industrial (–40 C < T PACKAGE TYPE K = 208 lead QFP (Plastic Shrink Quad Flat Pack) (PQR-208) ...
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TABLE OF CONTENTS Distinctive Characteristics ............................................................................................................ 1 General Description ..................................................................................................................... 2 Customer Service ........................................................................................................................ 3 Block Diagram ............................................................................................................................. 4 Ordering Information .................................................................................................................... 5 Connection Diagram .................................................................................................................. 13 ÉlanSC300 Microcontroller Pin Designations ............................................................................ 14 Pin Designations (Sorted by Pin Number) ................................................................................. ...
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PE ......................................................................................................................................... 37 PPDWE [PPDCS].................................................................................................................. 37 PPOEN.................................................................................................................................. 37 SLCT ..................................................................................................................................... 37 SLCTIN [PCMCOE]............................................................................................................... 38 STRB..................................................................................................................................... 38 Serial Port Interface ................................................................................................................... 38 CTS ....................................................................................................................................... 38 DCD ...................................................................................................................................... 38 DSR....................................................................................................................................... 38 DTR/CFG1 ............................................................................................................................ 38 RIN ........................................................................................................................................ 38 RTS/CFG0 ............................................................................................................................ 38 SIN ........................................................................................................................................ ...
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LVDD..................................................................................................................................... 41 LVEE ..................................................................................................................................... 41 M ........................................................................................................................................... 42 Miscellaneous Interface ............................................................................................................. 42 LF1, LF2, LF3, LF4 (Analog inputs) ...................................................................................... 42 X1OUT [BAUD_OUT]............................................................................................................ 42 [X14OUT] .............................................................................................................................. 42 X32IN, X32OUT .................................................................................................................... 42 Local Bus Interface .................................................................................................................... 42 A23–A12 ............................................................................................................................... 42 ...
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PCMCIA Slots ....................................................................................................................... 50 The PMU Modes and Clock Generators ............................................................................... 50 ÉlanSC300 Microcontroller Power Management .................................................................. 53 Micro Power Off Mode .......................................................................................................... 55 Core Peripheral Controllers ................................................................................................... 60 Additional Peripheral Controllers ........................................................................................... 60 Parallel Port Anomalies ......................................................................................................... 62 PC/AT ...
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Figure 12. 5-V I/O Drive Type E Fall Time ................................................................................ 86 Figure 13. 3.3-V I/O Drive Type D Rise Time............................................................................ 87 Figure 14. 3.3-V I/O Drive Type D Fall Time ............................................................................. 87 Figure 15. 5-V I/O Drive Type D Rise ...
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LIST OF TABLES Table 1. I/O Pin Voltage Level................................................................................................. 24 Table 2. Memory Bus Interface ............................................................................................... 25 Table 3. System Interface ....................................................................................................... 26 Table 4. Keyboard Interface .................................................................................................... 28 Table 5. Parallel Port Interface................................................................................................ 28 Table 6. Serial Port Interface................................................................................................... ...
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Table 51. Power-Up Sequencing ............................................................................................. 99 Table 52. DRAM Memory Interface, Page Hit and Refresh Cycle ......................................... 102 Table 53. DRAM First Cycle Read Access ............................................................................. 104 Table 54. DRAM Bank/Page Miss Read Cycles .................................................................... 104 Table 55. DRAM First ...
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CONNECTION DIAGRAM GND 1 2 RAS0 RAS1 3 CAS1L [SRCS2 CAS1H [SRCS3] 6 CAS0L [SRCS0] CAS0H [SRCS1 MWE 9 VMEM 10 MA10/SA13 11 MA9/SA23 12 GND MA8/SA22 13 MA7/SA21 14 MA6/SA20 15 MA5/SA19 16 MA4/SA18 17 ...
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MICROCONTROLLER PIN DESIGNATIONS This section, beginning with the Connection Diagram on the preceding page, identifies the pins of the ÉlanSC300 microcontroller and lists the signals associ- ated with each pin. The table beginning on page 15 lists the pins ...
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PIN DESIGNATIONS (SORTED BY PIN NUMBER) Signal Name Pin No. (Alternate Functions) 1 GND 2 RAS0 3 RAS1 4 CAS1L [SRCS2] 5 CAS1H [SRCS3] 6 CAS0L [SRCS0] 7 CAS0H [SRCS1] 8 MWE 9 VMEM 10 MA10/SA13 11 MA9/SA23 12 GND ...
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PIN DESIGNATIONS (SORTED BY PIN NUMBER) (CONTINUED) Signal Name Pin No. (Alternate Functions) 130 MCEH_A 131 VPP_A 132 REG_A 133 RST_A 134 CA24 135 VCC 136 CA25 137 PMC0 138 PMC1 139 SPKR 140 IORESET 141 RESIN 142 VSYS2 143 ...
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PIN DESIGNATIONS (SORTED BY PIN NAME) Signal Name (Alternate Functions) Pin No. (0WS/ADS) DSMD7 172 8042CS [XTDAT] 75 (A12/BALE) LVDD 173 (A13/DACK6) DSMA4 161 (A14/DACK7) DSMA5 160 (A15/DACK3) DSMA6 159 (A16/DACK0) DSMA7 158 (A17/LA17) DSMA8 155 (A18/LA18) DSMA9 154 (A19/LA19) ...
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PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED) Signal Name (Alternate Functions) Pin No. CD_B 116 CFG0/RTS 93 CFG1/DTR 92 CP1 (PULLDN/IRQ5) 178 CP2 (PULLUP/IRQ10) 179 (CPUCLK/PULLUP) DSMA3 162 (CPURDY/LMEG) DSOE 147 (CPURST/RSVD) DSMA2 163 CTS ...
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PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED) Signal Name (Alternate Functions) Pin No. DSCE (DACK1/DACK1) 146 DSMA0 (NC/PULLUP) 165 DSMA1 (PULLUP/IRQ7) 164 DSMA10 (A19/LA19) 153 DSMA11 (A20/LA20) 152 DSMA12 (A21/LA21) 151 DSMA13 (A22/LA22) 150 DSMA14 (A23/LA23) 149 DSMA2 (CPURST/RSVD) 163 ...
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PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED) Signal Name (Alternate Functions) Pin No. (IOIS16A) WP_A 112 (IOIS16B) WP_B 118 IOR 54 IORESET 140 IOW 55 (IREQ_A) RDY_A 111 (IREQ_B) RDY_B 117 IRQ1 195 (IRQ10/PULLUP) CP2 179 (IRQ11/BLE) DSMD2 167 (IRQ12/IRQ12) ...
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PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED) Signal Name (Alternate Functions) Pin No. LVDD (A12/BALE) 173 LVEE (IRQ15/IRQ15) 182 M (IRQ4/IRQ4) 173 MA0/SA14 24 MA1/SA15 21 MA10/SA13 10 MA11/SA12 60 MA2/SA16 19 MA3/SA17 18 MA4/SA18 17 MA5/SA19 16 MA6/SA20 15 ...
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PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED) Signal Name (Alternate Functions) Pin No. RAS0 RAS1 RC 78 RDY_A (IREQ_A) 111 RDY_B (IREQ_B) 117 REG_A 132 REG_B 126 RESIN 141 RIN 100 ROMCS 44 RST_A 133 RST_B 127 RSTDRV 58 RTS/CFG0 ...
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PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED) Signal Name (Alternate Functions) Pin No. SPKR 139 (SPKR_A) BVD2_A 113 (SPKR_B) BVD2_B 119 [SRCS0] CAS0L [SRCS1] CAS0H [SRCS2] CAS1L [SRCS3] CAS1H STRB 83 (STSCHG_A) BVD1_A 114 (STSCHG_B) BVD1_B 120 SUS/RES 103 SYSCLK ...
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PIN STATE TABLES The Pin State tables beginning on page 25 are grouped by function based on their primary function when the ÉlanSC300 microcontroller is configured at reset for the internal LCD Controller mode (NAME1). See page 14 for a ...
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Signal Name Pin No. Type 1,3 2 RAS0 3 1,3 RAS1 1,2 4 CAS1L [SRCS2] 1,2 5 CAS1H [SRCS3] 1,2 6 CAS0L [SRCS0] 1,2 7 CAS0H [SRCS1 MA10/SA13 3 11 MA9/SA23 3 13 MA8/SA22 3 14 MA7/SA21 3 ...
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Signal Name Pin No. I/O Type MA11/SA12 60 O SA11 61 O SA10 62 O SA9 63 O SA8 64 O SA7 66 O SA6 67 O SA5 69 O SA4 70 O SA3 71 O SA2 72 O SA1 ...
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Signal Name Pin No. I/O Type AEN [TDI] 47 O(I) TC [TMS] 49 O(I) ENDIRL 50 O ENDIRH 51 O DBUFOE 59 O IOR 54 O IOW 55 O MEMR 56 O MEMW 57 O RSTDRV 58 O IOCHRDY 192 ...
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I/O Signal Name Pin No. Type 8042CS [XTDAT] 75 O(STI A20GATE 79 I Notes: All inputs that have VCC clamp = 5 V are 5-V safe inputs regardless of their VCCIO. Signal Name Pin No ...
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I/O Signal Name Pin No. Type DTR/CFG RTS/CFG0 SOUT 94 O CTS 96 I DCD 98 I DSR 97 I RIN 100 I SIN 99 I Notes: 1. These pins are terminated externally per ...
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I/O Signal Name Pin No. Type MCEL_A 129 O MCEH_A 130 O VPP_A 131 O REG_A 132 O 1 133 O RST_A CD_A 110 STI 2 111 I RDY_A 2 112 I WP_A 2 113 STI BVD2_A 2 114 STI ...
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I/O Signal Name Pin No. Type DSMD7 (ADS/0WS) 172 B (O/I) DSMD6 (D/C/ 171 B (O/I) 1 DRQ0) DSMD5 (M/IO/ 170 B (O/I) 1 DRQ3) DSMD4 (W/R/ 169 B (O/I) 1 DRQ7) DSMD3 (BHE/ 168 B (O/I) 1 IRQ9) DSMD2 ...
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I/O Signal Name Pin No. Type LCDD3 174 O (I/I) (DRQ1 / DRQ1) LCDD0 (DACK5/ 144 O DACK5) LCDD1 (DRQ5/ 175 O (I/I) DRQ5) LCDD2 (IOCHCHK/ 177 O (I/I) IOCHCHK) M (IRQ4/IRQ4) 173 O (I/I) CP1 (PULLDN/IRQ5) 178 O (I/I) ...
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I/O Signal Name Pin No. Type 1 140 I IORESET 201 I 2 X32IN 3 202 O X32OUT LF1 204 A LF2 205 A LF3 206 A LF4 207 A X1OUT 200 O [BAUD_OUT] RESIN 141 STI 4 139 O ...
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PIN DESCRIPTIONS Descriptions of the ÉlanSC300 microcontroller pins are organized into the following functional groupings: Memory bus interface System interface Keyboard interface Parallel port interface Serial port interface MEMORY BUS INTERFACE CAS1H [SRCS3], CAS1L [SRCS2], CAS0H [SRCS1], CAS0L [ ] ...
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For more information about the ROMCS Using 16-Bit Designs in Élan ROMCS ÉlanSC310 Microcontrollers Application Note , order #21825. SYSTEM INTERFACE AEN [TDI] DMA Address Enable (Output; Active High) AEN is used to indicate that the current address active on ...
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IOW I/O Write Command (Output; Active Low) The IOW signal indicates that the current cycle is a write of the currently selected I/O device. When this signal is asserted, the selected I/O device can latch data from the data bus. ...
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TC [TMS] Terminal Count (Output; Active High) This signal is used to indicate that the transfer count for the currently active DMA channel has reached zero, and that the current DMA cycle is the last transfer. This is a dual-function ...
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SLCTIN [PCMCOE] Printer Selected (Output; Active Low) Asserting SLCTIN selects the line printer. This pin can be programmed to become the PCMCIA output enable signal (PCMCOE). For more information, see “Parallel Port” on page 61. STRB Strobe (Output; Active Low) ...
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ICDIR Card Data Direction (Output) This signal controls the direction of the card data buff- ers or translators, working in conjunction with the and card enable signals to control the MCEL_x MCEH_x data buffers on the card interface. When this ...
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POWER MANAGEMENT INTERFACE ACIN AC Input Status (Input; Active High) When asserted, this signal disables all power manage- ment functions (if so enabled). It can be used to indi- cate when the system is being supplied power from an AC ...
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CP1 LCD Panel Line Clock (Output) This is the Line Clock when in internal LCD mode and an LCD configuration is selected activated at the start of every pixel line refresh cycle. CP1 should be connected to the ...
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M LCD Panel AC Modulation (Output) In internal LCD mode, this is the AC modulation signal for the LCD. AC modulation causes the LCD to change polarity on its crystal material to keep the LCD from forming a DC bias. ...
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CPUCLK CPU 2X Clock (Output) This is the timing reference for the local bus device. The high-speed PLL can be programmed to provide one of the clock frequencies shown on page 53. CPURDY 386 CPU Ready Signal (Output; Active Low) ...
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IRQ15, IRQ14, IRQ12–IRQ9, IRQ7–IRQ3, IRQ1 Interrupt Request (Inputs; Rising Edge/Active High Trigger) Interrupt Request input pins signal the internal 8259 compatible interrupt controller that an I/O device needs servicing. IRQ3 and IRQ6 are shared with PIRQ0 and PIRQ1. IRQ0 is ...
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AVCC is required for battery backup. For more informa- tion about battery backup, see the Élan TM Élan SC310 Microcontrollers Solution For Systems Using a Back-Up Battery Application Note , order #20746. GND System Ground Pins These pins provide electric ...
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Am386 SX/SXL/SXLV Data Sheet , order #21020 and the Am386 DX/DXL Data Sheet , order #21017. Along with standard 386 architectural features, the CPU core includes SMM. SMM and the other features of the CPU are described in the Am386DXLV ...
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Table 15. Supported DRAM/SRAM Configuration Total DRAM/SRAM Size Bank 0 DRAMs 512 Kbyte 4 256 bits 512 Kbyte 1 256K x 16 bits 1 Mbyte 4 256 bits 1 Mbyte 1 256K x 16 ...
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Table 16. DRAM Address Translation (Page Mode) Index Index Index DRAM B4h 66h B1h Bit Bits Bits Size Bank (Byte) (Byte ...
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Table 17. DRAM Address Translation (Enhanced Page Mode) Index Index Index DRAM B4h 66h B1h Bit Bits Bits Size Bank (Byte) (Byte ...
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Configuration Index 63h Index 66h Bit 4 Bits 1 and Notes: Refer to Index 70h, bit 0, in the Élan for information on how to select SRAM versus DRAM. PCMCIA Slots Th e Éla nSC300 m ...
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MHz 32 kHz INT_PLL Input EN LS_PLL_EN HS_PLL_EN VID_PLL_EN Élan™SC300 Microcontroller Data Sheet LS_PLL EN 2.048 MHz Figure 1. PLL Block Diagram Programmable HS_PLL 2 x CPU Clock ...
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Cycle) + (DMA Cycle) + (Low Speed CPU Clock High Speed PLL ( 18.432 MHz Divide Chain Programmable Low Speed (I (Low-Speed PLL mode only ...
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In the PLL Block Diagram, the INT_PLL is the Interme- diate PLL, and is used to multiply the 32.768-kHz input frequency produce a 1.4746-MHz input for use by the LS_PLL and the VID_PLL. The LS_PLL, or Low- ...
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Mode Power On After Power-on reset, system enters High-Speed PLL mode. High-Speed PLL The system will be in this mode as long as activities are detected by activity monitor (described in the Pro- grammable Activity Mask Registers, Indexes 08h, 75h, ...
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PMC and PGP Pins The ÉlanSC300 microcontroller supports five power management control (PMC) pins and four programma- ble general purpose (PGP) pins. The PMC pins can be used to control the VCC rails of peripheral devices. The PMC pins are ...
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AVCC Analog Secondary Power Supply R RESIN Figure 3. Typical System Design with Secondary Power Supply to Maintain RTC When Primary Power Supply is Off (DRAM Refresh is Optional.) A portion ...
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When entering Micro Power Off mode and the primary power supply outputs are turned off, all of the ÉlanSC300 microcontroller’s powered-down I/O pins are essentially tri-stated and the internal pull-ups are removed because the VCCIO and VCC CLAMP of the ...
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The type of Micro Power DRAM refresh performed (CAS-before-RAS refresh, or self refresh) will be the same as that for which the part was configured before the IORESET pin sampled Low. If the micro power re- fresh feature is enabled ...
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VSYS is powered up, RSTDRV is im- mediately driven High and will remain High until the signal is deasserted and the preserved pro- IORESET grammed value in the PLL start-up timer has expired. Force Term Figure ...
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Core Peripheral Controllers The ÉlanSC300 microcontroller includes all the stan- dard peripheral controllers that make up a PC/AT sys- tem, including interrupt controller, DMA controller, counter/timer, and ISA bus controller. For more infor- TM mation, see Chapter 4 of the ...
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See Chapter 4 of the Élan Microcontroller Programmer’s Reference Manual , order #18470. 16450 UART The ÉlanSC300 microcontroller chip includes a UART, providing ÉlanSC300 microcontroller systems with a serial port. This serial controller is fully compatible ...
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SD7–SD0 PPOEN PPDCS IOW IOR Figure 6. The ÉlanSC300 CPU Bidirectional Parallel Port and EPP Implementation Parallel Port Anomalies General The ÉlanSC300 microcontroller parallel port can be physically mapped to three different I/O locations or can be completely disabled. These ...
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NMI check condition sources and sound generation features. The top, or most signif- icant, 4 bits are read/write bits that return status and di- agnostic ...
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Mbyte System Memory 3 512K x 8 512K x 8 RAS CAS WE Serial MAX241 Port Élan SC300 DSMD7–DMSD0 Microcontroller Video SRAM DSMA14–DMSA0 LCD Note: *Optional Figure 7. Typical System Block Diagram (Internal LCD Controller) ...
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LCD, Local Bus, or Maximum ISA Bus Controller ...
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Table 26. External Resistor Requirements (Continued) Signal Name LVEE (IRQ15/IRQ15) M (IRQ4/IRQ4) LCDD2 (IOCHCHK/IOCHCHK) DSWE (PULLUP/PULLUP) FRM (IRQ12/IRQ12) CP2 (PULLUP/IRQ10) DSMA1 (PULLUP/IRQ7) DSMD0 (LDEV/RESERVED) LCDD3 (DRQ1/ DRQ1) LCDD1 (DRQ5/ DRQ5) CP1 (PULLDN/ IRQ5) DSMD7 (ADS/0WS) DSMD3 (BHE/IRQ9) DSMD2 (BLE/IRQ11) DSMA3 ...
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Table 26. External Resistor Requirements (Continued) Signal Name RDY_A RDY_B WP_A WP_B DCD DSR SIN CTS RIN STRB AFDT INIT SLCTIN ERROR ACK BUSY PE SLCT PGP0 PGP1 ACIN Notes: All pull-up and pull-down resistor requirements are specified in ohms. ...
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ALTERNATE PIN FUNCTIONS To provide the system designer with the most flexibility, the ÉlanSC300 microcontroller provides a means for reconfiguring some of the pin functions, depending on the system requirements. Reconfiguration of the ÉlanSC300 microcontroller pin functions is accom- plished ...
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CPU Local Bus Interface versus Internal LCD Interface The tables of this section are brief descriptions of the alternate pin functions/names and the pin name of the Internal LCD mode function that the alternate function replaces. The CPU Local Bus ...
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Maximum ISA Interface versus Internal LCD Interface The maximum ISA interface alternate functions are configured via the DTR and RTS pin states when the ÉlanSC300 microcontroller is reset. Table 29. Pins Shared Between Maximum ISA Bus and Internal LCD Interface ...
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ALTERNATE PIN FUNCTIONS SELECTED VIA FIRMWARE The following tables contain brief descriptions of the alternate pin functions/names and the pin names of the default function that the alternate function replaces. These alternate functions are selected via system firmware only. SRAM ...
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X1OUT [BAUD_OUT] Clock Source The internal clock source driving out on this pin is configured via register bits of the Function Enable Registers, Indexes B0h and B1h. Table 33. X1OUT Clock Source Pin Description BAUDOUT Pin Name Pin Type [BAUD_OUT] ...
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ISA BUS DESCRIPTIONS The three bus configuration options (Internal LCD con- troller, local bus, or maximum ISA bus) each support a somewhat different subset of the ISA bus standard. The Internal LCD controller option supports the small- est ISA subset, ...
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System Test and Debug The ÉlanSC300 microcontroller provides test and debug features compatible with the standard Test Ac- cess Port (TAP) and Boundary-Scan Architecture (JTAG). The test and debug logic contains the following ele- ments: Five extra pins—TDI, TMS, TCK, ...
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Table 40. Boundary Scan (JTAG) Cells—Order and Type Cell Pin No. Name Position 77 PMC2 A20GATE 3 80 AFDT STRB 6 84 SLCTIN 7 85 BUSY 8 86 ERROR 9 ...
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Table 40. Boundary Scan (JTAG) Cells—Order and Type (Continued) Cell Pin No. Name Position 123 MCEL_B 43 124 MCEH_B 44 125 VPP_B 45 126 REG_B 46 127 RST_B 47 129 MCEL_A 48 130 MCEH_A 49 131 VPPA 50 132 REG_A ...
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Table 40. Boundary Scan (JTAG) Cells—Order and Type (Continued) Cell Pin No. Name Position 170 DSMD5 86 171 DSMD6 87 172 DSMD7 88 173 M 89 174 LCDD3 90 175 LCDD1 91 177 LCDD2 92 178 CP1 93 179 CP2 ...
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Table 40. Boundary Scan (JTAG) Cells—Order and Type (Continued) Cell Pin No. Name Position 19 MA2 129 21 MA1 130 24 MA0 131 25 D15 132 26 D14 133 27 D13 134 28 D12 135 29 D11 136 30 D10 ...
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Table 40. Boundary Scan (JTAG) Cells—Order and Type (Continued) Cell Pin No. Name Position 71 SA3 169 72 SA2 170 73 SA1 171 74 SA0 172 75 8042CS 173 76 DRQ2 JTAG Instruction Opcodes Table 41 lists the ÉlanSC300 microcontroller’s ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature ....................... – +150 C Ambient Temperature Under Bias ... – +125 C Stresses above those listed may cause permanent device failure. Functionality at or above these limits is not implied. Exposure ...
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Table 43. DC Characteristics over Commercial and Industrial Operating Ranges (Plastic Shrink Quad Flat Pack (QFP), 33 MHz VCCIO = 4.5 V – 5 +70 C (commercial); T AMBIENT Symbol Parameter Description ...
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THERMAL CHARACTERISTICS The ÉlanSC300 microcontroller is specified for operation with a case temperature range from 0°C to 100°C for a commercial device. Table 45 shows the thermal resistance for 208-pin QFP and TQFP packages. Table 45. Thermal Resistance (°C/Watt) Package ...
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Table 47. Typical Internal LCD Mode Power Consumption = 0 TTL TTL Power Pin Group Name Volts CPU Core VCC 3.3 I/O VCC VCC1 5 Analog AVCC 3.3 I/O VCC5 ...
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DERATING CURVES This section describes how to use the derating curves on the following pages in order to determine potential specified timing variations based on system capacitive loading. The pin characteristics tables in this document (see page 24) have a ...
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Figure 9. 3.3-V I/O Drive Type E Rise Time Figure 10. 3.3-V I/O Drive Type E Fall Time Élan™SC300 ...
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Figure 11. 5-V I/O Drive Type E Rise Time ...
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Figure 13. 3.3-V I/O Drive Type D Rise Time Figure 14. 3.3-V I/O ...
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Figure 15. 5-V I/O Drive Type D Rise Time ...
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Figure 17. 3.3-V I/O Drive Type C Rise Time Figure 18. 3.3-V I/O Drive Type C Fall Time Élan™SC300 ...
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Figure 19. 5-V I/O Drive Type C Rise Time ...
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Figure 21. 3.3-V I/O Drive Type B Rise Time Figure 22. 3.3-V I/O Drive Type B Fall Time ...
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Figure 23. 5-V I/O Drive Type B Rise Time ...
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Figure 25. 3.3-V I/O Drive Type A Rise Time Figure 26. 3.3-V I/O Drive Type A Fall Time ...
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Figure 27. 5-V I/O Drive Type A Rise Time ...
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VOLTAGE PARTITIONING The ÉlanSC300 microcontroller supports both 3.3-V system designs and mixed 3.3-V and 5-V system de- signs. For 3.3-V-only operation, all supply pins (VCC, VCC1, VCC5, VMEM, VSYS, VSYS2, and AVCC) should be connected to the 3.3-V DC supply. ...
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L and addition to these parameters, the manufac- O turer will provide a load capacitance specification usu ...
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LOOP FILTERS Each of the Phase-Locked Loops (PLLs) in the ÉlanSC300 microcontroller requires an external Loop Filter. Figure 30 describes each of the Loop Filters and the recommended component values. The recom- mended component values are shown in Table 50. ...
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AC SWITCHING CHARACTERISTICS AND WAVEFORMS The AC specifications provided in the AC characteris- tics tables that follow consist of output delays, input setup requirements, and input hold requirements. Fig- ure 31 provides a key to the switching waveforms. AC specifications ...
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AC Switching Characteristics over Commercial and Industrial Operating Ranges Table 51. Power-Up Sequencing (See Figures 32, 33, 34, and 35) Symbol Parameter Description t1 All VCC valid to RESIN and IORESET inactive t2 RESIN and IORESET inactive to RSTDRV inactive ...
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VCC/AVCC VMEM RESIN VCC5 VSYS2 VCC1 VSYS IORESET RSTDRV Notes: 1. RSTDRV external driver is powered by: VCCIO = VSYS and VCC Clamp = VCC5. VCC/AVCC VMEM RESIN VCC5 VSYS2 VCC1 VSYS IORESET RSTDRV Notes: 1. RSTDRV external driver is ...
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RSTDRV Note 1 IORESET VCC5 t 6 VSYS2 VCC1 VSYS VCC/AVCC VMEM RESIN Notes: 1. RSTDRV external driver is powered by: VCCIO = VSYS and VCC Clamp = VCC5 secondary power source could be applied at ...
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Table 52. DRAM Memory Interface, Page Hit and Refresh Cycle (See Figures 36 and 37) Symbol Parameter Description t30 MA valid setup to RAS Low t31 MA hold from RAS Low t32 MA setup to CAS Low t37 CAS precharge ...
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MA10–MA0 RAS CAS MWE D15–D0 RAS0 CAS0 MWE Figure 37. DRAM Timings, Refresh Cycle t31 t38 t32 t39 Figure 36. DRAM Timings, Page Hit t53 t50 t51 Élan™SC300 ...
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Table 53. DRAM First Cycle Read Access (See Figure 38) Symbol Parameter Description t5a CAS Low to data valid (read access time) t28a RAS Low to data valid (read access time) t30 MA valid setup to RAS Low t31 MA ...
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Table 54. DRAM Bank/Page Miss Read Cycles (See Figure 38) (Continued) Symbol Parameter Description t41b CAS pulse width (read, page miss) t44b CAS hold from RAS Low t47 D15–D0 hold from CAS High (read) Notes: For more information about DRAM ...
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Table 55. DRAM First Cycle Write Access (See Figure 39) Symbol Parameter Description t5c D15–D0 setup to CAS Low (write) t27d MWE setup to CAS Low (first cycle) t30 MA valid setup to RAS Low t31 MA hold from RAS ...
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MA10–MA0 t31 t30 t40 RAS t44d t32 t39 t41d CAS t43 t27d MWE t5c D15–D0 First Cycle Figure 39. DRAM First Cycle and Bank/Page Miss (Write Cycles t38 t34 ...
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Table 57. Local Bus Interface (See Figure 40) Symbol Parameter Description t1 CPUCLK period t2 CPUCLK pulse width low t3 CPUCLK pulse width high t4 ADS delay from CPUCLK t5 A[23–1] BLE, BHE, W/R,D/C, M/IO delay from CPUCLK t6a LDEV ...
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CPUCLK t4 ADS t5 A23–A12 LDEV LRDY CPURDY D15–D0 (in) D15–D0 (out) Élan™SC300 Microcontroller Data Sheet t11 t6a t12 Figure 40. Local ...
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Table 58. Video RAM/LCD Interface (See Figures 41 and 42) Symbol Parameter Description t81 DSMD hold from DSMA change t82 Display RAM read cycle pulse width t83 DSMD active from DSWE active t84 DSMD setup to DSWE inactive t85 DSMA ...
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DSMA14–DSMA0 DSCS DSOE DSWE DSMD7–DSMD0 CP1 CP2 FRM LCDD3– LCDD0 t82 t81 Figure 41. Display SRAM Timings t90 t92 t91 Figure 42. LCD Interface Timings Élan™SC300 Microcontroller Data Sheet ...
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Table 60. PCMCIA Memory Read Cycle (See Figure 43) Symbol Parameter Description t1a Data setup before MEMR inactive (8 bit) t1b Data setup before MEMR inactive (16 bit) t2 Data hold following MEMR t3 MEMR width time t4a Address setup ...
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SA25–SA0 t6a t6b REG/MCE MEMR WAIT_AB D15–D0 t11 ICDIR t13 DBUFOE t15a ENDIRH, t15b ENDIRL t10 t9 Figure 43. PCMCIA Memory Read Cycle Élan™SC300 Microcontroller Data ...
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Table 61. PCMCIA Memory Write Cycle (See Figure 44) Symbol Parameter Description t2 Data hold following MEMW t3 MEMW width time t4a Address setup before MEMW (8 bit) t4b Address setup before MEMW (16 bit) t5 Address hold following MEMW ...
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SA25–SA0 t6a REG/MCE t6b MEMW WAIT_AB D15–D0 t13a t13b DBUFOE t8a t8b MEMR Figure 44. PCMCIA Memory Write Cycle Élan™SC300 Microcontroller Data Sheet t10 t11 t12 ...
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Table 62. PCMCIA I/O Read Cycle (See Figure 45) Symbol Parameter Description t1 Data setup before IOR t2 Data hold following IOR t3a IOR width time (8 bit) t3b IOR width time (16 bit) t4a Address setup before IOR (8 ...
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SA15–SA0 t8 REG t6a t6b MCEL MCEH t20 IOR t10 IOIS16 WAIT_AB D15–D0 t14 ICDIR t16 DBUFOE t18a ENDIRH, t18b ENDIRL t3a t3b t12 t13 Figure 45. ...
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Table 63. PCMCIA I/O Write Cycle (See Figure 46) Symbol Parameter Description t1 Data setup before IOW active t2 Data hold following IOW t3a IOW width time (8 bit) t3b IOW width time (16 bit) t4a Address setup before IOW ...
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SA25–SA0 t8a REG t8b t6a t6b MCEL MCEH t1 IOW t16 t10 IOIS16 WAIT_AB D15–D0 t14a t14b DBUFOE Élan™SC300 Microcontroller Data Sheet t3a t3b t13 t12 Figure ...
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Table 64. BIOS ROM Read/Write 8-Bit Cycle (See Figure 47) Symbol Parameter Description t1a SA stable to ROMCS active t1b SA stable to ROMCS active t2a SA hold from ROMCS inactive (write) t2b SA hold from ROMCS inactive (read) t3a ...
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SA23–SA0 t1a ROMCS t1b MEMR/W RDDATA WRDATA DBUFOE ENDIRH, ENDIRL Figure 47. BIOS ROM Read/Write 8-Bit Cycle Élan™SC300 Microcontroller Data Sheet t3a t3b t14 t4a t4b t10 t12 0 ...
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Table 65. DOS ROM Read/Write 8-Bit Cycle (See Figure 48) Symbol Parameter Description t1a SA stable to DOSCS active t1b SA stable to DOSCS active t2a SA hold from DOSCS inactive (write) t2b SA hold from DOSCS inactive (read) t3a ...
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SA19–SA0 DOSCS t1b MEMR/W RDDATA WRDATA DBUFOE ENDIRH, ENDIRL Figure 48. DOS ROM Read/Write 8-Bit Cycle Élan™SC300 Microcontroller Data Sheet t1a t14 t4a t4b t10 t12 0 = Read ...
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Table 66. DOS ROM and Fast DOS ROM Read/Write 16-Bit Cycles (See Figure 49) Symbol Parameter Description t1a SA stable to DOSCS active t1b SA stable to DOSCS active t2a SA hold from DOSCS inactive (write) t2b SA hold from ...
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SA23–SA0 DOSCS t1b MEMR/W RDDATA WRDATA DBUFOE ENDIRH, ENDIRL Figure 49. DOS ROM Read/Write 16-Bit Cycle t1a t14 t4a t4b t10 t12 0 = Read Élan™SC300 Microcontroller Data Sheet ...
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Table 67. ISA Memory Read/Write 8-Bit Cycle (See Figure 50) Symbol Parameter Description t1 LA stable to BALE inactive t2 SA stable to command active t3 BALE pulse width t4 LA hold from BALE inactive t5a SA hold from ...
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BALE LA23–LA17 SA23–SA0 MEMR/W IOCHRDY RDDATA WRDATA DBUFOE ENDIRH, ENDIRL Figure 50. ISA Memory Read/Write 8-Bit Cycle Élan™SC300 Microcontroller Data Sheet t19 t4 t18 t6 t2 t8a ...
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Table 68. ISA Memory Read/Write 16-Bit Cycle (See Figure 51) Symbol Parameter Description t1 LA stable to BALE inactive t2 SA stable to command active t3 BALE pulse width t4 LA hold from BALE inactive t5a SA hold from command ...
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BALE t21 LA23–LA17 t20 SA23–SA0 MEMR/W t7a MCS16 IOCHRDY RDDATA WRDATA DBUFOE ENDIRH, ENDIRL Figure 51. ISA Memory Read/Write 16-Bit Cycle Élan™SC300 Microcontroller Data Sheet t8a ...
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Table 69. ISA Memory Read/Write 0 Wait State Cycle (See Figure 52) Symbol Parameter Description t1 LA stable to BALE inactive t2 SA stable to command active t3 BALE pulse width t4 LA hold from BALE inactive t5a SA hold ...
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BALE LA23–LA17 SA23–SA0 MEMR/W MCS16 0WS RDDATA WRDATA Figure 52. ISA Memory Read/Write 0 Wait State Cycle Élan™SC300 Microcontroller Data Sheet t4 t8 t14 ...
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Table 70. ISA I/O 8-Bit Read/Write Cycle (See Figure 53) Symbol Parameter Description t1a SA stable to IOW active t1b SA stable to IOR active t2a SA hold from IOW inactive t2b SA hold from IOR inactive t3a IOW pulse ...
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SA15–SA 0 BALE IOR/W IOCHRDY RDDATA WRDATA DBUFOE ENDIRH, ENDIRL Figure 53. ISA I/O 8-Bit Read/Write Cycle Élan™SC300 Microcontroller Data Sheet t14 t1a t1b t4a t4b t10 t12 0 ...
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Table 71. ISA I/O 16-Bit Read/Write Cycle (See Figure 54) Symbol Parameter Description t1a SA stable to IOW active t1b SA stable to IOR active t2 SA stable to IOCS16 active t3a IOW active to IOCHRDY inactive t3b IOR active ...
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SA15–SA0 BALE IOR/W IOCS16 IOCHRDY RDDATA WRDATA DBUFOE ENDIRH, ENDIRL Figure 54. ISA I/O 16-Bit Read/Write Cycle Élan™SC300 Microcontroller Data Sheet t15 t1a t1b t13 t2 t3a t3b t11 ...
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Table 72. EPP Data Register Write Cycle (See Figure 55) Symbol t0 AFDT delay from IOW active t1 AFDT delay from PPDCS active t2 AFDT delay from PPOEN active t3 AFDT active pulse width (no wait states added) t4 AFDT ...
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Table 73. EPP Data Register Read Cycle (See Figure 56) Symbol t1 AFDT delay from PPDCS active t2 AFDT active pulse width (no wait states) t3 AFDT High to Low recovery t4 Read data valid delay t5 Read data hold ...
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PHYSICAL DIMENSIONS PQR 208, Trimmed and Formed Plastic Shrink Quad Flat Pack (QFP) Pin 208 Pin 52 3.20 3.60 0.25 MIN Notes: 1. All measurements are in millimeters unless otherwise noted. 2. Not to scale. For reference only. 138 P ...
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... All measurements are in millimeters unless otherwise noted. 2. Not to scale. For reference only. Trademarks AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am386 and Am486 are registered trademarks of Advanced Micro Devices, Inc. E86, K86, and Élan are trademarks of Advanced Micro Devices, Inc. ...