IDT72201L20J Integrated Device Technology, Inc., IDT72201L20J Datasheet

IDT72201L20J

Manufacturer Part Number

IDT72201L20J

Description

CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9

Manufacturer

Integrated Device Technology, Inc.

Datasheet

1.IDT72201L20J.pdf (19 pages)

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IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO

64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

FEATURES:

• 64 x 9-bit organization (IDT72421)

• 256 x 9-bit organization (IDT72201)

• 512 x 9-bit organization (IDT72211)

• 1024 x 9-bit organization (IDT72221)

• 2048 x 9-bit organization (IDT72231)

• 4096 x 9-bit organization (IDT72241)

• 12 ns read/write cycle time (IDT72421/72201/72211)

• 15 ns read/write cycle time (IDT72221/72231/72241)

• Read and write clocks can be independent

• Dual-Ported zero fall-through time architecture

• Empty and Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags can

• Programmable Almost-Empty and Almost-Full flags

• Output enable puts output data bus in high-impedance

• Advanced submicron CMOS technology

• Available in 32-pin plastic leaded chip carrier (PLCC),

• For Through-Hole product please see the IDT72420/

• Military product compliant to MIL-STD-883, Class B

DESCRIPTION:

SyncFIFO

FUNCTIONAL BLOCK DIAGRAM

SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

1996 Integrated Device Technology, Inc

be set to any depth

default to Empty+7, and Full-7, respectively

state

ceramic leadless chip carrier (LCC), and 32-pin Thin

Quad Flat Pack (TQFP)

72200/72210/72220/72230/72240 data sheet

Integrated Device Technology, Inc.

The IDT72421/72201/72211/72221/72231/72241

are very high-speed, low-power First-In, First-

WRITE CONTROL

WCLK

WRITE POINTER

RESET LOGIC

WEN1

LOGIC

WEN2

CMOS SyncFIFO

64 X 9, 256 x 9, 512 x 9,

1024 X 9, 2048 X 9 and 4096 x 9

OUTPUT REGISTER

INPUT REGISTER

2048 x 9, 4096 x 9

512 x 9, 1024 x 9,

64 x 9, 256 x 9,

RAM ARRAY

- D

- Q

5.07

Out (FIFO) memories with clocked read and write controls.

The IDT72421/72201/72211/72221/72231/72241 have a 64,

256, 512, 1024, 2048, and 4096 x 9-bit memory array,

respectively. These FIFOs are applicable for a wide variety of

data buffering needs such as graphics, local area networks

and interprocessor communication.

port is controlled by a free-running clock (WCLK), and two

write enable pins (

Synchronous FIFO on every rising clock edge when the write

enable pins are asserted. The output port is controlled by

another clock pin (RCLK) and two read enable pins (

REN2

clock operation or the two clocks can run asynchronous of one

another for dual-clock operation. An output enable pin (

provided on the read port for three-state control of the output.

and Full (

and Almost-Full (

control. The programmable flags default to Empty+7 and Full-

7 for

offset loading is controlled by a simple state machine and is

initiated by asserting the load pin (

fabricated using IDT’s high-speed submicron CMOS

technology. Military grade product is manufactured in

compliance with the latest revision of MIL-STD-883, Class B.

These FIFOs have 9-bit input and output ports. The input

The Synchronous FIFOs have two fixed flags, Empty (

The IDT72421/72201/72211/72221/72231/72241 are

). The read clock can be tied to the write clock for single

PAE

and

). Two programmable flags, Almost-Empty (

OFFSET REGISTER

PAF

READ CONTROL

READ POINTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PAF

RCLK

WEN1

LOGIC

, respectively. The programmable flag

LOGIC

FLAG

), are provided for improved system

REN1

REN2

, WEN2). Data is written into the

2655 drw 01

PAE

PAF

DECEMBER 1995

IDT72421

IDT72201

IDT72211

IDT72221

IDT72231

IDT72241

DSC-2655/6

REN1

PAE

) is

)

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