ADL5306ACP-R2 Analog Devices Inc, ADL5306ACP-R2 Datasheet - Page 12

IC CONVERT LOGARITH 60DB 16LFCSP

ADL5306ACP-R2

Manufacturer Part Number
ADL5306ACP-R2
Description
IC CONVERT LOGARITH 60DB 16LFCSP
Manufacturer
Analog Devices Inc
Type
Logarithmic Converterr
Datasheet

Specifications of ADL5306ACP-R2

Rohs Status
RoHS non-compliant
Applications
Fiber Optics
Mounting Type
Surface Mount
Package / Case
16-LFCSP
Other names
ADL5306ACP-R2TR
ADL5306
The use of a negative supply, V
placed at ground level whenever the input transistor (Q1 in
Figure 1) has a sufficiently negative bias on its emitter. When
V
the default case when VSUM is grounded. This bias need not be
accurate, and a poorly defined source can be used. However, the
source must be able to support the quiescent current as well as
the INPT and IREF signal current. For example, it may be
convenient to utilize a forward-biased junction voltage of about
0.7 V or a Schottky barrier voltage of a little over 0.5 V. With the
summing node at ground, the ADL5306 may now be used as a
voltage-input log amp, at either the numerator input INPT or
the denominator input IREF by inserting a suitably scaled
resistor from the voltage source to the relevant pin. The overall
accuracy for small input voltages is limited by the voltage offset
at the inputs of the JFET op amps.
The use of a negative supply also allows the output to swing
below ground, thereby allowing the intercept to correspond to a
midrange value of I
referenced to the ACOM pin, and while V
negative for default operating conditions, it is free to do so.
Thus, adding a resistor from VLOG to the negative supply
lowers all values of V
disadvantage of this method is that the slope is reduced by the
shunting of the external resistor, and the poorly defined ratio of
on-chip and off-chip resistance causes errors in both the slope
and intercept. A more accurate method for repositioning the
intercept follows.
CHARACTERIZATION METHODS
During the characterization of the ADL5306, the device was
treated as a precision current-input logarithmic converter,
because it is impractical to generate accurate photocurrents by
illuminating a photodiode. The test currents were generated by
using either a well-calibrated current source, such as the
Keithley 236, or a high value resistor from a voltage source to
the input pin. Great care is needed when using very small input
currents. For example, the triax output connection from the
current generator was used with the guard tied to VSUM. The
input trace on the PC board was guarded by connecting
adjacent traces to VSUM.
These measures are needed to minimize the risk of leakage
current paths. With 0.5 V as the nominal bias on the INPT pin,
a leakage-path resistance of 1 GΩ to ground would subtract
0.5 nA from the input, which amounts to a –0.44 dB error for a
10 nA source current. Additionally, the very high output
resistance at the input pins and the long cables commonly
needed during characterization allow 60 Hz and RF emissions
to introduce substantial measurement errors. Careful guarding
techniques are essential to reducing the pickup of these
spurious signals.
N
= –0.5 V, the V
CE
PD
of Q1 and Q2 will be the same value as in
LOG
. However, the voltage V
, which raises the intercept. The
N
, allows the summing node to be
LOG
does not swing
LOG
remains
Rev. 0 | Page 12 of 16
The primary characterization setup shown in Figure 24 is used
to measure V
conformance, slope and intercept, the voltages appearing at Pins
VSUM, INPT, and IREF, and the buffer offset and V
with temperature. In some cases, a fixed resistor between Pins
VREF and IREF was used in place of a precision current source.
For the dynamic tests, including noise and bandwidth
measurements, more specialized setups are required. This
includes close attention to the input stabilizing networks; for
example, to ensure stable operation over the full current range
of I
and R13 = 2 kΩ are used at Pin IREF to ground.
Figure 25 shows the configuration used to measure the buffer
amplifier bandwidth. The AD8138 evaluation board includes
provisions to offset V
measurements over the full range of I
The network analyzer input impedances are set to 1 MΩ.
AD8138 PROVIDES DC OFFSET
Figure 25. Configuration for Buffer Amplifier Bandwidth Measurement
REF
(SIGNAL – INPT AND IREF
+IN
KEITHLEY 236
KEITHLEY 236
and temperature extremes, filter components C1 = 4.7 nF
EVALUATION
TRIAX CONNECTORS
SHIELD – GROUND)
AD8138
BOARD
GUARD – VSUM
REF
Figure 24. Primary Characterization Setup
, the static (dc) performance, logarithmic
B
A
OUTPUT INPUT R INPUT A INPUT B
LOG
NETWORK ANALYZER
at the buffer input, allowing
BNC-T
IREF
INPT
HP3577A
CHARACTERIZATION
VREF
DC MATRIX / DC SUPPLIES / DMM
ADL5306
1
2
3
4
BOARD
COMM
NC
VREF
IREF
INPT
VSUM
VNEG
16
PD
5
using a single supply.
COMM
VNEG
ADL5306
15
VSUM
6
VPOS
VLOG
VNEG
VOUT
COMM
BFIN
14
7
VOUT
VLOG
SCAL
VPOS
COMM
13
BFIN
8
REF
RIBBON
0.1µF
CABLE
03727-0-024
drift
12
11
10
9
03727-0-025
+V
S

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