AS7C33256NTD36A-133TQC Alliance Semiconductor, AS7C33256NTD36A-133TQC Datasheet
AS7C33256NTD36A-133TQC
Related parts for AS7C33256NTD36A-133TQC
AS7C33256NTD36A-133TQC Summary of contents
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... Snooze mode for standby operation Address register Burst logic CLK D Write delay addr. registers CLK Control logic CLK 36/32 Data 36/ Input Register CLK OE Alliance Semiconductor AS7C33256NTD32A AS7C33256NTD36A TM DDQ Q 18 CLK 256K x 32/36 SRAM Array 36/32 36/32 36/32 CLK Output Register OE 36/32 DQ[a:d] -166 -133 Units 6 7.5 166 133 MHz 3.5 ...
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... PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD- Alliance Semiconductor AS7C33256NTD32A AS7C33256NTD36A Speed 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/ ...
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... DQd2 22 DQd3 23 DQd4 24 25 DQd5 V 26 SSQ V 27 DDQ DQd6 28 29 DQd7 DQPd/NC 30 11/30/04, v. 2.1 ® TQFP 14x20mm Note: Pins 1, 30 and 80 are NC for ×32 Alliance Semiconductor AS7C33256NTD32A AS7C33256NTD36A 80 DQPb/NC 79 DQb7 78 DQb6 77 V DDQ 76 V SSQ 75 DQb5 74 DQb4 73 DQb3 72 DQb2 71 V SSQ 70 V ...
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... R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can be stalled using the CEN=1, the clock enable input. The AS7C33256NTD36A and AS7C33256NTD32A operate with a 3.3V ± 5% power supply for the device core (V separate power supply (V ) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14× ...
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... SRAM is transitioning out of SNOOZE MODE. 11/30/04, v. 2.1 ® or left floating, device follows Interleaved Burst DD is guaranteed after the time t is met. After entering SNOOZE MODE, all inputs SB2 ZZI , only a DESELECT or READ cycle should be given while PUS Alliance Semiconductor AS7C33256NTD32A AS7C33256NTD36A . The SB2 ...
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... External NOP/WRITE ABORT (Begin Burst) High Next Current enables WRITEs to byte “b” (DQb pins/balls); Alliance Semiconductor AS7C33256NTD32A AS7C33256NTD36A ...
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... D I OUT T stg T bias Symbol Min V 3.135 DD V 3.135 DDQ Vss 0 Symbol Min V 3.135 DD V 2.375 DDQ Vss 0 Alliance Semiconductor AS7C33256NTD32A AS7C33256NTD36A Burst Dsel Burst Burst Min Max Unit –0.5 +4.6 –0 0.5 DD –0 0.5 DDQ – 1.8 W – –65 +150 o –65 +150 ...
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... All V – 0.2V, Deselected < Max Deselected < 0.2V, I SB1 ≤ 0.2V or ≥ V all ≥ V Deselected Max I SB2 ≤ ≥ V all Alliance Semiconductor AS7C33256NTD32A AS7C33256NTD36A Min Max -2 2 < OUT DDQ * +0.3 DDQ ** -0.3 0.8 ** -0.5 0.8 2.4 – ...
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... WS t 1.5 – CSS t 0.5 – 0.5 – 0.5 – 0.5 – CSH t 1.5 – CENS t 0.5 – CENH t 1.5 – ADVS t 0.5 – ADVH Alliance Semiconductor AS7C33256NTD32A AS7C33256NTD36A –133 1 Min Max Unit Notes – 133 MHz 7.5 – ns – 4.0 ns – 4 – ns 2,3,4 1.5 – – ns 2,3,4 – 4.0 ns 2,3,4 – 4.0 ns 2,3,4 0 – ...
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... CSH t 1.7 – CENS t 0.7 – CENH t 1.7 – ADVS t 0.7 – ADVH Conditions Symbol ZZ > SB2 t PDS t PUS t ZZI t RZZI Alliance Semiconductor AS7C33256NTD32A AS7C33256NTD36A –133 1 Min Max Unit Notes – 133 MHz 7.5 – ns – 4.2 ns – 4 – ns 2,3,4 1.5 – – ns 2,3,4 – 4.0 ns 2,3,4 – ...
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... Falling input HZOE OE Q(A1) Q(A2) Q(A2Y‘01) Read Continue Continue Continue Q(A2) Read Read Q(A2Y‘10) Q(A2Y‘01) Q(A2Y‘11) Alliance Semiconductor AS7C33256NTD32A AS7C33256NTD36A Undefined t CYC A3 Q(A2Y‘10) Q(A3) Q(A2Y‘11) Continue Inhibit Read Read Read Clock Q(A3) Q(A3Y‘01 HLZC ...
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... Dout Q(n-2) Q(n-1) Write DSEL D(A1) 11/30/04, v. 2.1 ® D(A1) D(A2) D(A2Y‘01) Write Continue Continue Continue D(A2) Write Write Write D(A2Y‘10) D(A2Y‘01) D(A2Y‘11) Alliance Semiconductor AS7C33256NTD32A AS7C33256NTD36A t CYC D(A3) D(A2Y‘10) D(A2Y‘11) Continue Inhibit Write Write Clock D(A3) D(A3Y‘01 ...
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... Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low. BW[a:d] is don’t care. 11/30/04, v. 2.1 ® LZC OH D(A1) D(A2) Q(A3) D(A2Ý01) Burst Burst Read Read Write Q(A3) Read Q(A4) D(A2Ý01) Q(A4Ý01) Alliance Semiconductor AS7C33256NTD32A AS7C33256NTD36A t CYC HZC D(A5) Q(A6) Q(A4) Q(A4Ý01) t HZOE t LZOE Write Read Write D(A5) Q(A6) D(A7 DSEL ...
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... Command Read Burst Q(A1) Q(A1Ý01) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low low. 11/30/04, v. 2.1 ® A2 Q(A1Ý01) Q(A1) Q(A1Ý10) STALL DSEL Burst Burst Q(A1Ý10) DSEL Alliance Semiconductor AS7C33256NTD32A AS7C33256NTD36A A3 D(A2) Burst Write Write Burst NOP NOP D(A2) D(A2Ý10) D(A2Ý01) D(A3 ...
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... High-Z see Figure C. Ω Ω =1.5V out L 30 pF* Figure B: Output load (A) Alliance Semiconductor AS7C33256NTD32A AS7C33256NTD36A t PUS ZZ recovery cycle Normal operation Cycle Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O 319Ω/1667Ω D OUT 5 pF* 353Ω/1538Ω GND *including scope and jig capacitance Figure C: Output load(B) P ...
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... CLK. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled. Alliance Semiconductor AS7C33256NTD32A AS7C33256NTD36A = Figure C. L measured as low below VIL CL ...
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... Package Dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.80 14.20 E 19.80 20.20 e 0.65 nominal c Hd 15.80 16.20 He 21.80 22.20 L 0.45 0.75 L1 1.00 nominal α 0° 7° Dimensions in millimeters 11/30/04, v. 2.1 ® α Alliance Semiconductor AS7C33256NTD32A AS7C33256NTD36A ...
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... C = commercial ( 0° 70° C industrial ( -40 ° 85° Lead free part 11/30/04, v. 2.1 ® 166 MHz AS7C33256NTD32A -166TQC AS7C33256NTD32A -166TQI AS7C33256NTD36A -166TQC AS7C33256NTD36A -166TQI NTD 32/ Alliance Semiconductor AS7C33256NTD32A AS7C33256NTD36A 133 MHz AS7C33256NTD32A -133TQC AS7C33256NTD32A -133TQI AS7C33256NTD36A -133TQC AS7C33256NTD36A -133TQI –XXX TQ C ...
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... Alliance products in such life- supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS7C33256NTD32A AS7C33256NTD36A ® Copyright © Alliance Semiconductor All Rights Reserved Part Number:AS7C33256NTD36A AS7C33256NTD32A Document Version: v. 2.1 ...