DS2155 Dallas Semiconductor, DS2155 Datasheet
DS2155
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DS2155 Summary of contents
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... UTOPIA/TDM backplane interface, and is controlled by an 8-bit parallel port configured for Intel or Motorola bus operations. The DS2156 is pin and software compatible with the DS2155. The LIU is composed of transmit and receive interfaces and a jitter attenuator. The transmit interface is responsible for generating the necessary ...
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MAIN FEATURES........................................................................................................................................8 2. DETAILED DESCRIPTION......................................................................................................................11 2 ...........................................................................................................................................13 LOCK IAGRAM F 2- IGURE LOCK IAGRAM F 2- IGURE ECEIVE AND RANSMIT F 2- IGURE ECEIVE AND RANSMIT F 2- IGURE ...
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RANSMIT RANSPARENCY 8.3 AIS-CI RAI-CI G AND ENERATION AND 8 ECEIVE IDE IGITAL T 8- ABLE LARM RITERIA 9. E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS..............................................61 9 ...
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CHANNEL BLOCKING REGISTERS ..................................................................................................107 18. ELASTIC STORES OPERATION..........................................................................................................110 18 ..........................................................................................................................................113 ECEIVE IDE 18.1.1 T1 Mode ..............................................................................................................................................113 18.1.2 E1 Mode..............................................................................................................................................113 18 .......................................................................................................................................113 RANSMIT IDE 18.2.1 T1 Mode ..............................................................................................................................................114 18.2.2 E1 Mode..............................................................................................................................................114 18 LASTIC ...
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Transmit Open-Circuit Detector.........................................................................................................151 23.3.3 Transmit BPV Error Insertion ............................................................................................................151 23.3.4 Transmit G.703 Synchronization Signal (E1 Mode)...........................................................................151 23.4 MCLK P .................................................................................................................................152 RESCALER 23 ITTER TTENUATOR 23.6 CMI ( ODE ARK NVERSION F 23-2. CMI C ..................................................................................................................................152 ...
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BERT FUNCTION....................................................................................................................................200 26.1 S ....................................................................................................................................................200 TATUS 26.2 M .................................................................................................................................................200 APPING F 26- IGURE IMPLIFIED IAGRAM OF F 26- IGURE IMPLIFIED IAGRAM OF 26.3 BERT R D EGISTER ESCRIPTIONS 26.4 BERT R P EPETITIVE ATTERN 26.5 ...
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F 34- IGURE ECEIVE IDE F 34- ESF T IGURE ECEIVE IDE F 34- IGURE ECEIVE IDE F 34- 1.544MH IGURE ECEIVE IDE F 34- 2.048MH IGURE ...
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... Intel or Motorola § IEEE 1149.1 JTAG-Boundary Scan § 3.3V supply with 5V tolerant inputs and outputs § Pin compatible with DS2155, DS2152/DS2154, and DS21x5Y SCT family § Signaling System 7 Support § RAI-CI, AIS-CI support § 100-pin LQFP package (14mm x 14mm) (DS2156) § ...
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Flexible signaling support – Software or hardware based – Interrupt generated on change of signaling data – Receive signaling freeze on loss-of-sync, carrier loss, or frame slip § Addition of hardware pins to indicate carrier loss and signaling freeze ...
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Extended System Information Bus § Host can read interrupt and alarm status ports with a single bus read User-Programmable Output Pins § Four user-defined output pins for controlling external logic The DS2156 is compliant with the ...
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... DS2156 is composed of an LIU, framer, HDLC controllers, and a UTOPIA/TDM backplane interface, and is controlled by an 8-bit parallel port configured for Intel or Motorola bus operations. The DS2156 is pin and software compatible with the DS2155. The LIU is composed of transmit and receive interfaces and a jitter attenuator. The transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used ...
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Reader’s Note: This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125ms frame there are 24 8-bit channels plus a framing bit assumed that the framing bit is sent first followed by channel ...
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Block Diagram Figure 2-1 shows a simplified block diagram featuring the major components of the DS2156. Details are shown in subsequent figures. About 30 device pins have dual functions depending on the selection of the backplane, UTOPIA, or TDM. ...
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Figure 2-2. Receive and Transmit LIU (TDM Backplane Enabled) 32.768MHz RRING RTIP TRING TTIP VCO / PLL MUX 14 of 262 RCL MUX JACLK RPOS RNEG RCLK TPOS TNEG TCLK ...
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Figure 2-3. Receive and Transmit LIU (UTOPIA Backplane Enabled) 32.768MHz RRING RTIP TRING TTIP VCO / PLL 15 of 262 RCL JACLK RPOS RNEG RCLK TPOS TNEG TCLK ...
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Figure 2-4. Receive and Transmit Framer/HDLC RPOS RNEG RCLK TPOS TNEG TCLK REC HDLC #1 128 Byte FIFO MAPPER DATA RECEIVE CLOCK FRAMER SYNC SYNC TRANSMIT CLOCK FRAMER DATA MAPPER XMIT HDLC #1 128 Byte FIFO 16 of 262 REC ...
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Figure 2-5. Backplane Interface (TDM Backplane Enabled) DATA CLOCK SYNC SYNC Sa/FDL DATA INSERT CLOCK JACLK Sa BIT/FDL EXTRACTION SIGNALING BUFFER ELASTIC STORE CHANNEL TIMING SIGNALING BUFFER ELASTIC STORE CHANNEL TIMING TCLK MUX 17 of 262 RLINK RLCLK RSIG RSIGFR ...
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Figure 2-6. Backplane Interface (UTOPIA Bus Enabled) RCLK RCHCLK RECEIVE DATA FRAMER INTERFACE SYNC LOOPBACK TCHCLK TRANSMIT DATA DATA FRAMER INTERFACE SYNC TCLK CONTROL CELL SCRAMBLING STORAGE UTOPIA BUS & RATE FIFO INTERFACE DECOUPLING CONTROL CELL TRANSMIT SCRAMBLING STORAGE UTOPIA ...
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PIN FUNCTION DESCRIPTION The DS2156 has a user-selectable TDM or UTOPIA backplane. Table 3-A and Table 3-B indicate which pins have alternate functions depending on the backplane selected. Note that even when the UTOPIA backplane is selected, the basic ...
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Signal Name: TLCLK Signal Description: Transmit Link Clock Signal Type: Output Demand clock for the transmit link data [TLINK] input. T1 Mode: A 4kHz or 2kHz (ZBTSI) clock. E1 Mode: A 4kHz to 20kHz clock. Signal Name: TLINK Signal Description: ...
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Signal Name: TPOSO Signal Description: Transmit Positive-Data Output Signal Type: Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. Can be programmed to source NRZ data by the output data format (IOCR1.0) ...
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Receive Side Signal Name: RLINK Signal Description: Receive Link Data Signal Type: Output T1 Mode: Updated with either FDL data (ESF bits (D4 bits (ZBTSI) one RCLK before the start of a frame. E1 Mode: ...
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Signal Name: RMSYNC Signal Description: Receive Multiframe Sync Signal Type: Output An extracted pulse, one RCLK wide (elastic store disabled) or one RSYSCLK wide (elastic store enabled), is output at this pin that identifies multiframe boundaries. Signal Name: RDATA Signal ...
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Signal Name: RPOSO Signal Description: Receive Positive-Data Output Signal Type: Output Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally connected to RPOSI. Signal Name: RNEGO Signal Description: Receive Negative-Data ...
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UTOPIA Bus 3.2.1 Receive Side Signal Name: UR-ADDR0 to UR-ADDR4 Signal Description: Receive UTOPIA Address Signal Type: Input 5-bit UTOPIA address bus driven from ATM layer to select the appropriate UTOPIA port. RX_UTOP_ADDR4 is the MSB; RX_UTOP_ADDR0 is the ...
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Transmit Side Signal Name: UT-ADDR0 to UT-ADDR4 Signal Description: Transmit UTOPIA Address Signal Type: Input This 5-bit wide bus is driven by the ATM layer to poll and select the appropriate UTOPIA port. UT-ADDR4 is the MSB; UT-ADDR0 is ...
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Parallel Control Port Pins INT Signal Name: Signal Description: Interrupt Signal Type: Output Flags host controller during conditions and events defined in the status registers. Active-low, open-drain output. Signal Name: TSTRST Signal Description: Three-State Control and Device Reset Signal ...
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CS Signal Name: Signal Description: Chip Select Signal Type: Input Must be low to read or write to the device active-low signal. Signal Name: ALE(AS)/A7 Signal Description: Address Latch Enable (Address Strobe Signal Type: Input ...
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User Output Port Pins Signal Name: UOP0 Signal Description: User Output Port 0 Signal Type: Output This output port pin can be set low or high by the CCR4.0 control bit. This pin is forced low on power-up and ...
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JTAG Test Access Port Pins Signal Name: JTRST Signal Description: IEEE 1149.1 Test Reset Signal Type: Input JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to high. This ...
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Line Interface Pins Signal Name: MCLK Signal Description: Master Clock Input Signal Type: Input A (50ppm) clock source is applied at this pin. This clock is used internally for both clock/data recovery and for the jitter attenuator for T1 ...
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Supply Pins Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 3.3V ±5%. Should be connected to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal Type: Supply 3.3V ±5%. Should ...
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L and G Package Pinout The DS2156 is available in either a 100-pin LQFP (L) or 10mm CSBGA, 0.8mm pitch (G) package. Table 3-A. Pin Description Sorted by Pin Number (TDM Backplane Enabled) BOLD entries indicate pins that have ...
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PIN LQFP CSBGA K10 J10 H10 F10 E10 ...
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Table 3-B. Pin Description Sorted by Pin Number (UTOPIA Backplane Enabled) BOLD entries indicate pins that have an alternate function when the TDM bus interface is enabled. PIN LQFP CSBGA ...
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PIN LQFP CSBGA 49 K9 UT-UTDO K10 UT-DATA7 J10 H10 F10 E10 ...
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CSBGA Pin Configuration Figure 3-1. 10mm CSBGA Pin Configuration (TDM Signals Shown RLOS/ RCHBLK RFSYNC LOTC B JTCLK JTMS RSYSCLK C JTDI RCL BPCLK D JTDO UOP1 UOP0 E 8XCLK LIUC BTS F RTIP ...
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PARALLEL PORT The SCT is controlled by either a nonmultiplexed (MUX = multiplexed (MUX = 1) bus through an external microcontroller or microprocessor. The SCT can operate with either Intel or Motorola bus timing configurations. If ...
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ADDRESS R/W xxh 25 R/W Interrupt Mask Register 8 26 R/W Status Register 9 27 R/W Interrupt Mask Register 9 28 R/W Per-Channel Pointer Register 29 W Per-Channel Data Register Per-Channel Data Register Per-Channel ...
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ADDRESS R/W xxh 54 R/W Transmit Signaling Register 5 55 R/W Transmit Signaling Register 6 56 R/W Transmit Signaling Register 7 57 R/W Transmit Signaling Register 8 58 R/W Transmit Signaling Register 9 59 R/W Transmit Signaling Register 10 5A ...
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ADDRESS R/W xxh 83 R/W Transmit Idle Code Enable Register 4 84 R/W Receive Idle Code Enable Register 1 85 R/W Receive Idle Code Enable Register 2 86 R/W Receive Idle Code Enable Register 3 87 R/W Receive Idle Code ...
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ADDRESS R/W xxh B2 R Extend System Information Bus Register Extend System Information Bus Register Extend System Information Bus Register Extend System Information Bus Register 4 B6 R/W In-Band Code Control ...
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ADDRESS R/W xxh E1 R/W BERT Control Register BERT Bit Count Register BERT Bit Count Register BERT Bit Count Register BERT Bit Count Register ...
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UTOPIA Bus Registers When the UTOPIA bus is enabled, register space 50h–6A is mapped to the UTOPIA function. Table 4-B. UTOPIA Register Map ADDRESS R/W xxh 50 R/W Transmit Configuration Register 51 R/W Transmit PMON Counter-Latch Enable Register 52 ...
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SPECIAL PER-CHANNEL REGISTER OPERATION Some of the features described in the data sheet that operate on a per-channel basis use a special method for channel selection. There are five registers involved: per-channel pointer register (PCPR) and per- channel data ...
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Register Name: PCDR1 Register Description: Per-Channel Data Register 1 Register Address: 29h Bit # 7 6 Name — — Default CH8 CH7 Register Name: PCDR2 Register Description: Per-Channel Data Register 2 Register Address: 2Ah Bit # 7 6 Name — ...
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PROGRAMMING MODEL The DS2156 register map is divided into three groups: T1 specific features, E1 specific features, and common features. The typical programming sequence begins with issuing a reset to the DS2156, selecting operation in the ...
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Power-Up Sequence The DS2156 contains an on-chip power-up reset function that automatically clears the writeable register space immediately after power is supplied to the DS2156. The user can issue a chip reset at any time. Issuing a reset disrupts ...
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Interrupt Handling Various alarms, conditions, and events in the DS2156 can cause interrupts. For simplicity, these are all referred to as events in this explanation. All status registers can be programmed to produce interrupts. Each status register has an ...
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For example, SR2 has a bit that is set when the device goes into a loss-of-sync state (SR2.0, a condition bit) and a bit that is set (SR2.4, an event bit) when the loss-of-sync condition clears (goes in sync). ...
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CLOCK MAP Figure 7-1 shows the clock map of the DS2156. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator, which can ...
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T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS The T1 framer portion of the DS2156 is configured through a set of nine control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2156 ...
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Register Name: T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 04h Bit # 7 6 Name — RFM Default 0 0 Bit 0/Receive-Side D4 Yellow Alarm Select (RD4YM bit 2 of all channels 1 ...
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Register Name: T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 05h Bit # 7 6 Name TJC TFPT Default 0 0 Bit 0/Transmit Yellow Alarm (TYEL not transmit yellow alarm 1 = transmit yellow alarm ...
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Register Name: T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 06h Bit # 7 6 Name TB8ZS TSLC96 Default 0 0 Bit 0/Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS stuffing occurs 1 = bit 7 forced ...
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Register Name: T1CCR1 Register Description: T1 Common Control Register 1 Register Address: 07h Bit # 7 6 Name — — Default 0 0 Bit 0/Transmit Loop-Code Enable (TLOOP). See Section 25 for details transmit data normally 1 = ...
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T1 Transmit Transparency The software signaling insertion-enable registers, SSIE1–SSIE4, can be used to select signaling insertion from the transmit signaling registers, TS1–TS12 per-channel basis. Setting a bit in the SSIEx register allows signaling data to be sourced ...
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T1 Receive-Side Digital-Milliwatt Code Generation Receive-side digital-milliwatt code generation involves using the receive digital-milliwatt registers (T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be overwritten with a digital-milliwatt pattern. ...
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Register Name: INFO1 Register Description: Information Register 1 Register Address: 10h Bit # 7 6 Name RPDV TPDV Default 0 0 Bit 0/Frame Bit-Error Event (FBE). Set when an Ft (D4) or FPS (ESF) framing bit is received in error. ...
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Table 8-A. T1 Alarm Criteria ALARM Blue Alarm (AIS) (Note 1) Yellow Alarm (RAI) D4 Bit 2 Mode (T1RCR2 12th F-Bit Mode (T1RCR2 this mode is also referred to as the “Japanese Yellow Alarm”) ESF ...
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E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS The E1 framer portion of the DS2156 is configured by a set of four control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2156 ...
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Table 9-A. E1 Sync/Resync Criteria FRAME OR MULTIFRAME SYNC CRITERIA LEVEL FAS present in frame N and FAS FAS not present in frame Two valid MF alignment CRC4 words found within 8ms Valid MF ...
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Register Name: E1TCR1 Register Description: E1 Transmit Control Register 1 Register Address: 35h Bit # 7 6 Name TFPT T16S Default 0 0 Bit 0/Transmit CRC4 Enable (TCRC4 CRC4 disabled 1 = CRC4 enabled Bit 1/Transmit G.802 Enable ...
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Register Name: E1TCR2 Register Description: E1 Transmit Control Register 2 Register Address: 36h Bit # 7 6 Name Sa8S Sa7S Default 0 0 Bit 0/Automatic Remote Alarm Generation (ARA disabled 1 = enabled Bit 1/Automatic AIS Generation (AAIS) ...
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Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is enabled (E1TCR2.1 = 1), the device monitors the receive-side framer to determine if any of the following conditions are ...
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E1 Information Registers Register Name: INFO3 Register Description: Information Register 3 Register Address: 12h Bit # 7 6 Name — — Default 0 0 Bit 0/CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words ...
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Table 9-B. E1 Alarm Criteria ALARM SET CRITERIA An RLOS condition exists on power-up prior to initial synchronization, when a RLOS resync criteria has been met, or when a manual resync has been initiated by E1RCR1.0 RCL 255 or 2048 ...
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COMMON CONTROL AND STATUS REGISTERS Register Name: CCR1 Register Description: Common Control Register 1 Register Address: 70h Bit # 7 6 Name MCLKS CRC4R Default 0 0 Bit 0/Function of the RLOS/LOTC Output (RLOSF receive loss of ...
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Register Name: IDR Register Description: Device Identification Register Register Address: 0Fh Bit # 7 6 Name ID7 ID6 Default 1 1 Bits 0 to 3/Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to ...
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Register Name: IMR2 Register Description: Interrupt Mask Register 2 Register Address: 19h Bit # 7 6 Name RYELC RUA1C Default 0 0 Bit 0/Receive Loss-of-Sync Condition (RLOS interrupt masked 1 = interrupt enabled—interrupts on rising edge only Bit ...
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Register Name: SR3 Register Description: Status Register 3 Register Address: 1Ah Bit # 7 6 Name LSPARE LDN Default 0 0 Bit 0/Receive Remote Alarm Condition (RRA) (E1 Only). Set when a remote alarm is received at RPOSI and RNEGI. ...
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Register Name: IMR3 Register Description: Interrupt Mask Register 3 Register Address: 1Bh Bit # 7 6 Name LSPARE LDN Default 0 0 Bit 0/Receive Remote Alarm Condition (RRA interrupt masked 1 = interrupt enabled—interrupts on rising and falling ...
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Register Name: SR4 Register Description: Status Register 4 Register Address: 1Ch Bit # 7 6 Name RAIS-CI RSAO Default 0 0 Bit 0/Receive Align Frame Event (RAF) (E1 Only). Set every 250µs at the beginning of align frames. Used to ...
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Register Name: IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Dh Bit # 7 6 Name RAIS-CI RSAO Default 0 0 Bit 0/Receive Align Frame Event (RAF interrupt masked 1 = interrupt enabled Bit 1/Receive CRC4 Multiframe ...
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I/O PIN CONFIGURATION OPTIONS Register Name: IOCR1 Register Description: I/O Configuration Register 1 Register Address: 01h Bit # 7 6 Name RSMS RSMS2 Default 0 0 Bit 0/Output Data Format (ODF bipolar data at TPOSO and TNEGO ...
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Register Name: IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h Bit # 7 6 Name RCLKINV TCLKINV Default 0 0 Bit 0/RSYSCLK Mode Select (RSCLKM RSYSCLK is 1.544MHz RSYSCLK is 2.048MHz or ...
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LOOPBACK CONFIGURATION Register Name: LBCR Register Description: Loopback Control Register Register Address: 4Ah Bit # 7 6 Name — — Default 0 0 Bit 0/Framer Loopback (FLB). This loopback is useful in testing and debugging applications. In FLB, the ...
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Bit 3/Local Loopback (LLB). In this loopback, data continues to be transmitted as normal through the transmit side of the SCT. Data being received at RTIP and RRING are replaced with the data being transmitted. Data in this loopback passes ...
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Per-Channel Loopback The per-channel loopback registers (PCLRs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or, i.e., off of the line. If this loopback is enabled, ...
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Register Name: PCLR3 Register Description: Per-Channel Loopback Enable Register 3 Register Address: 4Dh Bit # 7 6 Name CH24 CH23 Default 0 0 Bits 0 to 7/Per-Channel Loopback Enable for Channels (CH17 to CH24 loopback ...
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ERROR COUNT REGISTERS The DS2156 contains four counters that are used to accumulate line-coding errors, path errors, and synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62ms (E1 mode only), or manual. See Error-Counter Configuration ...
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Line-Code Violation Count Register (LCVCR) 13.1.1 T1 Operation T1 code violations are defined as bipolar violations (BPVs) or excessive 0s. If the B8ZS mode is set for the receive side, then B8ZS codewords are not counted. This counter is ...
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Register Name: LCVCR1 Register Description: Line-Code Violation Count Register 1 Register Address: 42h Bit # 7 6 Name LCVC15 LCVC14 Default 0 0 Bits 0 to 7/Line-Code Violation Counter Bits (LCVC8 to LCVC15). LCV15 is the MSB ...
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Path Code Violation Count Register (PCVCR) 13.2.1 T1 Operation The path code violation count register records Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to operate in the T1 ESF ...
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Frames Out-of-Sync Count Register (FOSCR) 13.3.1 T1 Operation The FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is useful in ESF applications needing to measure the parameters loss-of-frame ...
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E-Bit Counter (EBCR) This counter is only available in E1 mode. E-bit count register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 16-bit counter that records far-end block errors (FEBE) as ...
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DS0 MONITORING FUNCTION The DS2156 has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel ...
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Register Name: RDS0SEL Register Description: Receive Channel Monitor Select Register Address: 76h Bit # 7 6 Name — — Default 0 0 Bits 0 to 4/Receive Channel Monitor Bits (RCM0 to RCM4). RCM0 is the LSB of a 5-bit channel ...
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SIGNALING OPERATION There are two methods to access receive signaling data and provide transmit signaling data, processor- based (software-based) or hardware-based. Processor-based refers to access through the transmit and receive signaling registers RS1–RS16 and TS1–TS16. Hardware-based refers to the ...
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Hardware-Based Receive Signaling In hardware-based signaling the signaling data can be obtained from the RSER pin or the RSIG pin. RSIG is a signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The signaling data, T1 ...
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Register Name: SIGCR Register Description: Signaling Control Register Register Address: 40h Bit # 7 6 Name GRSRE — Default 0 0 Bit 0/Force Receive Signaling All Ones (FRSAO mode, this bit forces all signaling data at the RSIG ...
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Register Name: RS1 to RS12 Register Description: Receive Signaling Registers (T1 Mode, ESF Format) Register Address: 60h to 6Bh (MSB) CH2-A CH2-B CH2-C CH4-A CH4-B CH4-C CH6-A CH6-B CH6-C CH8-A CH8-B CH8-C CH10-A CH10-B CH10-C CH12-A CH12-B CH12-C CH14-A CH14-B ...
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Register Name: RS1 to RS16 Register Description: Receive Signaling Registers (E1 Mode, CAS Format) Register Address: 60h to 6Fh (MSB CH2-A CH2-B CH2-C CH4-A CH4-B CH4-C CH6-A CH6-B CH6-C CH8-A CH8-B CH8-C CH10-A CH10-B CH10-C CH12-A CH12-B ...
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Register Name: RSCSE1, RSCSE2, RSCSE3, RSCSE4 Register Description: Receive Signaling Change-of-State Interrupt Enable Register Address: 3Ch, 3Dh, 3Eh, 3Fh (MSB) CH8 CH7 CH6 CH16 CH15 CH14 CH24 CH23 CH22 CH30 Setting any of the CH1–CH30 bits in the RSCSE1–RSCSE4 registers ...
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Transmit Signaling Figure 15-2. Simplified Diagram of Transmit Signaling Path T1/E1 DATA STREAM ONLY APPLIES TO T1 MODE 15.2.1 Processor-Based Mode In processor-based mode, signaling data is loaded into the transmit signaling registers (TS1–TS16) by the host interface. On ...
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E1 Mode In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common channel signaling) or CAS (channel associated signaling) format. The 32 time slots are referenced by two different channel number schemes in ...
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Register Name: TS1 to TS16 Register Description: Transmit Signaling Registers (E1 Mode, CAS Format) Register Address: 50h to 5Fh (MSB CH2-A CH2-B CH2-C CH4-A CH4-B CH4-C CH6-A CH6-B CH6-C CH8-A CH8-B CH8-C CH10-A CH10-B CH10-C CH12-A CH12-B ...
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Register Name: TS1 to TS12 Register Description: Transmit Signaling Registers (T1 Mode, ESF Format) Register Address: 50h to 5Bh (MSB) CH2-A CH2-B CH2-C CH4-A CH4-B CH4-C CH6-A CH6-B CH6-C CH8-A CH8-B CH8-C CH10-A CH10-B CH10-C CH12-A CH12-B CH12-C CH14-A CH14-B ...
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Software Signaling Insertion-Enable Registers, E1 CAS Mode In E1 CAS mode, the CAS signaling alignment/alarm byte can be sourced from the transmit signaling registers along with the signaling data. Register Name: SSIE1 Register Description: Software Signaling Insertion Enable 1 ...
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Register Name: SSIE3 Register Description: Software Signaling Insertion Enable 3 Register Address: 0Ah Bit # 7 6 Name CH22 CH21 Default 0 0 Bit 0/Lower CAS Align/Alarm Word (LCAW). Selects the lower CAS align/alarm bits (xyxx sourced from ...
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Software Signaling Insertion-Enable Registers, T1 Mode In T1 mode, only registers SSIE1–SSIE3 are used since there are only 24 channels frame. Register Name: SSIE1 Register Description: Software Signaling Insertion Enable 1 Register Address: 08h Bit # ...
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PER-CHANNEL IDLE CODE GENERATION Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. When operated in the T1 mode, only the first 24 channels are used by the DS2156, ...
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Idle-Code Programming Examples Example 1 Sets transmit channel 3 idle code to 7Eh. Write IAAR = 02h ;select channel 3 in the array Write PCICR = 7Eh ;set idle code to 7Eh Example 2 Sets transmit channels 3, 4, ...
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Register Name: IAAR Register Description: Idle Array Address Register Register Address: 7Eh Bit # 7 6 Name GRIC GTIC Default 0 0 Bits 0 to 5/Channel Pointer Address Bits (IAA0 to IAA5). These bits select the channel to be programmed ...
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The transmit-channel idle-code enable registers (TCICE1/2/3/4) are used to determine which of the channels from the backplane to the line should be overwritten with the code placed in the per-channel code array. ...
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The receive-channel idle-code enable registers (RCICE1/2/3/4) are used to determine which of the channels from the backplane to the line should be overwritten with the code placed in the per-channel code array. ...
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CHANNEL BLOCKING REGISTERS The receive channel blocking registers (RCBR1/RCBR2/RCBR3/RCBR4) and the transmit channel blocking registers (TCBR1/TCBR2/TCBR3/TCBR4) control RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low during ...
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Register Name: RCBR3 Register Description: Receive Channel Blocking Register 3 Register Address: 8Ah Bit # 7 6 Name CH24 CH23 Default 0 0 Bits 0 to 7/Receive Channels Channel Blocking Control Bits (CH17 to CH24 ...
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Register Name: TCBR1 Register Description: Transmit Channel Blocking Register 1 Register Address: 8Ch Bit # 7 6 Name CH8 CH7 Default 0 0 Bits 0 to 7/Transmit Channels Channel Blocking Control Bits (CH1 to CH8 ...
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ELASTIC STORES OPERATION The elastic store function is unavailable when UTOPIA backplane is enabled. The DS2156 contains dual two-frame elastic stores, one for the receive direction and one for the transmit direction. Both elastic stores are fully independent. The ...
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Register Name: ESCR Register Description: Elastic Store Control Register Register Address: 4Fh Bit # 7 6 Name TESALGN TESR Default 0 0 Bit 0/Receive Elastic Store Enable (RESE elastic store is bypassed 1 = elastic store is enabled ...
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Register Name: SR5 Register Description: Status Register 5 Register Address: 1Eh Bit # 7 6 Name — — Default 0 0 Bit 0/Receive Elastic Store Slip-Occurrence Event (RSLIP). Set when the receive elastic store has either repeated or deleted a ...
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Receive Side See the IOCR1 and IOCR2 registers for information about clock and I/O configurations. If the receive-side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the RSYSCLK pin. For higher ...
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T1 Mode If the user selects to apply a 2.048MHz clock to the TSYSCLK pin, then the data input at TSER is ignored every fourth channel. Therefore channels 13, 17, 21, 25, and 29 (time slots ...
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G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY) The DS2156 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSER already has the FAS/NFAS, CRC multiframe alignment word, and ...
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T1 BIT-ORIENTED CODE (BOC) CONTROLLER The DS2156 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. 20.1 Transmit BOC Bits ...
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Register Name: BOCC Register Description: BOC Control Register Register Address: 37h Bit # 7 6 Name — — Default 0 0 Bit 0/Send BOC (SBOC). Set = 1 to transmit the BOC code placed in bits ...
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Register Name: SR8 Register Description: Status Register 8 Register Address: 24h Bit # 7 6 Name — — Default 0 0 Bit 0/Receive BOC Detector Change-of-State Event (RBOC). Set whenever the BOC detector sees a change of state to a ...
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ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY) When operated in the E1 mode, the DS2156 provides three methods for accessing the Sa and the Si bits. The first method involves a hardware scheme that uses the RLINK/RLCLK ...
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Register Name: RAF Register Description: Receive Align Frame Register Register Address: C6h Bit # 7 6 Name Si 0 Default 0 0 Bit 0/Frame Alignment Signal Bit (1) Bit 1/Frame Alignment Signal Bit (1) Bit 2/Frame Alignment Signal Bit (0) ...
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Register Name: TAF Register Description: Transmit Align Frame Register Register Address: D0h Bit # 7 6 Name Si 0 Default 0 0 Bit 0/Frame Alignment Signal Bit (1) Bit 1/Frame Alignment Signal Bit (1) Bit 2/Frame Alignment Signal Bit (0) ...
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Method 3: Internal Register Scheme Based on CRC4 Multiframe The receive side contains a set of eight registers (RSiAF, RSiNAF, RRA, and RSa4–RSa8) that report the Si and Sa bits as they are received. These registers are updated with ...
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Register Name: RSiNAF Register Description: Received Si Bits of the Nonalign Frame Register Address: C9h Bit # 7 6 Name SiF15 SiF13 Default 0 0 Bit 0/Si Bit of Frame 1 (SiF1) Bit 1/Si Bit of Frame 3 (SiF3) Bit ...
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Register Name: RSa4 Register Description: Received Sa4 Bits Register Address: CBh Bit # 7 6 Name RSa4F15 RSa4F13 Default 0 0 Bit 0/Sa4 Bit of Frame 1 (RSa4F1) Bit 1/Sa4 Bit of Frame 3 (RSa4F3) Bit 2/Sa4 Bit of Frame ...
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Register Name: RSa6 Register Description: Received Sa6 Bits Register Address: CDh Bit # 7 6 Name RSa6F15 RSa6F13 Default 0 0 Bit 0/Sa6 Bit of Frame 1 (RSa6F1) Bit 1/Sa6 Bit of Frame 3 (RSa6F3) Bit 2/Sa6 Bit of Frame ...
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Register Name: RSa8 Register Description: Received Sa8 Bits Register Address: CFh Bit # 7 6 Name RSa8F15 RSa8F13 Default 0 0 Bit 0/Sa8 Bit of Frame 1 (RSa8F1) Bit 1/Sa8 Bit of Frame 3 (RSa8F3) Bit 2/Sa8 Bit of Frame ...
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Register Name: TSiNAF Register Description: Transmit Si Bits of the Nonalign Frame Register Address: D3h Bit # 7 6 Name TSiF15 TSiF13 Default 0 0 Bit 0/Si Bit of Frame 1 (TSiF1) Bit 1/Si Bit of Frame 3 (TSiF3) Bit ...
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Register Name: TSa4 Register Description: Transmit Sa4 Bits Register Address: D5h Bit # 7 6 Name TSa4F15 TSa4F13 Default 0 0 Bit 0/Sa4 Bit of Frame 1 (TSa4F1) Bit 1/Sa4 Bit of Frame 3 (TSa4F3) Bit 2/Sa4 Bit of Frame ...
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Register Name: TSa6 Register Description: Transmit Sa6 Bits Register Address: D7h Bit # 7 6 Name TSa6F15 TSa6F13 Default 0 0 Bit 0/Sa6 Bit of Frame 1 (TSa6F1) Bit 1/Sa6 Bit of Frame 3 (TSa6F3) Bit 2/Sa6 Bit of Frame ...
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Register Name: TSa8 Register Description: Transmit Sa8 Bits Register Address: D9h Bit # 7 6 Name TSa8F15 TSa8F13 Default 0 0 Bit 0/Sa8 Bit of Frame 1 (TSa8F1) Bit 1/Sa8 Bit of Frame 3 (TSa8F3) Bit 2/Sa8 Bit of Frame ...
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Register Name: TSACR Register Description: Transmit Sa Bit Control Register Register Address: DAh Bit # 7 6 Name SiAF SiNAF Default 0 0 Bit 0/Additional Bit 8 Insertion Control Bit (Sa8 not insert data from the TSa8 ...
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HDLC CONTROLLERS This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). Each HDLC controller has 128-byte ...
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Table 22-A. HDLC Controller Registers REGISTER CONTROL AND CONFIGURATION H1TC, HDLC #1 Transmit Control Register H2TC, HDLC #2 Transmit Control Register H1RC, HDLC #1 Receive Control Register H2RC, HDLC #2 Receive Control Register H1FC, HDLC #1 FIFO Control Register H2FC, ...
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Register Name: H1TC, H2TC Register Description: HDLC #1 Transmit Control HDLC #2 Transmit Control Register Address: 90h, A0h Bit # 7 6 Name NOFS TEOML Default 0 0 Bit 0/Transmit CRC Defeat (TCRCD). A 2-byte CRC code is automatically appended ...
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Register Name: H1RC, H2RC Register Description: HDLC #1 Receive Control HDLC #2 Receive Control Register Address: 31h, 32h Bit # 7 6 Name RHR RHMS Default 0 0 Bit 0/Receive SS7 Fill-In Signal Unit Delete (RSFD normal operation; ...
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FIFO Control The FIFO control register (HxFC) controls and sets the watermarks for the transmit and receive FIFOs. Bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark. When ...
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HDLC Mapping 22.3.1 Receive The HDLC controllers must be assigned a space in the T1/E1 bandwidth in which they transmit and receive data. The controllers can be mapped to either the FDL (T1), Sa bits (E1 channels. ...
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Register Name: H1RTSBS, H2RTSBS Register Description: HDLC # 1 Receive Time Slot Bits/Sa Bits Select HDLC # 2 Receive Time Slot Bits/Sa Bits Select Register Address: 96h, A6h Bit # 7 6 Name RCB8SE RCB7SE Default 0 0 Bit 0/Receive ...
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Transmit The HxTCS1–HxTCS4 registers are used to assign the transmit controllers to channels 1–24 (T1) or 1–32 (E1) according to the following table. Register Channels HxTCS1 1–8 HxTCS2 9–16 HxTCS3 17–24 HxTCS4 25–32 Register Name: H1TCS1, H1TCS2, H1TCS3, H1TCS4 ...
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Register Name: H1TTSBS, H2TTSBS Register Description: HDLC # 1 Transmit Time Slot Bits/Sa Bits Select HDLC # 2 Transmit Time Slot Bits/Sa Bits Select Register Address: 9Bh, ABh Bit # 7 6 Name TCB8SE TCB7SE Default 0 0 Bit 0/Transmit ...
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Register Name: SR6, SR7 Register Description: HDLC #1 Status Register 6 HDLC #2 Status Register 7 Register Address: 20h, 22h Bit # 7 6 Name — TMEND Default 0 0 Bit 0/Transmit FIFO Not Full Condition (TNF). Set when the ...
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Register Name: IMR6, IMR7 Register Description: HDLC # 1 Interrupt Mask Register 6 HDLC # 2 Interrupt Mask Register 7 Register Address: 21h, 23h Bit # 7 6 Name — TMEND Default 0 0 Bit 0/Transmit FIFO Not Full Condition ...
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Register Name: INFO5, INFO6 Register Description: HDLC #1 Information Register HDLC #2 Information Register Register Address: 2Eh, 2Fh Bit # 7 6 Name — — Default 0 0 Bits 0 to 2/Receive Packet Status (PS0 to PS2). These are real-time ...
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FIFO Information The transmit FIFO buffer-available register indicates the number of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the transmit ...
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HDLC FIFOs Register Name: H1TF, H2TF Register Description: HDLC # 1 Transmit FIFO HDLC # 2 Transmit FIFO Register Address: 9Dh, ADh Bit # 7 6 Name THD7 THD6 Default 0 0 Bit 0/Transmit HDLC Data Bit 0 (THD0). ...
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Receive HDLC Code Example The following is an example of a receive HDLC routine: Reset receive HDLC controller. 1) Set HDLC mode, mapping, and high watermark. 2) Start new message buffer. 3) Enable RPE and RHWM interrupts. 4) Wait ...
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Register Name: RFDL Register Description: Receive FDL Register Register Address: C0h Bit # 7 6 Name RFDL7 RFDL6 Default 0 0 The receive FDL register (RFDL) reports the incoming FDL or the incoming Fs bits. The LSB is received first. ...
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Transmit Section The transmit section shifts out into the T1 data stream either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the transmit FDL register (TFDL). When a new ...
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LINE INTERFACE UNIT (LIU) The LIU contains three sections: the receiver that handles clock and data recovery, the transmitter that waveshapes and drives the T1 line, and the jitter attenuator. These three sections are controlled by the line interface ...
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Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1 AMI/B8ZS waveform presented at the RTIP and RRING inputs. If the jitter attenuator is placed in the receive path (as ...
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Transmitter The DS2156 uses a phase-lock loop along with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the line. The waveforms created by the DS2156 meet the latest ETSI, ITU, ANSI, ...
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MCLK Prescaler A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz clock must be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specifications require an accuracy of ±32ppm for T1 ...
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LIU Control Registers Register Name: LIC1 Register Description: Line Interface Control 1 Register Address: 78h Bit # 7 6 Name L2 L1 Default 0 0 Bit 0/Transmit Power-Down (TPD powers down the transmitter and three-states the TTIP ...
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T1 Mode DSX-1 (0ft to 133ft) / 0dB CSU DSX-1 (133ft to 266ft DSX-1 (266ft to 399ft DSX-1 (399ft to 533ft DSX-1 ...
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Register Name: LIC3 Register Description: Line Interface Control 3 Register Address: 7Ah Bit # 7 6 Name — TCES Default 0 0 Bit 0/Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern (customer disconnect indication signal) at TTIP and ...
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Register Name: LIC4 Register Description: Line Interface Control 4 Register Address: 7Bh Bit # 7 6 Name CMIE CMII Default 0 0 Bits 0, 1/Receive Termination Select (RT0, RT1) RT1 RT0 Internal Receive-Termination Configuration 0 0 Internal receive-side termination disabled ...
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Register Name: INFO2 Register Description: Information Register 2 Register Address: 11h Bit # 7 6 Name BSYNC BD Default 0 0 Bits 0 to 3/Receive Level Bits (RL0 to RL3). Real-time bits RL3 RL2 RL1 ...
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Register Name: SR1 Register Description: Status Register 1 Register Address: 16h Bit # 7 6 Name ILUT TIMER Default 0 0 Bit 0/Loss of Line-Interface Transmit-Clock Condition (LOLITC). Set when TCLKI has not transitioned for one channel time. This is ...
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Register Name: IMR1 Register Description: Interrupt Mask Register 1 Register Address: 17h Bit # 7 6 Name ILUT TIMER Default 0 0 Bit 0/Loss-of-Transmit Clock Condition (LOLITC interrupt masked 1 = interrupt enabled—generates interrupts on rising and falling ...
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Recommended Circuits Figure 23-3. Basic Interface 2:1 TRANSMIT LINE RECEIVE LINE Note 1: All resistor values are ±1%. Note 2: Resistors R should be set to 60Ω each if the internal receive-side termination feature is enabled. When this feature ...
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Figure 23-4. Protected Interface Using Internal Receive Termination 2:1 F1 TRANSMIT LINE X2 F2 1:1 F3 RECEIVE LINE X1 F4 Note 1: All resistor values are ±1%. Note 2: X1 and X2 are very low DCR transformers. Note 3: C1 ...
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Component Specifications Table 23-A. Transformer Specifications SPECIFICATION Turns Ratio 3.3V Applications Primary Inductance Leakage Inductance Intertwining Capacitance Transmit Transformer DC Resistance Primary (Device Side) Secondary Receive Transformer DC Resistance Primary (Device Side) Secondary RECOMMENDED VALUE 1:1 (receive) and 1:2 ...
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Figure 23-5. E1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 Figure 23-6. T1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ...
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... Figure 23-7. Jitter Tolerance 1k 100 10 1 0.1 1 Figure 23-8. Jitter Tolerance (E1 Mode) 1k 100 0.1 1 DS2156 TOLERANCE TR 62411 (DEC. 90) ITU-T G.823 10 100 1k FREQUENCY (Hz) DS2155 TOLERANCE 1.5 MINIMUM TOLERANCE LEVEL AS PER ITU G.823 20 10 100 1k FREQUENCY (Hz) 164 of 262 10k 100k 0.2 2.4k 18k 10k 100k ...
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Figure 23-9. Jitter Attenuation (T1 Mode) 0dB -20dB -40dB -60dB 1 Figure 23-10. Jitter Attenuation (E1 Mode) 0dB -20dB -40dB -60dB 1 DS2156 T1 MODE 10 100 1K FREQUENCY (Hz) TBR12 Prohibited Area Prohibited Area DS2156 E1 MODE 10 100 ...
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Figure 23-11. Optional Crystal Connections Note 1: C1 and C2 should be 5pF lower than two times the nominal loading capacitance of the crystal to adjust for the input capacitance of the DS2156. DS2156 XTALD MCLK C1 C2 166 of ...
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UTOPIA BACKPLANE INTERFACE 24.1 Description The DS2156’s UTOPIA interface maps the ATM cells in a T1/E1 frame in the transmit direction as per ATM Forum Specifications af-phy-0016.000 [1] and af-phy-0064.000 [2] and recovers them in the receive direction from ...
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UTOPIA Clock Modes When the UTOPIA backplane is enabled, the user can select from several clocking modes: full T1/E1, clear-channel E1, or fractional T1/E1. Because ATM bytes are byte-aligned in the frame, clear-channel mode is only available in E1 ...
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Fractional T1/E1 mode In fractional T1/E1 mode, the framer is programmed to provide a gapped clock by setting CCR3.4 and CCR3 The gapped clocks are synchronous with RCLK and TCLK. The UTOPIA block is programmed to use ...
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Transmit Operation The DS2156 interface to the ATM layer is fully compliant to the ATM Forum’s UTOPIA Level 2 specification [3]. Either direct status or multiplexed with 1CLAV mode is supported. The DS2156 can be configured to use any ...
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Figure 24-2. Polling Phase and Selection Phase at Transmit Interface UT-CLK UT-ADDRx N+2 1F N-3 1F UT-CLAV N-3 N+2 UT-ENB UT-DATAx P35 P36 P37 P38 UT-SOC CELL XMIT TO: Note that the active PHY (PHY N) ...
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The example in Figure 24-3 shows where the transmission of cells though the transmit interface is stopped by the ATM PHY is ready to accept cells. Polling continues. Several clock cycles later one PHY gets ready to accept ...
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Figure 24-4 shows an example where the ATM must pause the data transmission, since it has no data available (in this case, for three clock cycles). This is done by deasserting UT-ENB and (optionally) setting UT-DATAx and UT-SOC into a ...
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Figure 24-5 shows an example of direct status for the transmit direction. Signals UT-CLAV[3:0] are associated to PHY port addresses #4, #3, #2, and #1. There is no need for a unique null device, thus “X = don’t care” represents ...
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Transmit Processing The DS2156 can optionally insert a valid HEC byte in the cell header can be programmed to transparently transmit the HEC byte from ATM layer. When inserting a valid HEC byte, COSET (0x55) addition can ...
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Receive Operation The receive interface of the DS2156 is fully compliant with the ATM Forum’s UTOPIA Level 2 specifications [3]. The DS2156 can be configured to use any address in the range its UTOPIA port ...
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The persistence of an out-of-cell delineation (OCD) event is integrated into loss-of-cell delineation (LCD), based on programmable integration time period (receive LCD integration-period register). If OCD persists for the programmed time, LCD is declared. LCD is deasserted only when cell ...
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HEC error correction is disabled, all HEC-errored cells are termed as uncorrectable HEC-errored cells. A 16-bit count of the number of cells that can be written into receive FIFO is maintained, which saturates at FFFFh. Note that, whether or not ...
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Figure 24-10 shows a case when, after the end of transmission of a cell from PHY N, no other PHY has a cell available. Therefore, UR-ENB remains asserted as the ATM assumes a cell-available from PHY N. With clock edge ...
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An example for the receive direction is shown in Figure 24-11. The status signals UR-CLAVx are associated to PHY port addresses #4, #3, #2, and #1. There is no need for a unique null device so “X = don’t care” ...
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Register Definitions The CCR2 register is used to configure the UTOPIA port address. The upper five bits of the CCR2 register contain the port address 0–31. The lower three bits are used for the backplane clock function. See Programmable ...
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Register Name: U_TPCL Register Description: UTOPIA Transmit PMON Counter Latch Register Register Address: 51h Bit # 7 6 Name — — Default 0 0 Bits 0 to 7/The host should always write 0x00 to this register when latching the PMON ...
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Register Name: U_TIUPB Register Description: UTOPIA Transmit Idle/Unassigned Payload Byte Register Register Address: 54h Bit # 7 6 Name TIUP7 TIUP6 Default 0 1 Bits 0 to 7/Transmit Idle/Unassigned Payload (TIUP0 to TIUP7). Holds the payload byte to be carried ...
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Register Name: U_TCR1 Register Description: UTOPIA Transmit Control Register 1 Register Address: 56h Bit # 7 6 Name — — Default 0 0 Bit 0/Transmit HEC-Insertion Enable (THIE HEC byte as received from ATM layer is transparently passed ...
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Register Name: U_TCR2 Register Description: UTOPIA Transmit Control Register 2 Register Address: 57h Bit # 7 6 Name — — Default 0 0 Bits 7/Unassigned, must be set to 0 for proper operation Bit 1/Transmit Physical-Layer Interface ...
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Register Name: U_RLCDIP Register Description: UTOPIA Receive LCD Integration Period Register Register Address: 61h Bit # 7 6 Name RLIP7 RLIP6 Default 0 1 Bits 0 to 7/Receive LCD Integration Period (RLIP0 to RLIP7) This 8-bit register holds the LCD ...
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Register Name: U_RCHEC Register Description: UTOPIA Receive Correctable HEC Counter Register Register Address: 63h Bit # 7 6 Name RCHC7 RCHC6 Default 0 0 Bits 0 to 7/Receive Correctable HEC Counter (RCHC0 to RCHC7) Note that write access to the ...
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Register Name: U_RACC1 Register Description: UTOPIA Receive-Assigned Cell Count Register 1 Register Address: 66h Bit # 7 6 Name RACC15 RACC14 Default 0 0 Bits0 to 7/Receive-Assigned Cell Count (RACC8 to RACC15) Register Name: U_RACC2 Register Description: ...
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Register Name: U_RSR Register Description: UTOPIA Receive Status Register Register Address: 68h Bit # 7 6 Name — — Default 0 0 Bit 0/Receive FIFO Overrun Interrupt Status (FOIS). Set if the receive FIFO overruns provided RxFIFO overrun interrupt mask ...
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Register Name: U_RCR1 Register Description: UTOPIA Receive Control Register 1 Register Address: 69h Bit # 7 6 Name — — Default 0 0 Bit 0/Receive COSET Subtraction Enable (RCSE DS2156 does not do COSET subtraction from the HEC ...
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Register Name: U_RCR2 Register Description: UTOPIA Receive Control Register 2 Register Address: 6Ah Bit # 7 6 Name — — Default 0 0 Bit 0/Diagnostic Loopback Enable (DLBE normal operation 1 = diagnostic loopback is enabled. In this ...
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Receive FIFO Overrun Receive FIFO overrun condition indicates that receive FIFO has been written with four cells before ATM layer reads the cells. The four cells that cause receive FIFO overrun conditions are intact in receive FIFO, and subsequent ...
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PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION The DS2156 has the ability to generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. To ...
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Register Name: IBCC Register Description: In-Band Code Control Register Register Address: B6h Bit # 7 6 Name TC1 TC0 Default 0 0 Bits 0 to 2/Receive Down-Code Length Definition Bits (RDN0 to RDN2) RDN2 RDN1 ...
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Register Name: TCD1 Register Description: Transmit Code-Definition Register 1 Register Address: B7h Bit # 7 6 Name C7 C6 Default 0 0 Bit 0/Transmit Code-Definition Bit 0 (C0). A don’t care if a 5-, 6-, or 7-bit length is selected. ...
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Register Name: RUPCD1 Register Description: Receive Up-Code Definition Register 1 Register Address: B9h Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Up-Code Definition Bits 0 (C0). A ...
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Register Name: RDNCD1 Register Description: Receive Down-Code Definition Register 1 Register Address: BBh Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Down-Code Definition Bit 0 (C0). A ...
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Register Name: RSCC Register Description: In-Band Receive Spare Control Register Register Address: BDh Bit # 7 6 Name — — Default 0 0 Bits 0 to 2/Receive Spare Code Length Definition Bits (RSC0 to RSC2) RSC2 RSC1 RSC0 0 0 ...
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Register Name: RSCD1 Register Description: Receive Spare-Code Definition Register 1 Register Address: BEh Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Spare-Code Definition Bit 0 (C0). A ...
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BERT FUNCTION The BERT block can generate and detect pseudorandom and repeating bit patterns used to test and stress data communication links, and it is capable of generating and detecting the following patterns: § The pseudorandom patterns ...