AS7C33512PFS36A-166TQC Alliance Semiconductor, AS7C33512PFS36A-166TQC Datasheet

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AS7C33512PFS36A-166TQC

Manufacturer Part Number
AS7C33512PFS36A-166TQC
Description
Manufacturer
Alliance Semiconductor
Datasheet
December 2004
Features
• Organization: 524,288 words × 32 or 36 bits
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.4/3.8 ns
• Fast OE access time: 3.4/3.8 ns
• Fully synchronous register-to-register operation
• Single-cycle deselect
• Asynchronous output enable control
• Available in 100-pin TQFP package
Logic block diagram
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
12/23/04, v 2.6
A[18:0]
3.3V 512K × 32/36 pipelined burst synchronous SRAM
ADSC
ADSP
GWE
BWE
CLK
BW
BW
BW
ADV
BW
CE0
CE1
CE2
OE
ZZ
d
c
b
a
Power
down
Alliance Semiconductor
19
D
CE
CLK
D
CLK
D
CLK
D
CLK
D
CLK
D
CE
CLK
D
CLK
CLK
CE
CLR
Byte write
Byte write
Byte write
Byte write
registers
registers
registers
registers
register
Address
register
Enable
register
delay
DQ
DQ
Enable
DQ
DQ
d
c
b
a
Q
Q
Q
Q
Q
Q
Burst logic
Q
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
LBO
19
Q0
Q1
®
17
19
CLK
OE
36/32
registers
Output
4
-166
166
300
3.4
90
60
6
512K × 32/36
Memory
DQ[a:d]
36/32
array
36/32
CLK
registers
Input
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33512PFS32A
AS7C33512PFS36A
-133
133
275
7.5
3.8
80
60
DDQ
1 of 19
Units
MHz
mA
mA
mA
ns
ns

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AS7C33512PFS36A-166TQC Summary of contents

Page 1

... CLK Byte write registers CLK D Q Enable CE register CLK CLK D Q Enable Power delay down register CLK Alliance Semiconductor AS7C33512PFS32A AS7C33512PFS36A DDQ 512K × 32/36 Memory array 36/32 36/ Output Input registers registers CLK 36/32 DQ[a:d] -166 -133 6 7.5 166 133 3.4 3.8 300 275 ...

Page 2

... PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD- Alliance Semiconductor AS7C33512PFS32A AS7C33512PFS36A Speed 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/ ...

Page 3

... DQd5 V 26 SSQ V 27 DDQ 28 DQd6 29 DQd7 30 NC/DQPd Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36 configuration. 12/23/04, v 2.6 ® TQFP 14 x 20mm Alliance Semiconductor AS7C33512PFS32A AS7C33512PFS36A 80 DQPb/NC 79 DQb7 78 DQb6 77 V DDQ 76 V SSQ 75 DQb5 74 DQb4 DQb3 73 ...

Page 4

... MHz bus frequencies. Three chip enable (CE) CD Test conditions Min OUT Conditions 1–layer 4–layer Alliance Semiconductor AS7C33512PFS32A AS7C33512PFS36A Max Unit Symbol Typical Units θ °C θ °C θ ...

Page 5

... DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. PUS 12/23/04, v 2.6 ® Description or left floating, device follows interleaved Burst order. When DD is guaranteed after the time t is met. After entering SNOOZE MODE, all inputs except ZZ is SB2 ZZI Alliance Semiconductor AS7C33512PFS32A AS7C33512PFS36A . The duration of SB2 ...

Page 6

... Starting Address First Increment Second Increment Third Increment Alliance Semiconductor AS7C33512PFS32A AS7C33512PFS36A Linear burst address (LBO = ...

Page 7

... Alliance Semiconductor AS7C33512PFS32A AS7C33512PFS36A CLK Operation Deselect Deselect Deselect Deselect Deselect External Begin read External Begin read External ...

Page 8

... Symbol Min Nominal V 3.135 3 3.135 3.3 DDQ Vss 0 0 Symbol Min Nominal V 3.135 3 2.375 2.5 DDQ Vss 0 0 Alliance Semiconductor AS7C33512PFS32A AS7C33512PFS36A Min Max Unit –0.5 +4.6 –0 0.5 DD –0 0.5 DDQ – 1.8 – –65 +150 –65 +135 Max Unit 3.465 V 3.465 V 0 ...

Page 9

... < Max IL Deselected < 0.2V, ≤ 0.2V or ≥ V all V – 0. ≥ V Deselected Max DD ≤ ≥ V all Alliance Semiconductor AS7C33512PFS32A AS7C33512PFS36A Min Max Unit -2 2 µA DD < µA DDQ +0.3 DDQ -0.3** 0.8 V -0.5** ...

Page 10

... ADSPS t 1.5 – ADSCS t 0.5 – ADVH t 0.5 – ADSPH t 0.5 – ADSCH Conditions Symbol ZZ > SB2 t PDS t PUS t ZZI t RZZI Alliance Semiconductor AS7C33512PFS32A AS7C33512PFS36A –133 1 Min Max Unit Notes – 133 MHz 7.5 – ns – 3.8 ns – 3 – ns 2,3,4 1.5 – – ns 2,3,4 – 3.8 ns 2,3,4 – ...

Page 11

... ADV inserts wait states HZOE t OH Q(A2) Q(A2Ý01) Q(A2Ý10) Read Burst Burst Suspend Burst Q(A2) Read Read Read Read Q(A 2Ý01 ) Q(A 2Ý10 ) Q(A 2Ý10 ) Q(A 2Ý11 ) Alliance Semiconductor AS7C33512PFS32A AS7C33512PFS36A Undefined A3 t HZC Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Read Burst Burst Burst Q(A3) Read Read Read DSEL Q(A 3Ý01 ) Q(A 3Ý10 ) Q(A 3Ý ...

Page 12

... CL ADSC LOADS NEW ADDRESS A2 ADV SUSPENDS BURST D(A2) D(A2Ý01) D(A2Ý01) D(A2Ý10) ADV Suspend Read Suspend Burst Write Q(A2) Write Write D D(A 2Ý01 ) D(A 2Ý01 ) D(A 2Ý10 ) Alliance Semiconductor AS7C33512PFS32A AS7C33512PFS36A t t ADSCS ADSCH ADVH ADVS D(A2Ý11) D(A3) D(A3Ý01) D(A3Ý10) ADV ADV ...

Page 13

... ADVH ADVS D(A2 HZOE LZOE t LZC Q(A1) Suspend Read Suspend Read Read Q(A2) Write Q(A3) Q(A1) D Alliance Semiconductor AS7C33512PFS32A AS7C33512PFS36A Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11) ADV ADV ADV Burst Burst Burst Read Read Read Q(A 3Ý01 ) Q(A 3Ý10 ) Q(A 3Ý ...

Page 14

... CSS CSH CE0,CE2 CE1 ADV LZOE Q(A1) Dout Din READ READ Q(A1) Q(A2) 12/23/04, v 2.6 ® t CYC HZOE Q(A2) Q(A3) Q(A4 D(A5) D(A6) READ READ WRITE Q(A3) Q(A4) D(A5) Alliance Semiconductor AS7C33512PFS32A AS7C33512PFS36A LZOE Q(A8 D(A7) READ WRITE WRITE READ Q(A9) D(A7) D(A6) Q(A8 Q(A9 ...

Page 15

... ZZ I supply S READ USPEND READ Q(A1) Q(A1) 12/23/04, v 2.6 ® HZC t PUS t PDS ZZ Recovery Cycle ZZ Setup Cycle t ZZI t RZZI I SB2 Sleep State Alliance Semiconductor AS7C33512PFS32A AS7C33512PFS36A t CYC D(A2) t HZOE D(A2(Ý01)) Normal Operation Mode READ USPEND Q(A2) WRITE TINUE D(A2) WRITE D( Ý01) ...

Page 16

... I/ DDQ for 2.5V I/O Figure B: Output load (A) at any given temperature and voltage. LZC is measured as low if below VIL. CL Alliance Semiconductor AS7C33512PFS32A AS7C33512PFS36A Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O 319Ω/1667Ω D OUT 5 pF* 353Ω/1538Ω /2 GND *including scope and jig capacitance ...

Page 17

... Package dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 L1 1.00 nominal α 0° 7° Dimensions in millimeters 12/23/04, v 2.6 ® Alliance Semiconductor AS7C33512PFS32A AS7C33512PFS36A α ...

Page 18

... Ordering information Package & Width AS7C33512PFS32A-166TQC TQFP x32 AS7C33512PFS32A-166TQI AS7C33512PFS36A-166TQC TQFP x36 AS7C33512PFS36A-166TQI Note: Add suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C33512PFS32A-166TQCN) Part numbering guide AS7C 33 512 1.Alliance Semiconductor SRAM prefix 2.Operating voltage 3.3V 3.Organization: 512 = 512K 4 ...

Page 19

... Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS7C33512PFS32A AS7C33512PFS36A ® Copyright © Alliance Semiconductor ...

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