ELANSC310-33KC Advanced Micro Devices, ELANSC310-33KC Datasheet
ELANSC310-33KC
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ELANSC310-33KC Summary of contents
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... Simultaneous multiple-voltage I/O pads operate at either 3 Core operates at 3.3 V for minimum power consumption. This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this product without notice. ...
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GENERAL DESCRIPTION The ÉlanSC310 microcontroller is a highly integrated, low-voltage, single-chip implementation of the Am386SXLV microprocessor plus most of the addi- tional logic needed for an AT-compatible personal com- puter ideal for embedded PC applications, such as point-of-sale ...
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BLOCK DIAGRAM IOR, IOW, MEMR, MEMW, BALE A20GATE, RC MCS16, IOCS16, 8042CS, SYSCLK IOCHRDY, 0WS Bus Controller PD15–PD0 PA23–PA0 Am386SXLV CONTROL LFX X32IN Management Clock Control Unit Generators X32OUT Real-Time Clock (146818A) Programmable Interval Timer (8254 ...
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... K É LANSC310 Valid Combinations ELANSC310–25 ELANSC310–33 ELANSC310–25 ELANSC310–33 ELANSC310–25 ELANSC310– TEMPERATURE RANGE C = Commercial ( Industrial (–40 C < T PACKAGE TYPE K = 208-lead QFP (Plastic Shrink Quad Flat Pack) (PQR-208) ...
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TABLE OF CONTENTS Distinctive Characteristics ............................................................................................................ 1 General Description ..................................................................................................................... 2 Customer Service ........................................................................................................................ 2 Block Diagram ............................................................................................................................. 3 Ordering Information .................................................................................................................... 4 Connection Diagram .................................................................................................................. 11 ÉlanSC310 Microcontroller Pin Designations ............................................................................ 12 Pin Designations (Sorted by Pin Number) ................................................................................. ...
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PPDWE [PPDCS].................................................................................................................. 33 PPOEN.................................................................................................................................. 33 SLCT ..................................................................................................................................... 33 SLCTIN ................................................................................................................................. 33 STRB..................................................................................................................................... 33 Serial Port Interface ................................................................................................................... 33 CTS ....................................................................................................................................... 33 DCD ...................................................................................................................................... 33 DSR....................................................................................................................................... 33 DTR/CFG1 ............................................................................................................................ 34 RIN ........................................................................................................................................ 34 RTS/CFG0 ............................................................................................................................ 34 SIN ........................................................................................................................................ 34 SOUT .................................................................................................................................... ...
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Reset and Power ....................................................................................................................... 37 AGND.................................................................................................................................... 37 AVCC .................................................................................................................................... 37 GND ...................................................................................................................................... 37 IORESET .............................................................................................................................. 37 RESIN ................................................................................................................................... 37 VCC....................................................................................................................................... 38 VCC1..................................................................................................................................... 38 VCC5..................................................................................................................................... 38 VMEM ................................................................................................................................... 38 VSYS..................................................................................................................................... 38 VSYS2................................................................................................................................... 38 Functional Description ............................................................................................................... 38 Am386SXLV CPU Core ........................................................................................................ ...
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LIST OF FIGURES Figure 1. PLL Block Diagram .................................................................................................. 42 Figure 2. Clock Steering Block Diagram ................................................................................. 43 Figure 3. Typical System Design with Secondary Power Supply to Maintain RTC When Primary Power Supply is Off (DRAM Refresh is Optional.)...................................... ...
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LIST OF TABLES Table 1. I/O Pin Voltage Level ............................................................................................... 21 Table 2. Memory Bus Interface .............................................................................................. 22 Table 3. System Interface ...................................................................................................... 23 Table 4. Keyboard Interface................................................................................................... 24 Table 5. Parallel Port Interface............................................................................................... 25 Table 6. Serial Port Interface ...
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Table 51. Local Bus Interface .................................................................................................. 98 Table 52. BIOS ROM Read/Write 8-Bit Cycle........................................................................ 100 Table 53. DOS ROM Read/Write 8-Bit Cycle......................................................................... 102 Table 54. DOS ROM and Fast DOS ROM Read/Write 16-Bit Cycles.................................... 104 Table 55. ISA Memory Read/Write ...
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CONNECTION DIAGRAM GND 1 RAS0 2 RAS1 3 CAS1L[SRCS2 CAS1H[SRCS3] CAS0L[SRCS0] 6 CAS0H[SRCS1 MWE VMEM 9 10 MA10/SA13 11 MA9/SA23 12 GND 13 MA8/SA22 MA7/SA21 14 MA6/SA20 15 MA5/SA19 16 17 MA4/SA18 18 MA3/SA17 19 MA2/SA16 ...
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MICROCONTROLLER PIN DESIGNATIONS This section, beginning with the Connection Diagram on the preceding page, identifies the pins of the ÉlanSC310 microcontroller and lists the signals associ- ated with each pin. Tables 2–10, beginning on page 22, group these signals ...
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PIN DESIGNATIONS (SORTED BY PIN NUMBER) Signal Name Pin No. (Alternate Functions) 1 GND 2 RAS0 3 RAS1 4 CAS1L [SRCS2] 5 CAS1H [SRCS3] 6 CAS0L [SRCS0] 7 CAS0H [SRCS1] 8 MWE 9 VMEM 10 MA10/SA13 11 MA9/SA23 12 GND ...
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PIN DESIGNATIONS (SORTED BY PIN NUMBER) (CONTINUED) Signal Name Pin No. (Alternate Functions) 130 RSVD 131 RSVD 132 RSVD 133 RSVD 134 RSVD 135 VCC 136 RSVD 137 PMC0 138 PMC1 139 SPKR 140 IORESET 141 RESIN 142 VSYS2 143 ...
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PIN DESIGNATIONS (SORTED BY PIN NAME) Signal Name Pin No. (0WS) ADS 172 Maximum ISA bus interface 8042CS [XTDAT] 75 Keyboard interface A12 (BALE) 145 Local bus interface A13 (DACK6) 161 Local bus interface A14 (DACK7) 160 Local bus interface ...
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PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED) Signal Name Pin No System interface D10 30 System interface D11 29 System interface D12 28 System interface D13 27 System interface D14 26 System interface D15 25 System interface D2 ...
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PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED) Signal Name Pin No. INIT 89 Parallel port interface IOCHCHK 177 Maximum ISA bus interface IOCHRDY 192 System interface IOCS16 196 System interface IOR 54 System interface IORESET 140 Reset and power IOW ...
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PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED) Signal Name Pin No. MA6/SA20 15 Memory bus interface MA7/SA21 14 Memory bus interface MA8/SA22 13 Memory bus interface MA9/SA23 11 Memory bus interface MCS16 197 System interface MEMR 56 System interface MEMW ...
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PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED) Signal Name Pin No. SA10 62 System interface SA11 61 System interface SA12/MA11 60 System interface SA13/MA10 10 System interface SA14/MA0 24 System interface SA15/MA1 21 System interface SA16/MA2 19 System interface SA17/MA3 ...
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PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED) Signal Name Pin No. VMEM 9, 22, 35 Power VSYS 48, 65 Power VSYS2 142 Power W/R (DRQ7) 169 Local bus interface [X14OUT] AFDT 80 Miscellaneous interface X1OUT [BAUD_OUT] 200 Miscellaneous interface X32IN ...
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PIN STATE TABLES The Pin State tables beginning on page 22 are grouped by function based on their primary function when the ÉlanSC310 microcontroller is configured at reset for the internal LCD Controller mode (NAME1). The Pin State tables also ...
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Pin Signal Name No. 1,3 2 RAS0 1,3 3 RAS1 1,2 4 CAS1L [SRCS2] 1,2 5 CAS1H [SRCS3] 6 1,2 CAS0L [SRCS0] 7 1,2 CAS0H [SRCS1 MA10/SA13 3 11 MA9/SA23 3 13 MA8/SA22 3 14 MA7/SA21 3 15 ...
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I/O Signal Name Pin No. Type MA11/SA12 60 O SA11 61 O SA10 62 O SA9 63 O SA8 64 O SA7 66 O SA6 67 O SA5 69 O SA4 70 O SA3 71 O SA2 72 O SA1 ...
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Signal Name Pin No. Type TC [TMS] 49 O(I) ENDIRL 50 ENDIRH 51 DBUFOE 59 IOR 54 IOW 55 MEMR 56 MEMW 57 RSTDRV 58 IOCHRDY 192 STI DACK1 146 DRQ1 174 DACK5 144 DRQ5 175 IOCHCHK 177 IRQ4 173 ...
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Signal Name Pin No. Type 1 80 AFDT [X14OUT INIT 1 83 STRB 84 1 SLCTIN ACK BUSY ERROR SLCT 87 PPDWE [PPDCS] 90 PPOEN 91 Notes: 1. These outputs function as ...
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Signal Name Pin No. Type ACIN 101 EXTSMI 102 SUS/RES 103 1 184 PMC4 1 185 PMC3 1 77 PMC2 1 138 PMC1 1 137 PMC0 PGP3 186 PGP2 187 PGP1 188 PGP0 189 BL1 106 BL2 107 BL3 108 ...
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Table 8. Local Bus Interface (Continued) I/O Signal Name Pin No. Type A20 (LA20) 152 A19 (LA19) 153 A18 (LA18) 154 A17 (LA17) 155 A16 (DACK0) 158 A15 (DACK3) 159 A14 (DACK7) 160 A13 (DACK6) 161 162 2 CPUCLK (PULLUP) ...
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Signal Name Pin No. Type 1 140 IORESET 2 201 X32IN 3 202 X32OUT LF1 204 LF2 205 LF3 206 LF4 207 X1OUT [BAUD_OUT] 200 RESIN 141 STI 4 139 SPKR JTAGEN 199 RSVD 129 RSVD 130 RSVD 131 RSVD ...
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All inputs that have VCC clamp = 5 V are 5-V safe inputs regardless of their VCCIO. Signal Name Pin No. 1 203 AVCC 23, 81, 135,180 1 VCC 95, 128 1 VCC5 1 142 VSYS2 1 48, 65 VSYS ...
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PIN DESCRIPTIONS Descriptions of the ÉlanSC310 microcontroller pins are organized into the following functional groupings: Memory bus interface System interface Keyboard interface Parallel port interface Serial port interface MEMORY BUS INTERFACE CAS1H [SRCS3], CAS1L [SRCS2], CAS0H [SRCS1], CAS0L [SRCS0] Column ...
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SYSTEM INTERFACE AEN [TDI] DMA Address Enable (Output; Active High) AEN is used to indicate that the current address active on the SA23–SA0 address bus is a memory address and that the current cycle is a DMA cycle. All I/O ...
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IRQ1, IRQ14 Interrupt Request Channels 1 and 14 (Input; Rising Edge/Active High, with Internal Pullup) This input is connected to the internal 8259A-compati- ble Interrupt Controller Channels 1 and 14. In PC-com- patible systems, IRQ1 may be connected to the ...
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In PC-compatible systems, this signal can be driven by an 8042 keyboard controller, port 2, bit 1. For detailed information about the A20GATE signal, TM see the Élan SC300 and ÉlanSC310 Microcontrollers GATEA20 Function Clarification Application Note, order #21811. ...
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DTR/CFG1 Data Terminal Ready (Output; Active Low) This signal indicates to the external serial device that the internal serial port controller is ready to communi- cate. The state of this signal is used to determine the pin configuration at power-up. ...
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Low immediately after reset, and the PMC3 signal is asserted High immediately after reset. Each of the PMC pins can then be programmed to be High or Low for each of the ÉlanSC310 microcontroller power management modes. SUS/RES ...
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LRDY Local Bus Device Ready (Input; Active Low) This signal is used by the local bus devices to terminate the current bus cycle. M/IO Local Bus Memory/I/O (Output; Active Low) This signal indicates to the local bus devices that the ...
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JTAG BOUNDARY SCAN INTERFACE The ÉlanSC310 microcontroller provides an IEEE Std 1149.1-1990 (JTAG) compliant Standard Test Access Port (TAP) and Boundary-Scan Architecture. The boundary-scan test logic consists of a boundary scan register and support logic that are accessed through the ...
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VCC 3 Supply Pins These supply pins provide power to the ÉlanSC310 mi- crocontroller core. Refer to AC Characteristics for VCC power up timing restrictions. The VCC pins are required for battery backup. For more information about battery ...
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DRAM banks. Both DRAM modes use standard Fast Page mode DRAMs. The memory controller operation is synchronous with respect to the CPU. This ensures maximum perfor- mance for all transfers to local memory. The ...
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Table 15. DRAM Address Translation (Page Mode) Index Index Index DRAM B4h 66h B1h Bit Bits Bits Size Bank (Byte) (Byte ...
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SRAM When using SRAM instead of DRAM for main memory Mbyte can be accessed, the SRAM being or- ganized as one or two banks. Each bank is 16 bits wide and is provided with a low and ...
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Clock Generation The ÉlanSC310 microcontroller requires only one 32.768-kHz clock input that is used to generate all other clock frequencies required by the system. This 32.768-kHz clock input is ...
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Cycle) + (DMA Cycle) + (Low Speed CPU Clock High Speed PLL ( 18.432 9.216 18.432 MHz Divide 4.608 Chain 2.304 1.152 Programmable Low Speed (I – (Low-Speed PLL mode only) Figure ...
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In the PLL Block Diagram, the INT_PLL is the Interme- diate PLL, and is used to multiply the 32.768-kHz input frequency produce a 1.4746-MHz input for use by the LS_PLL and the VID_PLL. The LS_PLL, or Low- ...
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Mode Power On After Power-on reset, system enters High-Speed PLL mode. High-Speed PLL The system will be in this mode as long as activities are detected by activity monitor (described in the Pro- grammable Activity Mask Registers, Indexes 08h, 75h, ...
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Low and PMC3 is asserted High. Prior to this edge, these signals are undefined. The ÉlanSC310 microcontroller can be programmed to reset a timer when an I/O access to a preset address range is detected I/O activity ...
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AVCC Analog Secondary Power Supply R RESIN + ISA and Misc. Figure 3. Typical System Design with Secondary Power Supply to Maintain RTC When Primary Power Supply is Off (DRAM Refresh is ...
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The ÉlanSC300 microcontroller samples the two reset inputs (RESIN and IORESET) to logically determine what state the power pins are in; and, in turn, controls the internal pull-down resistors. Note that in Micro Core Logic Data Out To Core Logic ...
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The Micro Power Refresh bit will always be cleared whenever the RESIN input is sampled Low. Therefore, when the core is initially powered up, the Micro Power DRAM refresh feature will be disabled. This bit is unaf- fected by the ...
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IORESET RESIN PGP Pins PGP2 and PGP3 can be programmed to be set to a pre-defined state for Micro Power Off mode. For more TM information, see the Élan SC310 Microcontroller Pro- ...
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PC/AT system and is unavailable on the ÉlanSC310 microcontroller. The other interrupts are available to external peripherals as in the PC/AT architecture via the IRQ15, IRQ14, IRQ12–IRQ9, IRQ7–IRQ3, and IRQ1 inputs. Other sources of ...
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Figure 5. 374 Octal D Flip Flop SD7–SD0 D Q CLK PPDWE OE Figure 5. ÉlanSC310 Microcontroller Unidirectional Parallel Port Data Bus Implementation When the ÉlanSC310 microcontroller parallel port is ...
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SD7–SD0 PPOEN PPDCS IOW IOR Figure 6. The ÉlanSC310 Microcontroller Bidirectional Parallel Port and EPP Implementation Parallel Port Anomalies General The ÉlanSC310 microcontroller parallel port can be physically mapped to three different I/O locations or can be completely disabled. These ...
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I/O address 070h. The default value for the NMI enable bit is 1, which inhibits NMI generation. The NMI enable bit ( write-only bit, and is active Low. The remaining bits of the register located at ...
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Mbyte System Memory 3 512K x 8 512K x 8 RAS CAS WE Serial MAX241 Port Élan SC310 Microcontroller Figure 7. Typical System Block Diagram (Maximum ISA Mode) Élan™SC310 Microcontroller Data Sheet ...
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Local Bus or Maximum ISA Bus Controller ...
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Table 25. External Resistor Requirements (Continued) Signal Name IRQ12 PULLUP(IRQ10) PULLUP(IRQ7) LDEV(RSVD) DRQ1 DRQ5 PULLDN(IRQ5) ADS(0WS) BHE(IRQ9) BLE(IRQ11) CPUCLK(PULLUP) RSVD(PULLUP) D/C(DRQ0) M/IO(DRQ3) W/R(DRQ7) LRDY(DRQ6) DRQ2[TDO] PULLUP PULLUP PULLUP PULLUP PULLUP PULLUP PULLUP PULLUP PULLUP PULLUP PULLUP DCD DSR SIN CTS ...
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Table 25. External Resistor Requirements (Continued) Signal Name ERROR ACK BUSY PE SLCT PGP0 PGP1 ACIN BL1 BL2 BL3 BL4 SOUT Notes: All Pull-Up and Pull-Down resistor requirements are specified in ohms. 1. This pin is an “alternate pin function ...
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ALTERNATE PIN FUNCTIONS To provide the system designer with the most flexibility, the ÉlanSC310 microcontroller provides a means for reconfiguring some of the pin functions, depending on the system requirements. Reconfiguration of the ÉlanSC310 microcontroller pin functions is accom- plished ...
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Maximum ISA Interface versus Local Bus Interface The maximum ISA interface alternate functions are configured via the DTR and RTS pin states when the ÉlanSC310 microcontroller is reset. Table 27. Pins Shared Between Maximum ISA Bus and Local Bus Interface ...
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ALTERNATE PIN FUNCTIONS SELECTED VIA FIRMWARE The following tables contain brief descriptions of the alternate pin functions/names and the pin names of the default function that the alternate function replaces. These alternate functions are selected via system firmware only. SRAM ...
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PC/XT Keyboard The PC/XT keyboard functionality is enabled via bit 3 of PMU Control 3 Register, Index ADh. PC/XT Keyboard Pin Pin Type Name [XTDAT] I/O [XTCLK] I/O 14-MHz Clock Source Setting bit 3 of Miscellaneous 3 Register, Index BAh, ...
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ISA BUS DESCRIPTIONS The two bus configuration options (local bus or maxi- mum ISA bus) each support a somewhat different sub- set of the ISA bus standard. These subsets are defined in Tables 33 and 34. Table 33. ISA Bus ...
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System Test and Debug The ÉlanSC310 microcontroller provides test and debug features compatible with the standard Test Ac- cess Port (TAP) and Boundary-Scan Architecture (JTAG). The test and debug logic contains the following ele- ments: Five extra pins—TDI, TMS, TCK, ...
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Table 35. Boundary Scan (JTAG) Cells—Order and Type Cell Pin No. Name Position 77 PMC2 A20GATE 3 80 AFDT STRB 6 84 SLCTIN 7 85 BUSY ERROR ...
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Table 35. Boundary Scan (JTAG) Cells—Order and Type (Continued) Cell Pin No. Name Position 124 RSVD 44 125 RSVD 45 126 RSVD 46 127 RSVD 47 129 RSVD 48 130 RSVD 49 131 RSVD 50 132 RSVD 51 133 RSVD ...
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Table 35. Boundary Scan (JTAG) Cells—Order and Type (Continued) Cell Pin No. Name Position 171 D/C 87 172 ADS 88 173 IRQ4 89 174 DRQ1 90 175 DRQ5 91 177 IOCHCHK 92 178 PULLDN 93 179 PULLUP 94 181 IRQ12 ...
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Table 35. Boundary Scan (JTAG) Cells—Order and Type (Continued) Cell Pin No. Name Position 21 MA1 130 24 MA0 131 25 D15 132 26 D14 133 27 D13 134 28 D12 135 29 D11 136 30 D10 137 31 D9 ...
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Table 35. Boundary Scan (JTAG) Cells—Order and Type (Continued) Cell Pin No. Name Position 72 SA2 170 73 SA1 171 74 SA0 172 75 8042CS 173 76 DRQ2 JTAG Instruction Opcodes Table 36 lists the ÉlanSC310 microcontroller’s public JTAG instruction ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature ....................... – +150 C Ambient Temperature Under Bias ... – +125 C Stresses above those listed may cause permanent device failure. Functionality at or above these limits is not implied. Exposure ...
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Table 38. DC Characteristics over Commercial and Industrial Operating Ranges (Plastic Shrink Quad Flat Pack (QFP), 33 MHz VCCIO = 4.5 V – 5 +70 C (commercial); T AMBIENT Symbol Parameter Description ...
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THERMAL CHARACTERISTICS The ÉlanSC310 microcontroller is specified for operation with a case temperature range from 0°C to 85°C for a com- mercial device. Table 40 shows the thermal resistance for 208-pin QFP and TQFP packages. Table 40. Thermal Resistance (°C/Watt) ...
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DERATING CURVES This section describes how to use the derating curves on the following pages in order to determine potential specified timing variations based on system capacitive loading. The pin characteristics tables in this document (see page 21) have a ...
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Figure 9. 3.3-V I/O Drive Type E Rise Time Figure 10. 3.3-V I/O Drive Type E Fall Time 74 P ...
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Figure 11. 5-V I/O Drive Type E Rise Time Figure 12. 5-V I/O ...
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Figure 13. 3.3-V I/O Drive Type D Rise Time Figure 14. 3.3-V I/O Drive Type ...
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Figure 15. 5-V I/O Drive Type D Rise Time Figure 16. ...
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Figure 17. 3.3-V I/O Drive Type C Rise Time Figure 18. 3.3-V I/O Drive Type C Fall Time 78 ...
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Figure 19. 5-V I/O Drive Type C Rise Time Figure 20. 5-V I/O ...
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Figure 21. 3.3-V I/O Drive Type B Rise Time Figure 22. 3.3-V I/O Drive Type B Fall Time ...
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Figure 23. 5-V I/O Drive Type B Rise Time Figure 24. 5-V I/O Drive Type B Fall ...
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Figure 25. 3.3-V I/O Drive Type A Rise Time Figure 26. 3.3-V I/O Drive Type A Fall Time ...
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Figure 27. 5-V I/O Drive Type A Rise Time Figure 28. 5-V I/O Drive Type A Fall Time Élan™SC310 Microcontroller Data ...
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VOLTAGE PARTITIONING The ÉlanSC310 microcontroller supports both 3.3-V system designs and mixed 3.3-V and 5-V system de- signs. For 3.3-V-only operation, all supply pins (VCC, VCC1, VCC5, VMEM, VSYS, VSYS2, and AVCC) should be connected to the 3.3-V DC supply. ...
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It is therefore required that the load capaci- tance in the oscillator circuit is duplicated as closely as possible to the manufacturer’s load capacitance speci- fication. The crystal load capacitance in the circuit consists of the capacitor network C ...
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LOOP FILTERS Each of the Phase-Locked Loops (PLLs) in the ÉlanSC310 microcontroller requires an external Loop Filter. Figure 30 describes each of the Loop Filters and the recommended component values. The recom- mended values for the components are shown in ...
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AC SWITCHING CHARACTERISTICS AND WAVEFORMS The AC specifications provided in the AC characteris- tics tables that follow consist of output delays, input setup requirements, and input hold requirements. Fig- ure 31 provides a key to the switching waveforms. AC specifications ...
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AC Switching Characteristics over Commercial Operating Ranges Table 45. Power-Up Sequencing (See Figures 32–35) Symbol Parameter Description t1 All VCC valid to RESIN and IORESET inactive t2 RESIN and IORESET inactive to RSTDRV inactive t3 IORESET active to RSTDRV active ...
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VCC/AVCC VMEM RESIN VCC5 VSYS2 VCC1 VSYS IORESET RSTDRV Notes: 1. RSTDRV external driver is powered by: VCCIO = VSYS and VCC Clamp = VCC5. Figure 32. Power-Up Sequence Timing Élan™SC310 Microcontroller Data Sheet ...
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VCC/AVCC VMEM RESIN VCC5 VSYS2 VCC1 VSYS IORESET RSTDRV Notes: 1. RSTDRV external driver is powered by: VCCIO = VSYS and VCC Clamp = VCC5. 2. The pulse width of RSTDRV is adjustable based on PLL start-up timing. See the ...
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RSTDRV Note 1 IORESET VCC5 t 6 VSYS2 VCC1 VSYS VCC/AVCC VMEM RESIN Notes: 1. RSTDRV external driver is powered by: VCCIO = VSYS and VCC Clamp = VCC5 secondary power source could be applied at ...
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Table 46. DRAM Memory Interface, Page Hit and Refresh Cycle (See Figures 36 and 37) Symbol Parameter Description t30 MA valid setup to RAS Low t31 MA hold from RAS Low t32 MA setup to CAS Low t37 CAS precharge ...
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MA10–MA0 RAS CAS MWE D15–D0 RAS0 CAS0 MWE Figure 37. DRAM Timings, Refresh Cycle t31 t38 t32 t39 Figure 36. DRAM Timings, Page Hit t53 t50 t51 Élan™SC310 ...
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Table 47. DRAM First Cycle Read Access (See Figure 38) Symbol Parameter Description t5a CAS Low to data valid (read access time) t28a RAS Low to data valid (read access time) t30 MA valid setup to RAS Low t31 MA ...
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Table 48. DRAM Bank/Page Miss Read Cycles (See Figure 38) (Continued) Symbol Parameter Description t44b CAS hold from RAS Low t47 D15–D0 hold from CAS High (read) For more information about DRAM bank miss read wait states, see the DRAM ...
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Table 49. DRAM First Cycle Write Access (See Figure 39) Symbol Parameter Description t5c D15–D0 setup to CAS Low (write) t27d MWE setup to CAS Low (first cycle) t30 MA valid setup to RAS Low t31 MA hold from RAS ...
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MA10–MA0 t31 t30 t40 RAS t44d t32 t39 t41d CAS t43 t27d MWE t49 t5c D15–D0 First Cycle Figure 39. DRAM First Cycle Bank/Page Miss (Write Cycles t38 t34 ...
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Table 51. Local Bus Interface (See Figure 40) Symbol Parameter Description t1 CPUCLK period t2 CPUCLK pulse width Low t3 CPUCLK pulse width High t4 ADS delay from CPUCLK t5 A[23–1] BLE, BHE, W/R,D/C, M/IO delay from CPUCLK t6a LDEV ...
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CPUCLK t4 ADS t5 A23–A12 LDEV LRDY CPURDY D15–D0 (in) D15–D0 (out) Figure 40. Local Bus Interface Élan™SC310 Microcontroller Data Sheet t11 t6a t7 t8 ...
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Table 52. BIOS ROM Read/Write 8 Bit Cycle (See Figure 41) Symbol Parameter Description t1a SA stable to ROMCS active t1b SA stable to ROMCS active t2a SA hold from ROMCS inactive (write) t2b SA hold from ROMCS inactive (read) ...
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SA23–SA0 t1a ROMCS t1b MEMR/W RDDATA WRDATA DBUFOE ENDIRH, ENDIRL Figure 41. BIOS ROM Read/Write 8 Bit Cycle Élan™SC310 Microcontroller Data Sheet t3a t3b t14 t4a t4b t10 t12 ...
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Table 53. DOS ROM Read/Write 8 Bit Cycle (See Figure 42) Symbol Parameter Description t1a SA stable to DOSCS active t1b SA stable to DOSCS active t2a SA hold from DOSCS inactive (write) t2b SA hold from DOSCS inactive (read) ...
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SA19–SA0 DOSCS t1b MEMR/W RDDATA WRDATA DBUFOE ENDIRH, ENDIRL Figure 42. DOS ROM Read/Write 8 Bit Cycle Élan™SC310 Microcontroller Data Sheet t1a t14 t4a t4b t10 t12 0 = ...
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Table 54. DOS ROM and Fast DOS ROM Read/Write 16-Bit Cycles (See Figure 43) Symbol Parameter Description t1a SA stable to DOSCS active t1b SA stable to DOSCS active t2a SA hold from DOSCS inactive (write) t2b SA hold from ...
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SA23–SA0 DOSCS t1b MEMR/W RDDATA WRDATA DBUFOE ENDIRH, ENDIRL Figure 43. DOS ROM Read/Write 16-Bit Cycle t1a t14 t4a t4b t10 t12 0 = Read Élan™SC310 Microcontroller Data Sheet ...
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Table 55. ISA Memory Read/Write 8-Bit Cycle (See Figure 44) Symbol Parameter Description t1 LA stable to BALE inactive t2 SA stable to command active t3 BALE pulse width t4 LA hold from BALE inactive t5a SA hold from command ...
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BALE LA23–LA17 SA23–SA0 MEMR/W IOCHRDY RDDATA WRDATA DBUFOE ENDIRH, ENDIRL Figure 44. ISA Memory Read/Write 8-Bit Cycle Élan™SC310 Microcontroller Data Sheet t19 t4 t18 t6 t2 t8a ...
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Table 56. ISA Memory Read/Write 16-Bit Cycle (See Figure 45) Symbol Parameter Description t1 LA stable to BALE inactive t2 SA stable to command active t3 BALE pulse width t4 LA hold from BALE inactive t5a SA hold from command ...
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BALE t21 LA23–LA17 t20 SA23–SA0 t19 MEMR/W t7a MCS16 IOCHRDY RDDATA WRDATA DBUFOE ENDIRH, ENDIRL Figure 45. ISA Memory Read/Write 16-Bit Cycle Élan™SC310 Microcontroller Data Sheet ...
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Table 57. ISA Memory Read/Write 0 Wait State Cycle (See Figure 46) Symbol Parameter Description t1 LA stable to BALE inactive t2 SA stable to command active t3 BALE pulse width t4 LA hold from BALE inactive t5a SA hold ...
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BALE LA23–LA17 SA23–SA0 MEMR/W MCS16 0WS RDDATA WRDATA Figure 46. ISA Memory Read/Write 0 Wait State Cycle Élan™SC310 Microcontroller Data Sheet t5a t5b ...
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Table 58. ISA I/O 8-Bit Read/Write Cycle (See Figure 47) Symbol Parameter Description t1a SA stable to IOW active t1b SA stable to IOR active t2a SA hold from IOW inactive t2b SA hold from IOR inactive t3a IOW pulse ...
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SA15–SA 0 BALE IOR/W IOCHRDY RDDATA WRDATA DBUFOE ENDIRH, ENDIRL - t14 t1a t1b t4a t4b t10 t12 0 = Read Figure 47. ISA I/O 8-Bit Read/Write Cycle Élan™SC310 ...
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Table 59. ISA I/O 16-Bit Read/Write Cycle (See Figure 48) Symbol Parameter Description t1a SA stable to IOW active t1b SA stable to IOR active t2 SA stable to IOCS16 active t3a IOW active to IOCHRDY inactive t3b IOR active ...
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SA15–SA0 BALE IOR/W IOCS16 IOCHRDY RDDATA WRDATA DBUFOE ENDIRH, ENDIRL Figure 48. ISA I/O 16-Bit Read/Write Cycle Élan™SC310 Microcontroller Data Sheet t15 t1a t1b t13 t2 t3a t3b t11 ...
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Table 60. EPP Data Register Write Cycle (See Figure 49) Symbol t0 AFDT delay from IOW active t1 AFDT delay from PPDCS active t2 AFDT delay from PPOEN active t3 AFDT active pulse width (no wait states added) t4 AFDT ...
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Table 61. EPP Data Register Read Cycle (See Figure 50) Symbol t1 AFDT delay from PPDCS active t2 AFDT active pulse width (no wait states) t3 AFDT High to Low recovery t4 Read data valid delay t5 Read data hold ...
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PHYSICAL DIMENSIONS PQR 208, Trimmed and Formed Plastic Shrink Quad Flat Pack (QFP) Pin 208 Pin 1 I.D. Pin 52 3.20 3.60 0.25 MIN Notes: 1. All dimensions are in millimeters 2. Not to scale. For reference only. 118 P ...
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... All dimensions are in millimeters. 2. Not to scale. For reference only. Trademarks AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am386 and Am486 are registered trademarks of Advanced Micro Devices, Inc. E86, K86, and Élan are trademarks of Advanced Micro Devices, Inc. ...