W986432DH-7 Winbond, W986432DH-7 Datasheet
W986432DH-7
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W986432DH-7 Summary of contents
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... Power Down Mode..........................................................................................................................10 No Operation Command.................................................................................................................11 Deselect Command ........................................................................................................................11 Clock Suspend Mode......................................................................................................................11 8. TABLE OF OPERATING MODES .....................................................................................................12 9. SIMPLIFIED STATE DIAGRAM.........................................................................................................13 10. DC CHARACTERISTICS .................................................................................................................14 Absolute Maximum Rating..............................................................................................................14 11. RECOMMENDED DC OPERATING CONDITIONS ........................................................................14 12. CAPACITANCE................................................................................................................................14 13. DC CHARACTERISTICS .................................................................................................................15 512K 4 BANKS Publication Release Date: July 30, 2002 - 1 - W986432DH 32 BITS SDRAM Revision A5 ...
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... Timing Chart of Burst Stop Cycle (Burst Stop Command) .............................................................42 Timing Chart of Burst Stop Cycle (Precharge Command)..............................................................43 CKE/DQM Input Timing (Write Cycle) ............................................................................................44 CKE/DQM Input Timing (Read Cycle) ............................................................................................45 Self Refresh/Power Down Mode Exit Timing..................................................................................46 17. PACKAGE DIMENSION ..................................................................................................................47 86L TSOP (II)-400 mil.....................................................................................................................47 18. VERSION HISTORY ........................................................................................................................ W986432DH ...
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... Sequential and Interleave burst Burst read, single write operation 3. AVAILABLE PART NUMBER PART NUMBER W986432DH-5 W986432DH-6 W986432DH-6I W986432DH-7 W986432DH-7L Byte data controlled by DQM Power-down Mode Auto-precharge and controlled precharge 4K refresh cycles/64 mS Interface: LVTTL Packaged in 86-pin TSOP II, 400 mil - 0.50 SELF REFRESH SPEED ( CURRENT (MAX ...
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... BS0 22 BS1 W986432DH DQ15 DQ14 82 DQ13 DQ12 80 79 DQ11 DQ10 76 DQ9 DQ8 ...
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... V CCQ for I/O Buffer noise immunity. Ground for I/O Separated ground from V V SSQ Buffer noise immunity Connection No connection - 5 - W986432DH DESCRIPTION A10. Column address: A7. A10 is sampled during a precharge RAS , CAS and RAS RAS , to improve improve DQ SS Publication Release Date: July 30, 2002 ...
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... COLUMN DECODER CELL ARRAY BANK #0 SENSE AMPLIFIER DATA CONTROL CIRCUIT COLUMN DECODER CELL ARRAY BANK #2 SENSE AMPLIFIER NOTE: The cell array configuration is 2048 * 256 * W986432DH COLUMN DECODER CELL ARRAY BANK #1 SENSE AMPLIFIER DQ0 DQ BUFFER DQ31 DQM0~3 COLUMN DECODER CELL ARRAY BANK #3 ...
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... After power up, an initial pause of 200 S is required followed and WE at the positive edge of the clock. The address input data ). The maximum time that each bank can be held active is RRD - 7 - W986432DH CC RSC delay. WE pin voltage RCD high write operation ( WE ...
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... Latency in a burst read cycle, interrupted by Burst Stop Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored. The Mode Register sets type of burst (sequential or interleave) and and CAS high with - 8 - W986432DH CS and CAS while holding CS , CAS ...
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... (disturb addresses are A0, A1 and A2) No address carry from ACCESS ADDRESS W986432DH BUST LENGTH Publication Release Date: July 30, 2002 Revision A5 ...
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... Power Down mode longer than the Refresh period (t device. ) has been satisfied. Issue of Auto-Precharge RP DPL = When using the Auto-precharge Command, DAL RAS and WE are low and CS , RAS , CAS - 10 - W986432DH and t are satisfied. This is RP CAS is high at the and CKE held low with the REF ...
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... CKE returns high to when Clock Suspend mode is exited. (min CKS low with RAS , CAS , and is brought high, the RAS , CAS , and - 11 - W986432DH . The input buffers need (min.). WE held high at the rising WE signals become don't Publication Release Date: July 30, 2002 Revision A5 ...
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... W986432DH RAS CAS ...
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... REF IDLE Power Down CKE Active ROW Power ACTIVE CKE Down Read WRITE READ Write READA WRITEA Precharge Precharge - 13 - W986432DH CBR Refresh Read CKE READ SUSPEND CKE CKE READA SUSPEND CKE Automatic sequence Manual input Publication Release Date: July 30, 2002 Revision A5 ...
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... Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 11. RECOMMENDED DC OPERATING CONDITIONS ( PARAMETER Power Supply Voltage Supply voltage for W986432DH-7L during self refresh mode Power Supply Voltage (for I/O Buffer) Input High Voltage Input Low Voltage Note: V (max +1.2V for pulse width < ...
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... Down mode min 190 CC4 (t = min 125 CC5 Standard (-5/-6/- CC6 Low Power(-6I/,-7L) I CC6L SYMBOL W986432DH -6/-6I -7/-7L UNIT MAX. MAX 165 145 120 110 400 400 A MIN. ...
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... T t 1.5. 1 1.5 1 1.5 1.5 CKS CKH t 1.5 1.5 CMS CMH REF RSC - 16 - W986432DH -7/-7L UNIT NOTE MIN. MAX 100000 20 1 Cycle 1000 7 1000 5 0.5 10 1.5 1 1.5 1 1 ...
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... CLK measured from the negative edge to the positive edge referenced (simultaneously) while all input signals are held in the "NOP" state. The CLK CCQ CONDITIONS See diagram below 1 ohms ohms 30pF AC TEST LOAD and W986432DH 1.4V 2.4V/0. 1.4V (min.). IH (max.). IL Publication Release Date: July 30, 2002 Revision A5 ...
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... Bust Stop Command to Last Valid Data out Read with Auto-precharge Command to Active/Ref Command Write with Auto-precharge Command to Active/Ref Command Latency W986432DH 1 Cycle Cycle + ...
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... RAS CAS WE A0-A10 BS0 CKS CKH CKE t t CMS CMH t t CMS CMH t t CMS CMH t t CMS CMH CKH CKS t CKS - 19 - W986432DH CMH CMS t CKH Publication Release Date: July 30, 2002 Revision A5 ...
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... Timing Waveforms, continued Read Timing CLK CS RAS CAS WE A0-A10 BS0 Read Command Read CAS Latency Valid Data-Out - 20 - W986432DH Valid Data-Out Burst Length ...
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... Valid Data- Valid Data- Valid Data- Valid Data- W986432DH t t CMH CMS Valid Valid Data-in Data- Valid Data- Valid Valid Data-in Data-in ...
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... OH Valid Valid Data-Out Data-Out Valid Valid Data-Out Data-Out Valid Valid Data-Out Data-Out Valid Valid Data-Out Data-Out - 22 - W986432DH OPEN Valid Data-Out OPEN Valid Data-Out ...
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... Reserved Reserved A9 A0 Single Write Mode A0 0 Burst read and Burst write Burst read and single write A0 Publication Release Date: July 30, 2002 - 23 - W986432DH next command Reserved A0 Revision A5 ...
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... RP t RAS t t RCD RCD RBb RAc RBb CBx RAc t AC bx1 aw0 aw2 aw3 bx0 aw1 t RRD Precharge Active Precharge Active Read - 24 - W986432DH RAS RAS t RCD RBd CAy RBd CBz t AC ...
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... RAS t RCD t RCD RAc CBx RAc aw0 aw1 aw2 aw3 bx0 bx1 t RRD Active AP* Read AP W986432DH RAS RAS t RCD RBd RAe CAy CBz RAe RBd ...
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... RP RAS t RCD RBb RBb CBy ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 t RRD Precharge Active Read - 26 - W986432DH RAS t RCD RAc RAc CAz t AC by1 by4 by5 by6 by7 CZ0 Active Read Precharge ...
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... RAS RP t RCD RBb RBb CBy CAC ax3 ax4 ax0 ax2 ax5 ax6 ax7 ax1 t RRD AP* Active Read * AP is the internal precharge start timing - 27 - W986432DH RAS t RCD RAc CAz RAc t CAC t CAC by0 by1 by4 by5 ...
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... RC t RAS t RCD RBb RBb CBy ax4 ax5 ax6 ax7 by0 by1 by2 t RRD Precharge Active Write - 28 - W986432DH RAS t RCD RAc RAc CAz by3 by4 by5 by6 by7 CZ0 CZ1 Active Write ...
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... RC t RAS t RCD RBb CBy RBb ax4 by2 ax5 ax6 ax7 by0 by1 by3 t RRD AP* Active Write * AP is the internal precharge start timing - 29 - W986432DH RAS t RCD RAb CAz RAc by5 by4 by6 by7 CZ0 CZ1 ...
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... RAS t RAS RCD CBx CAy CAm bx0 Ay0 Ay1 a2 bx1 Read Read Read * AP is the internal precharge start timing - 30 - W986432DH CBz am1 am2 bz0 bz1 bz2 bz3 Ay2 am0 Precharge AP* Read ...
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... MHz RAS CAy ax5 ax0 ax1 ax3 ay0 ax2 ax4 Write - 31 - W986432DH ay1 ay2 ay4 ay3 Precharge Publication Release Date: July 30, 2002 Revision A5 23 ...
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... Bank #2 Idle Bank #3 (CLK = 100 MHz RCD RAb RAb aw0 aw1 aw2 aw3 AP* Active * AP is the internal precharge start timing - 32 - W986432DH RAS CAx t AC bx1 bx2 bx3 bx0 Read AP* 23 ...
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... RCD RAb RAb CAx aw2 aw3 bx0 Active Write AP the internal precharge start timing - 33 - W986432DH RAS RP RAc RAc bx1 bx3 bx2 Active AP* Publication Release Date: July 30, 2002 Revision A5 ...
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... Operating Timing Example, continued Autorefresh Cycle CLK RAS CAS WE BS0,1 A10 A0-A9 DQM CKE DQ All Banks Auto Prechage Refresh (CLK = 100 MHz W986432DH Auto Refresh (Arbitrary Cycle) ...
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... A10 A0-A9 DQM t SB CKE t CKS DQ All Banks Self Refresh Precharge Entry (CLK = 100 MHz CKS Self Refresh Cycle - 35 - W986432DH CKS Operation Cycle Arbitrary Cycle Publication Release Date: July 30, 2002 Revision A5 23 ...
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... Bank #2 Idle Bank #3 (CLK = 100 MHz CBw CBx t AC av0 av1 av3 aw0 ax0 av2 Single Write - 36 - W986432DH CBz CBy t AC ay0 az0 az1 az2 az3 Read 22 23 ...
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... When CKE goes high, command input must be No operation at next CLK rising edge. (CLK = 100 MHz CAa t CKS ax0 ax1 ax2 ax3 Precharge Read - 37 - W986432DH RAa RAa CAx CKS NOPActive Precharge Standby Power Down mode ...
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... Act Act represents the Write with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command W986432DH Act Act AP Act ...
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... Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command W986432DH Act Act AP Act (min ...
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... Command DQM DQ (2) CAS Latency Command DQM Command DQM DQ Note: The Output data must be masked by DQM to avoid I/O conflict Read Write Read Write Read Write Read Write W986432DH ...
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... Command DQM Command Write DQM D0 DQ (2) CAS Latency = 3 Write ( a ) Command DQM D0 DQ Write ( b ) Command DQM Read Read Read Q0 Q1 Read W986432DH Publication Release Date: July 30, 2002 Revision A5 11 ...
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... Timing Chart of Burst Stop Cycle (Burst Stop Command (3) Read cycle ( a ) CAS latency =2 Read Command CAS latency = 3 Read Command DQ (2) Write cycle Write Command Note: BST BST BST BST represents the Burst stop command - 42 - W986432DH ...
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... DQM CAS latency = 3 Write Commad DQM D0 DQ PRCG Note PRCG PRCG PRCG PRCG represents the Precharge command - 43 - W986432DH Publication Release Date: July 30, 2002 Revision A5 11 ...
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... External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM DQM MASK ( DQM MASK ( CKE MASK ( W986432DH CKE MASK CKE MASK ...
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... External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM W986432DH Open Open Open Publication Release Date: July 30, 2002 Revision A5 ...
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... All Input Buffer (Include CLK Buffer) are turned off in the Power Down mode and Self Refresh mode NOP Represents the No-Operation command Command Represents one command (min (min)+t (min) CKS CK Command Input Buffer Enable (min (min)+t (min) CKS CK Command Input Buffer Enable - 46 - W986432DH (min (min.) CKS CK ...
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... NOM. MAX. MIN. NOM. MAX. 1.20 0.047 0.15 0.006 0.05 0.002 1.00 0.039 0.17 0.27 0.007 0.011 0.12 0.21 0.005 0.008 22.12 22.22 22.62 0.871 0.875 0.905 10.06 10.16 10.26 0.396 0.400 0.404 11.56 11.76 11.96 0.455 0.463 0.471 0.50 0.020 0.40 0.50 0.60 0.016 0.020 0.024 0.80 0.032 0.10 0.004 0.024 0. W986432DH Publication Release Date: July 30, 2002 Revision A5 ...
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... TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 - 48 - W986432DH DESCRIPTION number Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No ...