5962-9311201MXA Cypress Semiconductor Corporation., 5962-9311201MXA Datasheet

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5962-9311201MXA

Manufacturer Part Number
5962-9311201MXA
Description
Logic ICS, Clock Distribution, Programmable Skew Clock Buffer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Part Number:
5962-9311201MXA
Manufacturer:
TI
Quantity:
287
Cypress Semiconductor Corporation
Document #: 38-07138 Rev. **
Features
Functional Description
The CY7B991 and CY7B992 Programmable Skew Clock Buff-
ers (PSCB) offer user-selectable control over system clock
• All output pair skew <100 ps typical (250 max.)
• 3.75- to 80-MHz output operation
• User-selectable output functions
• Zero input to output delay
• 50% duty-cycle outputs
• Outputs drive 50 terminated lines
• Low operating current
• 32-pin PLCC/LCC package
• Jitter < 200 ps peak-to-peak (< 25 ps RMS)
• Compatible with a Pentium™-based processor
Pentium is a trademark of Intel Corporation.
Logic Block Diagram
REF
— Selectable skew to 18 ns
— Inverted and non-inverted
— Operation at
— Operation at 2x and 4x input frequency (input as low
FB
TEST
as 3.75 MHz)
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
FS
PHASE
FREQ
DET
SELECT
(THREE
INPUTS
LEVEL)
1
FILTER
2
and
1
4
input frequency
GENERATOR
TIME UNIT
VCO AND
SELECT
MATRIX
SKEW
3901 North First Street
7B991–1
Programmable Skew Clock Buffer
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
functions. These multiple-output clock drivers provide the sys-
tem integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual driv-
ers, arranged as four pairs of user-controllable outputs, can
each drive terminated transmission lines with impedances as
low as 50
and full-swing logic levels (CY7B991 TTL or CY7B992 CMOS).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are deter-
mined by the operating frequency with outputs able to skew up
to 6 time units from their nominal “zero” skew position. The com-
pletely integrated PLL allows external load and transmission line
delay effects to be canceled. When this “zero delay” capability of the
PSCB is combined with the selectable output skew functions, the
user can create output-to-output delays of up to 12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility mini-
mizes clock distribution difficulty while allowing maximum sys-
tem clock speed and flexibility.
V
V
GND
GND
4Q1
4Q0
CCQ
3F1
4F0
4F1
CCN
Pin Configuration
San Jose
while delivering minimal and specified output skews
5
6
7
8
9
10
11
12
13
14
4
15
3
PLCC/LCC
16
2
CY7B991
CY7B992
CA 95134
17
Revised September 26, 2001
1
18 19 20
32 31 30
CY7B991
CY7B992
29
28
27
26
25
24
23
22
21
408-943-2600
2F0
GND
1F1
1F0
V
1Q0
1Q1
GND
GND
CCN
7B991–2

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5962-9311201MXA Summary of contents

Page 1

Features • All output pair skew <100 ps typical (250 max.) • 3.75- to 80-MHz output operation • User-selectable output functions — Selectable skew — Inverted and non-inverted 1 1 — Operation at and input frequency 2 ...

Page 2

Pin Definitions Signal Name I/O REF I Reference frequency input. This input supplies the frequency and timing against which all functional variation is measured PLL feedback input (typically connected to one of the eight outputs Three-level ...

Page 3

FBInput REFInput 1Fx 3Fx 2Fx 4Fx (N/A) LM – – (N/A) – – (N/A) – (N/A) + ...

Page 4

Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH (REF and FB inputs only) V Input LOW Voltage IL (REF and FB inputs only) V Three-Level ...

Page 5

Capacitance Parameter Description C Input Capacitance IN Note: 12. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms 5V R1=130 R1 R2=91 ...

Page 6

Switching Characteristics Over the Operating Range Parameter Description f Operating Clock NOM Frequency in MHz t REF Pulse Width HIGH RPWH t REF Pulse Width LOW RPWL t Programmable Skew Unit U t Zero Output Matched-Pair Skew SKEWPR [16, 17] ...

Page 7

Switching Characteristics Over the Operating Range Parameter Description f Operating Clock NOM Frequency in MHz t REF Pulse Width HIGH RPWH t REF Pulse Width LOW RPWL t Programmable Skew Unit U t Zero Output Matched-Pair Skew SKEWPR [16, 17] ...

Page 8

Switching Characteristics Over the Operating Range Parameter Description f Operating Clock NOM Frequency in MHz t REF Pulse Width HIGH RPWH t REF Pulse Width LOW RPWL t Programmable Skew Unit U t Zero Output Matched-Pair Skew SKEWPR [16, 17] ...

Page 9

AC Timing Diagrams t REF t RPWH REF SKEWPR, t SKEW0,1 OTHER Q INVERTED Q t SKEW3,4 REF DIVIDED SKEW1,3, 4 REF DIVIDED BY 4 Document #: 38-07138 Rev RPWL ...

Page 10

Operational Mode Descriptions FB SYSTEM REF CLOCK FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST Figure 2. Zero-Skew and/or Zero-Delay Clock Driver Figure 2 shows the PSCB configured as a zero-skew clock buffer. In this mode the 7B991/992 ...

Page 11

MID, and 3F1 = High. (Since FB aligns at –4 t skews total of +10 t skew is realized.) Many other con figurations can be realized by skewing both the output ...

Page 12

FB 20–MHz REF DISTRIBUTION FS CLOCK 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST FB SYSTEM REF CLOCK FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST Figure 8 shows the CY7B991/992 connected in series to con- struct ...

Page 13

Ordering Information Accuracy (ps) Ordering Code 250 CY7B991–2JC 500 CY7B991–5JC CY7B991–5JI 750 CY7B991–7JC CY7B991–7JI CY7B991–7LMB 250 CY7B992–2JC 500 CY7B992–5JC CY7B992–5JI 750 CY7B992–7JC CY7B992–7JI CY7B992–7LMB MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups ...

Page 14

Package Diagrams 32-Pin Rectangular Leadless Chip Carrier Document #: 38-07138 Rev. ** © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other ...

Page 15

Document Title: CY7B991/CY7B992 Programmable Skew Clock Buffer (PSCB) Document Number: 38-07138 Issue REV. ECN NO. Date ** 110247 12/19/01 Document #: 38-07138 Rev. ** Orig. of Change SZV Change from Spec number: 38-00513 to 38-07138 CY7B991 CY7B992 Description of Change ...

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