W981216BH-7 Winbond, W981216BH-7 Datasheet

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... Using pipelined architecture and 0.175 W981216BH delivers a data bandwidth 143M words per second (-7). To fully comply with the personal computer industrial standard, W981216BH is sorted into three speed grades: -7, -75 and - 8H. The -7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -75 is compliant to the PC133/CL3 specification, the -8H is compliant to the PC100/CL2 specification Accesses to the SDRAM are burst oriented ...

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... RAS CS BS0 BS1 A10/ W981216BH DQ15 DQ14 51 DQ13 DQ12 48 DQ11 DQ10 45 DQ9 DQ8 ...

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... Ground for input buffers and logic circuit inside DRAM. Power (+3.3V) Separated power from V for I/O Buffer improve noise. Ground for I/O Separated ground from V Buffer improve noise. No Connection No connection - 3 - W981216BH DESCRIPTION A11. Column address: A0 A8. , used for output buffers used for output buffers to SS Publication Release Date: October 2000 Revision A1 ...

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... CELL ARRAY D E BANK # SENSE AMPLIFIER Note: The cell array configuration is 4096 * 512 * 16 W981216BH CELL ARRAY E C BANK # SENSE AMPLIFIER ...

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... STG T 260 SOLDER OUT SYMBOL MIN. TYP. V 3.0 3 3.0 3.3 CCQ SYMBOL CLK W981216BH UNIT V +0 ° ° ° MAX. UNIT 3 0.8 V MIN. MAX. UNIT - 3 3 6.5 pf Publication Release Date: October 2000 Revision A1 ...

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... SB t 0.5 10 0.5 T 1.5 1 0.8 0.8 DH 1.5 1 0.8 0 1.5 1.5 t CKS t 0.8 0.8 CKH 1.5 1.5 t CMS 0.8 0.8 t CMH t 64 REF RSC - 6 - W981216BH UNIT -8H (PC100) MAX. MIN. MAX. 68 100000 48 100000 Cycle 1000 10 1000 1000 8 1000 ...

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... IL CC2PS CC3 I 10 CC3P IL I 100 CC4 I 170 CC5 I 2 CC6 SYMBOL MIN I( O( W981216BH UNIT NOTES -75 -8H (PC100) MAX. MIN. MAX 160 150 2 2 MAX. UNIT NOTES 5 A ...

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... Transition times are measured between defines the time at which the outputs achieve the open circuit condition and is not referenced to HZ output level. Output TEST LOAD and W981216BH 1.4V/1.4V See diagram below 2.4V/0. 1. ...

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... Publication Release Date: October 2000 - 9 - W981216BH RAS CAS WE A11 ...

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... Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle. ). The maximum time that each bank can be held active is RRD - 10 - W981216BH +0. has RSC ). ...

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... Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs high impedance state after a delay which is equal to the CAS Latency in a burst Publication Release Date: October 2000 - 11 - W981216BH Revision A1 ...

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... W981216BH BURST LENGTH BUST LENGTH ...

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... Power Down mode longer than the Refresh period (t device. ) has been satisfied. Issue of Auto-Precharge command is RP and When using the Auto-precharge Command, the interval W981216BH . The bank W R are satisfied. This is referred the REF Publication Release Date: October 2000 Revision ...

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... While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. . The input buffers need (min (min). CKS W981216BH to ...

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... A0-A11 BS0 CKS CKE CMS CMH t t CMS CMH t t CMS CMH t t CMS CMH CKH CKH CKS W981216BH CMH CMS t CKS CKH Publication Release Date: October 2000 Revision A1 ...

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... Timing Waveforms, continued Read Timing CLK CS RAS CAS WE A0-A11 BS0 Read Command Read CAS Latency Valid Data-Out - 16 - W981216BH Valid Data-Out Burst Length ...

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... Valid Valid Data-Out Data-Out CKS CKH CKS Valid Valid Data-Out Data-Out - 17 - W981216BH Valid Valid Data-in Data- Valid Valid Data-in Data- ...

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... A0 0 Sequential Interleave CAS Latency Reserved Reserved Reserved A0 A9 Single Write Mode A0 0 Burst read and Burst write Burst read and single write W981216BH ...

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... RP t RAS t t RCD RCD RBb RAc CBx RBb RAc t AC bx1 aw0 aw1 aw2 aw3 bx0 t RRD Precharge Active Precharge Active Read - 19 - W981216BH RAS RAS t RCD RBd CAy RBd CBz t AC ...

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... RAS t RCD t RCD RAc CBx RAc aw0 aw1 aw2 aw3 bx0 bx1 t RRD AP* Active Read - 20 - W981216BH RAS RAS t RCD RAe RBd CAy CBz RAe RBd ...

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... RAS RAS t RCD RBb RBb CBy ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 t RRD Precharge Active Read - 21 - W981216BH RAS RCD RAc RAc CAz t AC by1 by4 by5 by6 ...

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... RAS RP t RCD RBb RBb CBy t CAC ax3 ax4 ax0 ax1 ax2 ax5 ax6 ax7 t RRD AP* Active Read * AP is the internal precharge start timing - 22 - W981216BH RAS t t RAS RP t RCD RAc RAc CAz t CAC t ...

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... RC t RAS t RCD RBb RBb CBy ax4 ax5 ax6 ax7 by0 by1 by2 t RRD Precharge Active Write - 23 - W981216BH RAS RP t RAS t RCD RAc RAc CAz by3 by4 by5 by6 by7 CZ0 Active Write ...

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... RC t RAS t RCD RBb CBy RBb ax4 ax5 ax6 ax7 by0 by1 by2 t RRD AP* Active Write * AP is the internal precharge start timing - 24 - W981216BH RAS t RAS t RCD RAb CAz RAc by3 by4 by5 by6 by7 CZ0 ...

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... RAS t RAS t RCD CBx CAy CAm bx0 Ay0 Ay1 a2 bx1 Read Read Read * AP is the internal precharge start timing - 25 - W981216BH CBz am1 am2 bz0 bz1 bz2 bz3 Ay2 am0 ...

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... Read Bank #1 Bank #2 Idle Bank #3 (CLK = 100 MHz RAS CAy AC ax5 ax0 ax1 ax3 ay0 ax2 ax4 Write - 26 - W981216BH ay1 ay2 ay4 ay3 Precharge 22 23 ...

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... RCD RAb RAb AC aw0 aw1 aw2 aw3 AP* Active * AP is the internal precharge start timing - 27 - W981216BH RAS CAx t AC bx0 bx1 bx2 bx3 Read AP* Publication Release Date: October 2000 Revision A1 ...

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... Bank #1 Bank #2 Idle Bank #3 (CLK = 100 MHz RCD RAb RAb CAx bx0 aw3 Active Write AP the internal precharge start timing - 28 - W981216BH RAS RP RAc RAc bx1 bx3 bx2 AP* Active 23 ...

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... CLK RAS CAS WE BS0,1 A10 A0-A9, A11 DQM CKE DQ All Banks Auto Prechage Refresh (CLK = 100 MHz W981216BH Auto Refresh (Arbitrary Cycle) Publication Release Date: October 2000 Revision A1 ...

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... CLK RAS CAS WE BS0,1 A10 A0-A9, A11 DQM CKE t CKS DQ All Banks Self Refresh Precharge Entry (CLK = 100 MHz CKS t SB Self Refresh Cycle - 30 - W981216BH CKS Operation Cycle Arbitrary Cycle 23 ...

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... CBw CBx t AC av0 av1 av3 aw0 ax0 av2 Single Write - 31 - W981216BH CBz CBy t AC ay0 az0 az1 az2 az3 Read Publication Release Date: October 2000 Revision A1 23 ...

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... When CKE goes high, command input must be No operation at next CLK rising edge. (CLK = 100 MHz CAa t CKS ax0 ax1 ax2 ax3 Read Precharge - 32 - W981216BH RAa RAa CAx CKS NOP Active Precharge Standby Power Down mode 23 ...

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... Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. (min). RAS - 33 - W981216BH Act Act AP Act Publication Release Date: October 2000 ...

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... Act Act represents the Write with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command W981216BH Act Act AP Act ...

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... Note: The Output data must be masked by DQM to avoid I/O conflict Read Read Read Read W981216BH Publication Release Date: October 2000 Revision A1 ...

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... BST BST BST Note: BST represents the Burst stop command PRCG PRCG PRCG PRCG W981216BH ...

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... CLK cycle No. External CLK Internal CKE DQM DQM MASK ( DQM MASK CKE MASK ( CKE MASK ( W981216BH CKE MASK Publication Release Date: October 2000 Revision A1 ...

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... Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM W981216BH Open Open Open ...

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... All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode and Self Refresh mode NOP Represents the No-Operation command Command Represents one command t CK (min) +t (min) CK Command Input Buffer Enable (min) +t (min) CKS CK Command Input Buffer Enable - 39 - W981216BH Publication Release Date: October 2000 Revision A1 ...

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... SEATING PLANE DIMENSION DIMENSION (MM) (INCH) MIN. MAX. MIN. NOM. NOM. 1.20 0.10 0.15 0.004 0.05 0.002 1.00 0.039 0.40 0.24 0.32 0.009 0.012 0.15 0.006 22.12 22.62 0.871 0.875 22.22 10.06 0.400 10.16 10.26 0.396 11.76 11.96 0.455 11.56 0.463 0.80 0.0315 0.60 0.40 0.50 0.016 0.020 0.80 0.032 0.10 0.71 0.028 - 40 - W981216BH MAX. 0.047 0.006 0.016 0.905 0.404 0.471 0.024 0.004 ...

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... Winbond Microelectronics Corp. Winbond Systems Lab. Winbond Systems Lab. 2727 N. First Street, San Jose, 2727 N. First Street, San Jose, CA 95134, U.S.A. CA 95134, U.S.A. TEL: 408 -9436666 TEL: 408 -9436666 FAX: 408 -5441798 FAX: 408 -5441798 t notice. t notice. Publication Release Date: October 2000 - 41 - W981216BH Revision A1 ...