W981616BH-7 Winbond, W981616BH-7 Datasheet
W981616BH-7
Available stocks
Related parts for W981616BH-7
W981616BH-7 Summary of contents
Page 1
... Auto Precharge Command .............................................................................................................10 Precharge Command......................................................................................................................10 Self Refresh Command ..................................................................................................................10 Power-down Mode ..........................................................................................................................10 No Operation Command.................................................................................................................11 Deselect Command ........................................................................................................................11 Clock Suspend Mode......................................................................................................................11 8. TABLE OF OPERATING MODES .....................................................................................................12 9. ELECTRICAL CHARACTERISTICS..................................................................................................13 Absolute Maximum Ratings ............................................................................................................13 Recommended DC Operating Conditions ......................................................................................13 Capacitance ....................................................................................................................................13 512K 2 BANKS Publication Release Date: December 25, 2001 - 1 - W981616BH 16 BITS SDRAM Revision A4 ...
Page 2
... Timing Chart of Burst Stop Cycle (Burst Stop Command) .............................................................37 Timing Chart of Burst Stop Cycle (Prechare Command)................................................................38 CKE/DQM Input Timing (Write Cycle) ............................................................................................39 CKE/DQM Input Timing (Read Cycle) ............................................................................................40 Self Refresh/Power-down Mode Exit Timing ..................................................................................41 12. PACKAGE DIMENSIONS ................................................................................................................42 50L-TSOP (II) 400 mill ....................................................................................................................42 13. VERSION HISTORY ........................................................................................................................ W981616BH ...
Page 3
... Auto precharge and controlled precharge 4K refresh cycles/64 mS Interface: LVTTL Packaged in 50-pin, 400 mil TSOP II 3. AVAILABLE PART NUMBER PART NUMBER W981616BH-5 W981616BH-6 W981616BH-7 W981616BH-7L SPEED ( SELF REFRESH CURRENT(MAX.) 200 MHz 166 MHz 143 MHz 143 MHz Publication Release Date: December 25, 2001 - 3 - ...
Page 4
... CAS 17 34 RAS A10 W981616BH V SS DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 UDQM CLK CKE ...
Page 5
... Separated power from V (+3.3V) for improve noise immunity. I/O buffer Ground for Separated ground from V I/O buffer improve noise immunity connection Connection Publication Release Date: December 25, 2001 - 5 - W981616BH DESCRIPTION A7. , and define the CAS WE , used for output buffers used for output buffers to SS Revision A4 ...
Page 6
... COUNTER COLUMN DECODER CELL ARRAY D BANK # SENSE AMPLIFIER DATA CONTROL CIRCUIT COLUMN DECODER CELL ARRAY D E BANK # SENSE AMPLIFIER Note: The cell array configuration is 2048 * 256 * W981616BH DQ0 DQ BUFFER DQ15 LDQM UDQM ...
Page 7
... WE at the positive edge of the clock. The address input data activate in EDO DRAM. The delay from when the Bank Activate ). The maximum time that each bank can be held active is RRD Publication Release Date: December 25, 2001 - 7 - W981616BH has RSC RC delay. WE pin voltage ...
Page 8
... Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and high with CAS W981616BH and CAS while holding CAS and WE while and low at the rising ...
Page 9
... (disturb addresses are A0, A1 and A2) No address carry from ACCESS ADDRESS Publication Release Date: December 25, 2001 - 9 - W981616BH BUST LENGTH Revision A4 ...
Page 10
... Issue of Auto Precharge command is RP and When using the Auto precharge Command, the interval RAS and RAS , - 10 - W981616BH . The bank WR are satisfied. This is referred are low and CAS is high at the CAS and CKE held low with ) of the REF WE ...
Page 11
... CKE returns high to when Clock Suspend mode is exited. (min (min). CKS low with RAS , CAS , and is brought high, the RAS , CAS , and Publication Release Date: December 25, 2001 - 11 - W981616BH . The input buffers need held high at the rising WE signals become don't Revision A4 ...
Page 12
... W981616BH A10 A9-0 CS RAS CAS ...
Page 13
... OPR T -55 STG T SOLDER OUT SYM. MIN. TYP. V 3.0 3 3 SYM RAS , CAS , Publication Release Date: December 25, 2001 - 13 - W981616BH UNIT NOTE °C 1 150 °C 260 1 ° MAX. UNIT NOTE ...
Page 14
... IH CC3 CKE = CC3P (Power-down mode CC4 ( CC5 Standrad I CC6 Low Power I CC6L SYM. I I( W981616BH - UNIT NOTES MAX. MAX 120 110 100 60 55 ...
Page 15
... 1.5 CKS t 1 CKH t 1.5 CMS t 1 CMH t 64 REF t 10 RSC Publication Release Date: December 25, 2001 - 15 - W981616BH -6 -7 MIN. MAX. MIN. MAX 100000 45 100000 1000 10 1000 6 1000 7 1000 ...
Page 16
... Transition times are measured between defines the time at which the outputs achieve the open circuit condition and is not referenced to HZ output level PARAMETER output ohms AC TEST LOAD and W981616BH CONDITIONS 1.4V/1.4V See diagram below 2.4V/0. 1.4V 1 ohms 30pF ...
Page 17
... IL CS RAS t CAS WE A0-A10 CKS CKH CKE t t CMS CMH t t CMS CMH t CMS CMH t t CMS CMH CKH CKS Publication Release Date: December 25, 2001 - 17 - W981616BH CMH t t CKS CKH Revision A4 t CMS ...
Page 18
... Timing Waveforms, continued Read Timing CLK CS RAS CAS WE A0-A10 BA DQ Read Command Read CAS Latency Valid Data-Out - 18 - W981616BH Valid Data-Out Burst Length ...
Page 19
... Valid Valid Data-Out Data-Out CKH CKS CKH CKS Valid Data-Out Publication Release Date: December 25, 2001 - 19 - W981616BH Valid Valid Data-in Data- Valid Valid Data-in Data- ...
Page 20
... Addressing Mode A0 0 Sequential A0 1 Interleave CAS Latency Reserved Reserved Reserved Single Write Mode A9 0 Burst read and Burst write Burst read and single write W981616BH next ...
Page 21
... RCD RCD RBb RAc CBx RBb RAc t AC bx1 aw0 aw1 aw2 aw3 bx0 t t RRD Precharge Active Precharge Active Read Publication Release Date: December 25, 2001 - 21 - W981616BH RAS RAS t RCD RBd CAy ...
Page 22
... RP t RAS t RCD t RCD RAc CBx CAy RAc t AC aw0 aw1 aw2 aw3 bx0 bx1 bx2 t t RRD RRD Read Active AP* AP* Read - 22 - W981616BH RAS RAS t RCD RBd RAe CBz RAe RBd t ...
Page 23
... RAS t RCD RBb RBb CBy t AC ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 t RRD Precharge Active Read Publication Release Date: December 25, 2001 - 23 - W981616BH RAS RCD RAc RAc CAz t AC by1 by4 by5 ...
Page 24
... RAS RP t RAS t RCD RBb RBb CBy ax3 ax4 ax0 ax1 ax2 ax5 ax6 ax7 by0 t RRD AP* Read Active * AP is the internal precharge start timing - 24 - W981616BH RAS RCD RAc RAc CAz t CAC t CAC by1 by4 ...
Page 25
... RC t RAS t RCD RBb RBb CBy ax4 ax5 ax6 ax7 by0 by1 by2 by3 t RRD Precharge Active Write Publication Release Date: December 25, 2001 - 25 - W981616BH RAS RP t RCD RAc RAc CAz by4 by5 by6 by7 CZ0 CZ1 ...
Page 26
... RC t RAS t RCD RBb CBy RBb ax4 by2 ax5 ax6 ax7 by0 by1 t RRD AP* Active Write * AP is the internal precharge start timing - 26 - W981616BH RAS t RCD RAb CAz RAb by5 by3 by4 by6 by7 CZ0 Write ...
Page 27
... RAS CAm CBx CAy bx0 bx1 Ay0 Ay1 Ay2 Read Read Read * AP is the internal precharge start timing Publication Release Date: December 25, 2001 - 27 - W981616BH CBz am0 am1 am2 bz0 ...
Page 28
... RAa CAx A0-A9 DQM CKE Bank #0 Active Read Bank # RAS CAy ax5 ay1 ax0 ax1 ax3 ay0 ax2 ax4 Write - 28 - W981616BH ay2 ay4 ay3 Precharge 23 ...
Page 29
... RCD RAb RAb aw0 aw1 aw2 aw3 AP* Active * AP is the internal precharge start timing Publication Release Date: December 25, 2001 - 29 - W981616BH RAS RP CAx t AC bx0 bx1 bx2 Read AP* Revision A4 23 ...
Page 30
... Write Bank #1 Bank #2 Idle Bank # RCD RAb RAb CAx bx0 aw3 Active Write AP the internal precharge start timing - 30 - W981616BH RAS RP RAc RAc bx1 bx3 bx2 Active AP* 23 ...
Page 31
... Auto Refresh Cycle CLK RAS CAS WE BA A10 A0-A9 DQM CKE DQ All Banks Auto Prechage Refresh (CLK = 100 MHz Publication Release Date: December 25, 2001 - 31 - W981616BH Auto Refresh (Arbitrary Cycle) Revision A4 ...
Page 32
... MHz CLK RAS CAS WE BA A10 A0-A9 DQM t SB CKE t CKS DQ All Banks Self Refresh Precharge Entry CKS Self Refresh Cycle - 32 - W981616BH CKS Operation Cycle Arbitrary Cycle 23 ...
Page 33
... Bank # CBw CBx CBy av0 av1 av3 aw0 ax0 ay0 av2 Single Write Publication Release Date: December 25, 2001 - 33 - W981616BH CBz t AC az0 az1 az2 az3 Read Revision A4 23 ...
Page 34
... When CKE goes high, command input must be No operation at next CLK rising edge CAa t CKS ax0 ax2 ax3 ax1 Precharge Read - 34 - W981616BH RAa RAa CAx CKS NOPActive Precharge Standby Power Down mode ...
Page 35
... represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. (min). RAS Publication Release Date: December 25, 2001 - 35 - W981616BH Act Act AP Act ...
Page 36
... Act Act Act Act t RP Act W981616BH Act Act AP Act ...
Page 37
... Read Read Read Q0 Q1 Read BST BST BST represents the Burst stop command Publication Release Date: December 25, 2001 - 37 - W981616BH Revision A4 ...
Page 38
... Commad DQ (2) Write cycle ( a ) CAS latency = 2 Write Commad DQM CAS latency = 3 Write Commad DQM Note: PRCG PRCG PRCG PRCG PRCG represents the Precharge command - 38 - W981616BH ...
Page 39
... DQ 1 CLK cycle No. External CLK Internal CKE DQM DQM MASK ( DQM MASK ( CKE MASK ( 3 ) Publication Release Date: December 25, 2001 - 39 - W981616BH CKE MASK CKE MASK Revision A4 ...
Page 40
... Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM W981616BH Open Open Open ...
Page 41
... Self Refresh mode NOP Command (min)+t (min) CKS CK NOP Command Input Buffer Enable (min (min)+t (min) CKS CK Command Input Buffer Enable Represents the No-Operation command Represents one command Publication Release Date: December 25, 2001 - 41 - W981616BH (min (min) CKS CK Revision A4 ...
Page 42
... NOM. 1.20 0.15 0.05 0.10 0.002 0.004 0.90 1.00 1.10 0.035 0.039 0.30 0.45 0.012 0.10 0.15 0.20 0.004 0.006 20.82 20.95 21.08 0.820 0.825 10.03 10.16 10.29 0.395 0.400 11.56 11.76 11.96 0.455 0.463 E 0.80 0.031 e 0.50 0.40 0.60 0.016 0.020 0.80 0.031 0.10 0.031 0. W981616BH MAX. 0.047 0.006 0.043 0.018 0.008 0.830 0.405 0.471 0.024 0.004 o 10 ...
Page 43
... Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Publication Release Date: December 25, 2001 - 43 - W981616BH DESCRIPTION Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No ...