MB86831-80PFV-G-BND Fujitsu, MB86831-80PFV-G-BND Datasheet
MB86831-80PFV-G-BND
Related parts for MB86831-80PFV-G-BND
MB86831-80PFV-G-BND Summary of contents
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... Fujitsu Microelectronics, Inc. has been granted permission to use the trademark SPARC is a registered trademark of SPARC International, Inc. in the United States. SPARC is based on technology developed by Sun Microsystems, Inc. PACKAGE 176-pin plastic QFP MB86831/832/834 (FPT-176P-M01) 1 series of RISC architecture processors, providing high performance for a 2 ...
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MB86830 Series FEATURES • IU (integer unit) Maximum operating frequency : 120 MHz SPARC architecture V8E conforming With 32-bits general register :136 / register window : 8 • Instruction cash The entry lock function is supported • Data cache No ...
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... PRODUCT LINEUP Part number MB86831 Item CPU maximum frequency (MHz) BUS maximum frequency (MHz) Ancillary Version Register (0000) Instruction cache 4 KB/2 way 8 KB/2 way 1 KB/Direct 16 KB/2 way 4 KB/2 way 8 KB/2 way Data cache 2 KB/2 way 8 KB/2 way 1 KB/Direct 16 KB/2 way 2 KB/2 way 8 KB/2 way Cache size change function ADR pin ADR enhancement (ASISEL) ...
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... MB86833/835/836 : LQFP144 • MB86836 : FBGA144 2.Pin array • MB86831/832/834 : The pin is interchangeable.However, the terminal of MB86834 is the pull-up resistor none. • MB86833/835 : The pin is interchangeable. • MB86836 : MB86833/835, from which DRAMC related pins are deleted and to which one channel of general-purpose 16-bit timer and the JTAG pin are added. ...
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... ASI Data Cache Invalidate Register ASI (DCINVLD) ASI Register name MB86831 Ancillary Version Register (00) (VER2) 7.Clock gear • MB86832/833/834/835/836 : Supported • MB86831 : No supported 8.External signal Item MB86831 ASISEL pin function No DSU (debugging No support unit) 4Bank DRAM controller supported General-purpose 16-bit timer ...
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MB86830 Series PIN ASSIGNMENT (TOP VIEW) 132 133 176 1 (FPT-176P- M01 144 109 ...
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... DD3 V :For I/O power supply. DD5 Reserved:This pin must be open. *:The pull-up resistor is built into. However, there is no pull-up resistor in MB86834. [ ]:Pin is added with MB86832/834. Please use this terminal by the opening in case of MB86831-66 and 80. MB86830 Series Pin Pin Pin symbol Pin symbol no ...
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MB86830 Series • MB86833/835 Pin no. Pin symbol Pin no DD3 2 BMODE16 D<28> D<27> D<26> D<25> D<24> D<23> ...
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MB86836 Pin no. Pin symbol Pin no DD3 2 BMODE16 D<28> D<27> D<26> D<25> D<24> D<23> D<22> 46 ...
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MB86830 Series PIN DESCRIPTION 1. CPU Core Related Pins Symbol Pin name CLKIN CLOCK EXTERNAL CLKEXT CLOCK BYPASS RESET# SYSTEM RESET CLKSEL0 INTERNAL CLKSEL1 CLOCK SELECT CLKSEL2 ADDRESS ASISEL SPACE IDENTI- FIERS SELECT CTEST# CTEST BTEST# BTEST ADR<27:2> or ADR<23:2> ...
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Symbol Pin name D<31:0> DATA BUS ADDRESS AS# STROBE READ/WRITE RDWR# BUS TRANSACTION BE0# BE1# BYTE ENABLE BE2# BE3# I/O Function Data bus signal. This pin provides a bidirectional data bus used for instruction fetch, data load, and data ...
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MB86830 Series (Continued) Symbol Pin name BE0# BE1# BYTE ENABLE BE2# BE3# CS0# CS1# CS2# CHIP SELECT CS3# CS4# CS5# 12 I/O Function (Continued) Width of Access type bus Byte-0 (D<15:8>) Byte-1 (D<7:0>) Byte-2 (D<15:8>) Byte-3 (D<7:0>) Write Width of ...
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Symbol Pin name BREQ# BUS REQUEST BGRNT# BUS GRANT O IRL3 IRL2 INTERRUPT RE- IRL1 QUEST LEVEL IRL0 EXTERNAL READY# READY MEMORY MEXC# I EXCEPTION I/O Function Bus request signal. When the BREQ# signal is asserted by external bus ...
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... ADR<28:31> pin on the MB86832/834 or ADR<24:27> pin on the MB86833/835/836. When the ASISEL pin is set to “L”, the “L” input to the AS# pin is prohibited. A choice of these pins is supported by the MB8682/833/834/835/836 but not by the MB86831-66/80 (only I/O ASI<3:0> is available). Like the ADR<27:2> pin (ADR<23:2> pin on the MB86833/835/836), this pin remains enabled for output during the bus cycle ...
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Symbol Pin name NON-CACHE- NONCACHE# ABLE PDOWN# POWER DOWN WKUP# WAKE-UP BURST MODE BMREQ# REQUEST BURST MODE BMACK# ACKNOWL- EDGE PROCESSOR PBREQ# BUS REQUEST I/O Function Non-cacheable signal. This pin inputs the signal for exclusion from data caching. The ...
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MB86830 Series (Continued) Symbol Pin name TIMER OVER- OVF# FLOW SAME PAGE SAMEPAGE# DETECT FLOAT# FLOATING • State of pins Pin symbol At reset ADR<27:2> O (X) AS# O (H) BE0# O (X) BE2# O (X) CS0# to CS5# O ...
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... DRAM Controller Related Pins (MB86831/832/833/834/835) Symbol Pin name RAS0# DRAM ROW RAS1# ADDRESS RAS2# STROBE RAS3# CAS0# DRAM COLUMN CAS1# ADDRESS CAS2# STROBE CAS3# DWE0# DWE1# DRAM WRITE DWE2# ENABLE DWE3# DOE# DRAM OUTPUT ADR<13:2> ADDRESS BUS • State of pins Pin symbol ...
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MB86830 Series 3. Interrupt controller (IRC) Related Pins Symbol Pin name IRQ15/IRL3 IRQ14/IRL2 IRQ13/IRL1 IRQ12/IRL0 INTERRUPT IRQ11 REQUEST IRQ10 IRQ9 IRQ8 4. Signals for the general-purpose 16-bit timer (MB86836) Symbol Pin name Prescaler Clock PRSCK0 Output0 OUT0 Timer Output0 IN0 ...
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DDSU (Debug Support Unit) Related Pins (MB86832/834) Symbol Pin name EMUBRK# Emulator Break EMUENB# Emulator Enable EMUD<3:0> Emulator Data Bus Emulator Status/ EMUSD<3:0> Data Bus 6. Signals for the JTAG Test Port (MB86836) Symbol Pin name TCK Test Clock ...
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... Peripheral resource DATA ADDRESS ASI CONTROL IRL CHIP_SEL PAGE_DET REFRESH *1:The cache capacity is as follows. Parts number MB86831 Item Instruction cash 4 KB/2 way Data cash 2 KB/2 way *2:DSU (debug support unit) is added with MB86832/834. 20 CLKIN DIVIDE STEP Clock Generator SPARC INTEGER UNIT ...
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... ELECTRIC CHARACTERISTICS 1. ABSOLUTE MAXIMUM RATINGS (1)MB86831-66/MB86832-66/MB86833 Parameter Power supply voltage(I/O) V Power supply voltage(Internal) V Input voltage V Storage temperature T Temperature at bias T Overshoot Undershoot (2)MB86834-108,-120/MB86836-90,-108 Parameter Power supply voltage(I/O) V Power supply voltage(Internal) V Input voltage V Storage temperature T Temperature at bias T (3)MB86835 Parameter ...
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MB86830 Series (Notes on Board Wiring) • For connecting the power supply and ground (GND), use multiple V on the MB86830 series must be a multilayer board containing power supply (V stable power supply. Leave any pin designated as “N.C.” ...
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... Power supply voltage (I/O 5.0 V) Power supply voltage (I/O 3.3 V) Power supply voltage (internal) “L” level input voltage “H” level input voltage Operating temperature (2)MB86831-80/MB86832- 80, -100 Parameter Power supply voltage (I/O 5.0 V) Power supply voltage (I/O 3.3 V) Power supply voltage (internal) “L” level input voltage “ ...
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... Parameter Power supply voltage (I/O 3.3 V) Power supply voltage (internal) “L” level input voltage “H” level input voltage Operating temperature • The MB86831/832/833 can be used with a 5.0-V or 3.3-V interface. 5.0-V interface 5 DD5 3.3-V interface DD5 • When the 3.3-V interface is used, all signals input to the MB86830 series must be 3.3 V because the MB86830 series cannot input 5.0-V signals with that interface. • ...
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... DC Characteristics (1)MB86831-66 (Maximum internal operation frequency:66 MHz) • 5.0 V interface Parameter Symbol “L” level input voltage V IL “H” level input voltage V IH “L” level output voltage V OL “H” level output voltage V OH Input leakage current I LI Trial state output leakage ...
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... MB86830 Series (2)MB86831-80 (Maximum internal operation frequency:80 MHz) • 5.0 V interface Parameter “L” level input voltage V “H” level input voltage V “L” level output voltage V “H” level output voltage V Input leakage current I Trial state output leakage I current Power supply current (V ...
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MHz) • 5.0 V interface Parameter Symbol “L” level input voltage V IL “H” level input voltage V IH “L” level output voltage V OL “H” level output voltage V OH Input leakage current I ...
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MB86830 Series (4)MB86832-80 (Maximum internal operation frequency:80 MHz) • 5.0 V interface Parameter “L” level input voltage V “H” level input voltage V “L” level output voltage V “H” level output voltage V Input leakage current I Trial state output ...
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MHz) • 5.0 V interface Parameter Symbol “L” level input voltage V IL “H” level input voltage V IH “L” level output voltage V OL “H” level output voltage V OH Input leakage current I ...
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MB86830 Series (6)MB86833 (Maximum internal operation frequency:66 MHz) • 5.0 V interface Parameter “L” level input voltage V “H” level input voltage V “L” level output voltage V “H” level output voltage V Input leakage current I Trial state output ...
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MHz) (V Parameter Symbol “L” level input voltage V IL “H” level input voltage V IH “L” level output voltage V OL “H” level output voltage V OH Input leakage current I LI Trial state ...
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MB86830 Series (9)MB86835 (Maximum internal operation frequency:84 MHz) Parameter “L” level input voltage V “H” level input voltage V “L” level output voltage V “H” level output voltage V Input leakage current I Trial state output leakage I current Power ...
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MHz) (V Parameter Symbol “L” level input voltage V IL “H” level input voltage V IH “L” level output voltage V OL “H” level output voltage V OH Input leakage current I LI Trial state ...
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... MB86830 Series 4. AC Characteristics All are provided by CLKIN (BUS clock), and the AC characteristic does not depend on the frequency of the oper- ation in CPU. (1)MB86831-66/MB86832-66/MB86833 (Maximum internal operation frequency:66 MHz) Classifica- Parameter tion CLKIN cycle time CLKIN high time CLK CLKIN low time ...
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Classifica- Parameter tion Delay time Hold time Delay time Hold time Output Delay time Hold time Delay time Hold time Setup time Hold time Setup time Hold time Setup time Hold time Setup time Input Hold time Setup time ...
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MB86830 Series (Continued) Classifica- Parameter tion Delay time Hold time Delay time Hold time DRAMC output Delay time Hold time Delay time Hold time Setup time Hold time IRC input “H” level period “L” level period P:Period (Cycle time) * ...
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... MHz) Classifica- Parameter tion CLKIN cycle time CLKIN high time CLK CLKIN low time CLKIN rising time CLKIN falling time Delay time Hold time Delay time Hold time Delay time Hold time Delay time Hold time ...
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MB86830 Series (Continued) Classifica- Parameter tion Delay time Hold time Delay time Output Hold time Delay time Hold time Setup time Hold time Setup time Hold time Setup time Hold time Setup time Input Hold time Setup time Hold time ...
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Classifica- Parameter tion Delay time Hold time Delay time Hold time DRAMC output Delay time Hold time Delay time Hold time Setup time Hold time IRC input “H” level period “L” level period P:Period (Cycle time RDYOUT# ...
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MB86830 Series (3)MB86832-100 (Maximum internal operation frequency:100 MHz) Classifica- Parameter tion CLKIN cycle time CLKIN high time CLK CLKIN low time CLKIN rising time CLKIN falling time Delay time Hold time Delay time Hold time Delay time Hold time Delay ...
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Classifica- Parameter tion Delay time Hold time Delay time Output Hold time Delay time Hold time Setup time Hold time Setup time Hold time Setup time Hold time Setup time Input Hold time Setup time Hold time Setup time ...
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MB86830 Series (Continued) Classifica- Parameter tion Delay time Hold time Delay time Hold time DRAMC output Delay time Hold time Delay time Hold time Setup time Hold time IRC input “H” level period “L” level period P:Period (Cycle time) * ...
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Classifica- Parameter tion CLKIN cycle time CLKIN high time CLK CLKIN low time CLKIN rising time CLKIN falling time Delay time Hold time Delay time Hold time Delay time Hold time Delay time Hold time Delay time Hold ...
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MB86830 Series (Continued) Classifica- Parameter tion Delay time Hold time Delay time Hold time Output Delay time Hold time Delay time Hold time Setup time Hold time Setup time Hold time Setup time Hold time Setup time Input Hold time ...
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Classifica- Parameter tion Delay time Hold time Delay time Hold time DRAM- Coutput Delay time Hold time Delay time Hold time Setup time Hold time IRC input “H” level period “L” level period P:Period (Cycle time ...
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MB86830 Series (5)MB86835 Classifica- Parameter tion CLKIN cycle time CLKIN high time CLK CLKIN low time CLKIN rising time CLKIN falling time Delay time Hold time Delay time Hold time Delay time Hold time Delay time Hold time Delay time ...
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Classifica- Parameter tion Delay time Hold time Delay time Hold time Output Delay time Hold time Delay time Hold time Setup time Hold time Setup time Hold time Setup time Hold time Setup time Input Hold time Setup time ...
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MB86830 Series (Continued) Classifica- Parameter tion Delay time Hold time Delay time Hold time DRAMC output Delay time Hold time Delay time Hold time Setup time Hold time IRC nput “H” level period “L” level period P:Period (Cycle time) * ...
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Classifica- Parameter tion CLKIN cycle time CLKIN high time CLK CLKIN low time CLKIN rising time CLKIN falling time Delay time Hold time Delay time Hold time Delay time Hold time Delay time Hold time Delay time Hold ...
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MB86830 Series (Continued) Classifica- Parameter tion Delay time Hold time Delay time Hold time Output Delay time Hold time Delay time Hold time Setup time Hold time Setup time Hold time Setup time Hold time Setup time Input Hold time ...
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Classifica- Parameter tion Delay time Hold time Delay time Hold time DRAM- Coutput Delay time Hold time Delay time Hold time Setup time Hold time IRC input “H” level period “L” level period P:Period (Cycle time ...
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MB86830 Series TIMING DIAGRAM • Reset timing CLKIN RESET# Note : CLKIN is steady, and raise reset input "H", please after at least 100msec. • Input/output timing 1 CLKIN Input pins Setup Outpou pins Setup Input/output pins Input pins : ...
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Input/output timing 2 CLKIN Hold Input pins Setup Output pins Hold Setup Input/Output Input data pins Imput pins : READY#, MEXC# Output pins : RDYOUT# (internal ready mode) Input/output pins : ADR<27: 2> • Input/output timing 3 CLKIN Hold ...
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... The MB86830 series incorporates data and instruction caches so that the processor can work independently of the slower memory subsystem. These caches are implemented in two-way set-associative configuration on the MB86831/832; they are directly mapped on the MB86833. (4)Locking entries in caches The MB86830 series can lock both of data and instruction entries in their respective caches, ensuring high perfor- mance in processing important or frequently called routines ...
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The on-chip interrupt controller accepts interrupt inputs through eight channels, allowing a trigger mode to be set independently for each of the channels. The interrupt request accepted according to the trigger mode is encoded and output to ...
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MB86830 Series • Integer operation unit internal block diagram I data ir adder inc (+4) e_ir 0 m_ir w_ir pc d_pc e_pc m_pc Instruction Address block block (A block) (I block) I address 3. Address Space The MB86830 series has ...
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The passed parameter remains in the “in“ registers in the current register window and can be ...
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MB86830 Series 5. Instruction Set The MB86830 series is upward code-compatible with other SPARC processors. The MB86830 series now sup- ports additional instructions to improve performance, which were previously not directly supported. In addition to a set of already supported ...
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... MB86834, and 64 units/1 bank on a 16-byte line on the MB86833. The data cache consists of: 64 units/2 banks on the MB86831/835, 64 units/1 bank on a 16-byte line on the MB86833, 128 units/2 banks on the MB86832/836, and 256 units/2 banks on a 32-byte line on the MB86834. (See “The com- position of the data cache” ...
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... With the DRAM controller controlling DRAM, the MB86830 series can write/read data to/from DRAM. The DRAM controller can control up to four banks on the MB86831/832/834 or only one bank on the MB86833/835. The fast page mode, DRAM mode, or EDO DRAM mode can be selected depending on the register setting. The DRAM ...
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RAS and CAS to place DRAM in the self-refresh mode when the processor enters the sleep mode (low power consumption mode). The MB86836 has no DRAM controller. 10. Interrupt Controller (IRC) The interrupt controller (IRC) accepts ...
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MB86830 Series (4)Y Register (Y) bit 31 (5)Ancillary State Register 17 (ASR17) bit 31 bit 31 to bit 1 :Reserved [“0”Write, Don’t care for read] bit 0 :Single Vector Trapping [SVT] (Enable 13. IU (Integer Unit) General-Purpose Registers (Not Memory ...
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Control Register (LCR) bit 31 bit 31 to bit 2 :Reserved [“0”Write, Don’t care for read] bit 1 :Data Cache Entry Auto Lock (Enable bit 0 :Instruction Cache Entry Auto Lock (Enable (3)Lock Control Save Register (LCSR) bit 31 ...
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MB86830 Series (7)Same Page Mask Register (SPGMR) bit 31 30 ASI<7:0>Mask bit 31 :Reserved [“0”Write, Don’t care for read] bit 30 to bit 23 :ASI<7:0>Mask (Care bit 22 to bit 1 :Address<31:10>Mask (Care bit 0 :Reserved [“0”Write,Don’t care for read] ...
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... Pre-load Value (RST (14)Ancillary Version Register (VER2)[Read only] bit 31 Reserved bit 31 to bit 16 :Reserved [Don’t care for read] bit 15 to bit 0 :Version (MB86831:Value 0, MB86832:Value MB86835:Value 4, MB86836:Value (15)Sleep Mode Register (SLPMD)[Write only] bit 31 bit 31 to bit 1 :Reserved ...
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MB86830 Series 15. Bit map of register for cash access (1)Instruction Tag Lock Bit (ICLOCK) [Wite only] bit 31 bit 31 to bit 1 :Reserved [“0”Write, Don’t care for read] bit 0 :Entry Lock (Lock (2)Data Tag Lock Bit (DCLOCK)[Wite ...
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Cache Tag (ICTAG) bit 31 Address Tag bit 31 to bit 13 :Address Tag (RST bit 12 :Capacity 16 KB <Reserved>, Other bit 11 :Capacity 16 KB bit 10 :Capacity 16 KB Capacity ...
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MB86830 Series (5)Instruction Cache Data RAM (ICDATA) bit 31 bit 31 to bit 0:Data (RST X) X:Don’t care (6)Data Cache Tag (DCTAG) bit 31 Address Tag bit 31 to bit 13 :Address Tag (RST bit 12 :Capacity 16 KB bit ...
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Cache Invalidate Register (DCINVLD)[Wite only] bit 31 bit 31 to bit 2 :Reserved [“0”Write] bit 1 :Cache LRU, Lock Bit Clear (Clear bit 0 :Valid Bit Clear (Clear (8)Data Cache Data RAM(DCDATA) bit 31 bit 31 to bit 0 ...
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MB86830 Series 16. Interrupt controller (IRC) (1)Trigger Mode 0 Register (TRGM0) bit 31 Reserved bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read] bit 15 to bit 0 :Trigger Mode (High Level (2)Trigger Mode 1 Register (TRGM1) bit ...
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Latch/Clear Register (IRLAT) bit 31 Reserved bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read] bit 15 to bit 5 :Reserved [“0”Write, Read"0"] bit 4 :IRL Clear [Wite only] (Clear bit 3 to bit 0 :IRL Latch ...
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MB86830 Series 18. DSU (Debugging support unit )(MB86832/834) (1)Instruction Address Descriptor Register (INSTADR) bit 31 bit 31 to bit 2 :Instruction Address Compare Data (RST bit 1 to bit 0 :Reserved [“0”Write, Don’t care for read] (2)Data Address Descriptor Register ...
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... Address 2 Match (Match bit 2 :Instruction Address 1 Match (Match bit 1 :EMUENBL [Read only] bit 0 :EMUBRK [Read only] 19. Clock gear (Not supported in MB86831-66,80) Internal Clock Control/Status Register (ICCS) bit 31 bit 31 to bit 7 :Reserved [“0”Write, Don’t care for read] bit 6 to bit 4 ...
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MB86830 Series • Register explanation Internal Clock Control/Status Register (ICCS) bit 31 bit 31 to bit 7 :Reserved [“0”Write, Don’t care for read] bit 6 to bit 4 :CLKST (Internal Clock Status)(An initial value is a set point of external ...
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Timer Control Register (TCR) bit 31 Reserved bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read] bit 15 :Value Of OUT Signal bit 14 :Value Of IN Signal bit 13 :Reserved [“0”Write, Don’t care for read] bit ...
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MB86830 Series (2)Bus Control Register • Enable burst transfer after setting Cache Enable. To set Cache Disable, disable burst transfer in advance. (3)System Support Control Register • Set Cache Enable before setting DRAM Burst Enable. To set Cache Disable, disable ...
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The Request Sense Register may contain “1” when the Trigger Mode is changed. Therefore, issue “Request Clear” before canceling interrupt masks. The interrupt controller (IRC) and DRAM controller registers cannot be accessed until CS3# becomes“L”. (9)Cache Invalidate Register When ...
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... MB86830 Series ORDERINGINFORMATION Part number MB86831PFV MB86831-80PFV MB86832-66PFV MB86832- 80PFV MB86832-100PFV MB86833PMT2 MB86834PFV MB86834-120PFV MB86835PMT2 MB86836PMT2 MB86836-108PMT2 MB86836PBT MB86836-108PBT 78 Package Plastic QFP 176-pin (FPT-176P-M01) Plastic QFP 176-pin (FPT-176P-M01) Plastic QFP 176-pin (FPT-176P-M01) Plastic QFP 176-pin (FPT-176P-M01) Plastic QFP 176-pin (FPT-176P-M01) Plastic LQFP 144-pin ...
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... PACKAGE DIMENSIONS 176-pin plastic QFP (FPT-176P-M01) 26.60±0.20(1.047±.008)SQ 24.00±0.10(.945±.004)SQ 132 133 INDEX 176 "A" LEAD No. 1 0.50(.0197)TYP 0.10(.004) 1995 FUJITSU LIMITED F176001S-3C-3 C MB86830 Series 3.85(.152)MAX (Mounting height) 0(0)MIN 89 (STAND OFF) 88 21.50 25.60 (.846) (1.008) REF NOM 45 44 0.20± ...
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... MB86830 Series (Continued)I 144-pin plastic LQFP (FPT-144P-M08) 22.00±0.30(.866±.012)SQ 20.00±0.10(.787±.004)SQ 108 109 INDEX 144 "A" LEAD No. 1 0.50(.0197)TYP 0.10(.004) 1995 FUJITSU LIMITED F144019S-1C 1.70(.67)MAX (Mounting height) 0(0)MIN 73 (STAND OFF) 72 21.00 (.827) 17.50 NOM (.686) REF 37 36 0.20± ...
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... FBGA (BGA-144P-M02) 12.00±0.10(.472±.004)SQ INDEX C0.80(.031) 1998 FUJITSU LIMITED B144002S-2C-2 C MB86830 Series +0.20 +.008 9.60(.378)REF 1.25 .049 –0.10 –.004 (Mounting height) 0.38±0.10(.015±.004) 0.80(.031)TYP (Stand off) 0.10(.004 144-Ø0.45±0.10 (144-Ø ...
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... FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval ...