KAA00B606A-TGPX Samsung, KAA00B606A-TGPX Datasheet
KAA00B606A-TGPX
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KAA00B606A-TGPX Summary of contents
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... KAA00B606A Document Title Multi-Chip Package MEMORY 256M Bit(16Mx16) Nand Flash/64M Bit(4Mx16) UtRAM/128M Bit(2Mx16x4Banks) MobileSDRAM Revision History Revision No. History 0.0 Initial issue. 0.1 <UtRAM> Revised - Changed I 2u(Max.) from 35mA to 40mA CC - Changed I 2u(Typ.) from 30mA to 35mA CC - Changed I (Max.) from SBD 0.11 <UtRAM> Errata Correction -Changed UtRAM Speed from 90/100ns to 85ns < ...
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... Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. The KAA00B606A is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This device is available in 127-ball TBGA Type. ...
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... KAA00B606A PIN CONFIGURATION DNU DNU WPn RE C Vss ALE D Vcc A2 E A6d A5d F CSd A9d G Vss CAS H Vcc CLK J Vss WEd K BA1 A10d L Vcc A0 M DNU Vss CSu N DNU Vss OEu A18 Vss Vccu Vccn ...
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... KAA00B606A PIN DESCRIPTION Pin Name Pin Function A0~A21 Address Input(UtRAM) A0d~A11d Address Input(SDRAM) BA0~BA1 Bank Address Input(SDRAM) DQ0~DQ15 Data Input/Out Put(UtRAM, NAND) DQ0d~DQ15d Data Input/Out Put(SDRAM) CEn Chip Enable(NAND) RE Read Enable(NAND) WPn Write Protection(NAND) ALE Address Latch Enable(NAND) CLE Command Latch Enable(NAND) ...
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... KAA00B606A FUNCTIONAL BLOCK DIAGRAM BA0~BA1 Bank Select CLK CKE CS RAS CAS WE LDQM UDQM DPD Vcc /Vcc Q Vss X-Buffers RE Latches & Decoders ALE Y-Buffers CLE Latches & Decoders Vcc F Command Register Vss R/B F Control Logic & High Voltage WE Generator Clk gen. ...
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... KAA00B606A 256Mb(16M x 16) NAND Flash C-die MCP MEMORY - 6 - Preliminary Revision 1.0 May 2003 ...
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... KAA00B606A Figure 1. NAND Flash(x16) ARRAY ORGANIZATION 64K Pages Page Register (=2,048 Blocks) (=256 Words) 256Word Page Register 256 Word I/O 0 I/O 1 I/O 2 1st Cycle 2nd Cycle 3rd Cycle NOTE : Column Address : Starting Address of the Register must be set to "Low". ...
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... KAA00B606A PRODUCT INTRODUCTION This device is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 264 columns. Spare eight columns are located from column address of 256~263. A 264-Word data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...
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... KAA00B606A ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Temperature Under Bias Storage Temperature Short Circuit Current NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet ...
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... KAA00B606A VALID BLOCK Parameter Symbol Valid Block Number NOTE : 1. This device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre- sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits factory-marked bad blocks ...
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... KAA00B606A AC Timing Characteristics for Command / Address / Data Input Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time : NOTE ...
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... KAA00B606A NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor- mation regarding the invalid block( called as the invalid block information. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
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... KAA00B606A NAND Flash Technical Notes Error in write or read operation Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... KAA00B606A NAND Flash Technical Notes Erase Flow Chart Write 60h Write Block Address Write D0h Read Status Register I R Erase Error I Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. Block Replacement ...
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... KAA00B606A Pointer Operation Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. ’00h’ command sets the pointer to ’A’ area(0~255word), and ’50h’ command sets the pointer to ’B’ area(256~263word). With these commands, the starting column address can be set to any of a whole page(0~263word). ’ ...
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... KAA00B606A System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 264word page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant savings in power consumption ...
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... KAA00B606A Command Latch Cycle CLE ALS ALE I/Ox Address Latch Cycle t CLS CLE ALS ALE I/Ox t CLH CLS ALH Command ALH ALS ALH A9~A16 ...
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... KAA00B606A Input Data Latch Cycle CLE ALS ALE I/Ox DIN 0 Sequential Out Cycle after Read I/ R/B : NOTE 1. Transition is measured 200mV from steady state voltage with load. 2. This parameter is sampled and not 100% tested ...
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... KAA00B606A Status Read Cycle CLE t CLS I/Ox READ1 OPERATION (READ ONE PAGE) CLE CEn ALE RE N Address I/Ox 00h Column Page(Row) Address Address R/Bn t CLR t CLH WHR 70h ...
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... KAA00B606A READ1 OPERATION (INTERCEPTED BY CE) CLE CE WE ALE RE N Address I/Ox 00h Row Add1 Col. Add Column Address R/B READ2 OPERATION (READ ONE PAGE) CLE CE WE ALE RE I/Ox 50h Col. Add R/B M Address A ~A are Valid Address & Dout N ...
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... KAA00B606A PAGE PROGRAM OPERATION CLE ALE RE N Address I/Ox 80h Col. Add Row Add1 Sequential Data Column Page(Row) Input Command Address Address R/B COPY-BACK PROGRAM OPERATION CLE ALE RE I/Ox 00h Col. Add Row Add1 Row Add2 Column Page(Row) Address Address ...
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... KAA00B606A BLOCK ERASE OPERATION (ERASE ONE BLOCK) CLE ALE RE I/Ox 60h A9~A16 A17~A24 Page(Row) Address R/B Auto Block Erase Setup Command MANUFACTURE & DEVICE ID READ OPERATION CLE CE WE ALE RE I/Ox 90h Read ID Command Address. 1cycle t t BERS WB DOh Busy Erase Command t AR ...
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... KAA00B606A DEVICE OPERATION PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg- ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera- tion ...
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... KAA00B606A Figure 7. Read2 Operation CLE CE WE ALE R/B RE I/Ox Start Add.(3Cycle) 50h & are "L" Data Output(Sequential) Main array Data Field Spare Field - 24 - Preliminary MCP MEMORY Spare Field Revision 1.0 May 2003 ...
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... KAA00B606A PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive words up to 264 single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done in any random order in a block ...
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... KAA00B606A BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com- mand(60h). Only address valid while address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...
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... KAA00B606A READ ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 11 shows the operation sequence. ...
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... KAA00B606A READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... KAA00B606A Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.3V. WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down and recovery time of minimum required before internal circuit gets ready for any command sequences as shown in Figure 14 ...
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... KAA00B606A 64Mb(4M x 16) UtRAM M-die MCP MEMORY - 30 - Preliminary Revision 1.0 May 2003 ...
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... KAA00B606A POWER UP SEQUENCE 1. Apply power. 2. Maintain stable power(V min.=2.7V Issue read operation at least twice. FUNCTIONAL DESCRIPTION ...
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... KAA00B606A PRODUCT LIST Part Name K1S641635M-EI85 RECOMMENDED DC OPERATING CONDITIONS Item Power Supply voltage I/O Power Supply voltage Ground Input high voltage Input low voltage otherwise specified Overshoot: V +1.0V in case of pulse width 20ns. DDQ 3. Undershoot: -1.0V in case of pulse width 20ns. ...
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... KAA00B606A AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level: 0 -0.2V DDQ Input rising and falling time: 5ns Input and output reference voltage DDQ Output load: C =50pF L AC CHARACTERISTICS (V =2.7~3.1V Parameter List Read Cycle Time Address Access Time ...
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... KAA00B606A TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address Data Out Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) Address CS UB Data out High-Z (READ CYCLE and are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage ...
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... KAA00B606A TIMING WAVEFORM OF WRITE CYCLE(1) Address CS UB Data in Data Undefined Data out TIMING WAVEFORM OF WRITE CYCLE(2) Address CS UB Data in Data out , (WE Controlled ZZ CW( WP(1) t AS( High-Z t WHZ , (CS Controlled ZZ CW(2) t AS( WP( Data Valid ...
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... KAA00B606A TIMING WAVEFORM OF WRITE CYCLE(3) Address CS UB Data in Data out High-Z (WRITE CYCLE wri e occurs during the overlap low CS and low WE. A write begins when CS goes low and WE goes low with asserting for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high ...
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... KAA00B606A TIMING WAVEFORM OF POWER UP(1) V DD(Min DDQ(Min) V DDQ ZZ CS (POWER UP(1)) 1. After V reaches V (Min.) following power application, wait 200 s with CS high and then toggle CS low and commit Read Operation least twice. Then you get into the normal operation. 2. Read operation should be executed by toggling CS pin low. ...
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... KAA00B606A TECHNICAL NOTE INTRODUCTION UtRAM is based on single-transistor DRAM cells. As with any other DRAM, the data in these cells must be periodically refreshed to prevent data loss. What makes the UtRAM unique is that it offers a true SRAM style interface that hides all refresh operations from the memory controller. ...
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... KAA00B606A Figure Address Write operation has similar restriction to Read operation. If your system has a timing which sustains invalid states over write mode and has continuous write signals with length of Min. tWC over s like Figure 4, you must toggle WE once to high 4 Figure 4. CS ...
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... KAA00B606A 128Mb(8M x 16) Mobile SDRAM D-die MCP MEMORY - 40 - Preliminary Revision 1.0 May 2003 ...
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... KAA00B606A ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Voltage on V supply relative Storage temperature Power dissipation Short circuit current NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. ...
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... KAA00B606A DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to V Parameter Symbol Operating Current I CC1 (One Bank Active CKE CC2 Precharge Standby Current in power-down mode I PS CKE & CLK CC2 CKE I N CC2 Input signals are changed one time during 20ns Precharge Standby Current ...
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... KAA00B606A AC OPERATING TEST CONDITIONS Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition VDDQ 13.9K VOH (DC Output VOL (DC) = 0.2V, IOL = 0.1mA 30pF 10.6K Figure 1. DC Output Load Circuit (V = 1.8V + 0.15V - ...
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... KAA00B606A OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay ...
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... KAA00B606A AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CAS latency=3 CLK cycle time CAS latency=2 CAS latency=3 CLK to valid output delay CAS latency=2 CAS latency=3 Output data hold time CAS latency=2 CLK high pulse width CLK low pulse width Input setup time ...
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... KAA00B606A SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address Auto Precharge Enable ...
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... KAA00B606A A. MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with Normal MRS *1 A11 ~ A10/ BA0 ~ BA1 Address "0" Setting for Normal Function MRS Normal MRS Mode Test Mode CAS Latency A8 A7 Type Mode Register Set Reserved ...
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... KAA00B606A Partial Array Self Refresh 1. In order to save power consumption, Mobile SDRAM has PASR option. 2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : 4 Banks, 2 Banks and 1 Bank. BA1=0 BA1=0 BA0=0 BA0=1 BA1=1 BA1=1 BA0=0 BA0 Banks Internal Temperature Compensated Self Refresh 1 ...
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... KAA00B606A C. POWER UP SEQUENCE for Mobile SDRAM 1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined. - Apply VDD before or at the same time as VDDQ. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. ...
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... KAA00B606A E. DEVICE OPERATIONS ADDRESSES of 128Mb BANK ADDRESSES (BA0 ~ BA1) This SDRAM is organized as four independent banks of 2,097,152 words x 16 bits memory arrays. The BA0 ~ BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and precharge operations ...
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... KAA00B606A E. DEVICE OPERATIONS (continued) EXTENDED MODE REGISTER SET (EMRS) The extended mode register stores the data for selecting driver strength, partial self refresh or temperature compensated self refresh. EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used. The default state without EMRS command issued is the full driver strength, and all 4 banks refreshed ...
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... KAA00B606A E. DEVICE OPERATIONS (continued) BURST WRITE The burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS, CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command ...
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... KAA00B606A E. BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend 1) Clock Suspended During Write CLK CMD WR CKE Masked by CKE Internal CLK D D DQ(CL2 DQ(CL3 Not Written 2. DQM Operation 1) Write Mask (BL=4) CLK CMD WR DQM Masked by CKE DQ(CL2 DQ(CL3 ...
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... KAA00B606A 3. CAS Interrupt (I) 1) Read interrupted by Read (BL=4) CLK RD RD CMD A B ADD QA DQ(CL2) 0 DQ(CL3) *2 tCCD 2) Write interrupted by Write (BL=2) CLK CMD tCCD A B ADD tCDL *NOTE " Interrupt" meant to stop burst read/write by external command before the end of burst. ...
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... KAA00B606A 4. CAS Interrupt (II) : Read Interrupted by Write & DQM (a) CL=2, BL=4 CLK i) CMD RD WR DQM ii) CMD RD DQM Hi-Z DQ iii) CMD RD DQM DQ iv) CMD RD DQM DQ (b) CL=3, BL=4 CLK i) CMD RD WR DQM ii) CMD RD DQM DQ iii) CMD RD DQM DQ iv) CMD RD DQM DQ v) CMD RD DQM DQ *NOTE: 1 ...
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... KAA00B606A 5. Write Interrupted by Precharge & DQM 1) tRDL = 2CLK CLK CMD WR DQM Masked by DQM *NOTE prevent bus contention, DQM should be issued which makes at least one gap between data in and data out inhibit invalid write, DQM should be issued. ...
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... KAA00B606A 8. Burst Stop & Interrupted by Precharge 1) Normal Write BL=4 & tRDL=2CLK CLK WR CMD DQM tRDL 2) Write Burst Stop (BL=8) CLK WR CMD DQM Read Burst Stop (BL=4) CLK RD STOP CMD Q DQ(CL2) 0 DQ(CL3) 9. MRS 1) Mode Register Set CLK *4 CMD ...
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... KAA00B606A 10. Clock Suspend Exit & Power Down Exit 1) Clock Suspend (=Active Power Down) Exit CLK CKE Internal *1 CLK CMD 11. Auto Refresh & Self Refresh Auto Refresh An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the clock(CLK) ...
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... KAA00B606A 12. About Burst Type Control Sequential Counting Basic MODE Interleave Counting Random Random column Access MODE CLK CCD 13. About Burst Length Control 1 2 Basic 4 MODE 8 Full Page Special BRSW MODE Random Burst Stop MODE RAS Interrupt (Interrupted by Precharge) Interrupt MODE ...
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... KAA00B606A FUNCTION TRUTH TABLE (TABLE 1) Current CS RAS CAS WE State IDLE Row Active Read ...
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... KAA00B606A FUNCTION TRUTH TABLE (TABLE 1) Current CS RAS CAS Precharging Row Activating Refreshing Mode ...
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... KAA00B606A FUNCTION TRUTH TABLE (TABLE 2) Current CKE CKE CS State (n- Self Refresh All Banks Precharge Power Down All ...
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... KAA00B606A Power Up Sequence Single Bit Read - Write - Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK Page Read Cycle at Different Bank @Burst Length=4 Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK Read & ...
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... KAA00B606A Power Up Sequence for Mobile SDRAM CLOCK CKE Hi CS RAS CAS ADDR BA0 BA1 A10/AP DQ Hi-Z WE High level is necessary DQM t RP Precharge Auto (All Bank) Refresh *NOTE: 1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined. ...
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... KAA00B606A Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length CLOCK CKE t RAS t RC *Note RCD t SH RAS CAS ADDR *Note 2 *Note 2,3 BA0,BA1 BS BS *Note 3 A10/ DQM ...
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... KAA00B606A Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK CLOCK CKE CS RAS CAS ADDR Ra Ca BA0 BA1 A10/AP Ra CL=2 t RCD DQ CL=3 WE DQM Row Active Read (A-Bank) (A-Bank) *NOTE: 1. Minimum row cycle times is required to complete internal DRAM operation. ...
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... KAA00B606A Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK CLOCK CKE CS RAS CAS ADDR Ra Ca BA0 BA1 A10/AP Ra CL=2 t RCD DQ CL=3 WE DQM Row Active Read (A-Bank) (A-Bank) (A-Bank) *NOTE write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention ...
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... KAA00B606A Page Read Cycle at Different Bank @Burst Length CLOCK CKE *Note 1 CS RAS CAS ADDR RAa RBb CAa BA0 BA1 A10/AP RAa RBb CL=2 DQ CL=3 WE DQM Row Active Read (A-Bank) (A-Bank) Row Active Row Active (B-Bank) (C-Bank) *NOTE can be don't cared when RAS, CAS and WE are high at the clock high going dege. ...
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... KAA00B606A Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK CLOCK CKE CS RAS CAS ADDR RAa RAb CAa BA0 BA1 A10/AP RAa RBb DQ DAa0 DAa1 WE DQM Row Active Write (A-Bank) (A-Bank) Row Active (B-Bank) *NOTE interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. ...
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... KAA00B606A Read & Write Cycle at Different Bank @Burst Length CLOCK CKE CS RAS CAS ADDR RAa CAa BA0 BA1 A10/AP RAa CL=2 QAa0 DQ CL=3 WE DQM Row Active Read (A-Bank) (A-Bank) Row Active (D-Bank) *NOTE should be met to complete write. CDL ...
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... KAA00B606A Read & Write Cycle with Auto Precharge I @Burst Length CLOCK CKE CS RAS CAS ADDR RAa RBb CAa BA0 BA1 A10/AP RAa RBb DQ CL=2 CL=3 WE DQM Row Active Read with (A-Bank) Auto Pre charge (A-Bank) Row Active (B-Bank) *NOTE: 1 ...
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... KAA00B606A Read & Write Cycle with Auto Precharge II @Burst Length CLOCK CKE CS RAS CAS ADDR Ra Ca BA0 BA1 A10/ CL=2 CL=3 WE DQM Row Active Read with (A-Bank) Auto Precharge (A-Bank) *NOTE: 1. Any command to A-bank is not allowed in this period determined from at auto precharge start point ...
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... KAA00B606A Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length CLOCK CKE CS RAS CAS ADDR Ra Ca BA0 BA1 A10/ Qa0 WE DQM Row Active Read Suspension *NOTE: 1. DQM is needed to prevent bus contention Qa1 ...
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... KAA00B606A Read Interrupted by Precharge Command & Read Burst Stop Cycle @Full Page Burst CLOCK CKE CS RAS CAS ADDR RAa CAa BA0 BA1 A10/AP RAa CL=2 DQ CL=3 WE DQM Row Active Read (A-Bank) (A-Bank) *NOTE full page mode, burst is finished by burst stop or precharge. ...
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... KAA00B606A Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=2CLK CLOCK CKE CS RAS CAS ADDR RAa CAa BA0 BA1 A10/AP RAa DQ DAa0 DAa1 WE DQM Row Active Write (A-Bank) (A-Bank) *NOTE full page mode, burst is finished by burst stop or precharge. ...
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... KAA00B606A Burst Read Single bit Write Cycle @Burst Length CLOCK CKE CS RAS CAS ADDR RAa CAa RBb BA0 BA1 A10/AP RAa RBb CL=2 DAa0 DQ CL=3 DAa0 WE DQM Row Active Row Active (A-Bank) (B-Bank) Write Read with (A-Bank) Auto Precharge *NOTE: 1. BRSW modes is enabled by setting A9 " ...
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... KAA00B606A Active/Precharge Power Down Mode @CAS Latency=2, Burst Length CLOCK t SS *Note 1 *Note 2 CKE *Note 3 CS RAS CAS ADDR BA A10/ DQM Precharge Power-down Entry Precharge Power-down Exit *NOTE: 1. All banks should be in idle state prior to entering precharge power down mode. ...
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... KAA00B606A Self Refresh Entry & Exit Cycle CLOCK *Note 2 *Note 1 CKE RAS CAS ADDR BA0,BA1 A10/AP Hi DQM Self Refresh Entry *NOTE: TO ENTER SELF REFRESH MODE 1. CS, RAS & CAS with CKE should be low at the same clcok cycle. ...
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... KAA00B606A Mode Register Set Cycle CLOCK HIGH CKE CS *Note 2 RAS *Note 1 CAS *Note 3 ADDR Key Ra BA0 BA1 Hi DQM MRS New Command * All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. *NOTE: MODE REGISTER SET CYCLE 1. CS, RAS, CAS, BA0, BA1 & ...
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... KAA00B606A Extended Mode Register Set Cycle CLOCK HIGH CKE CS *Note 2 RAS *Note 1 CAS *Note 3 ADDR Key Ra BA0 BA1 Hi DQM EMRS New Command *NOTE: EXTENDED MODE REGISTER SET CYCLE 1. CS, RAS, CAS, BA0, BA1 & WE activation at the same clock cycle with address key will set internal mode register. ...
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... KAA00B606A PACKAGE DIMENSION 127-Ball Tape Ball Grid Array Package (measured in millimeters) Top View 10.50 ±0.10 #A1 0.08MAX Bottom View 10.50 0.80 x11=8.80 (Datum (Datum 4.40 127- 0.45 ±0.05 0. Side View 0.45 ±0.05 12.00 ±0. Preliminary MCP MEMORY ±0.10 ...