21285-AB

Manufacturer Part Number21285-AB
DescriptionMicroprocessor, 21285 Core Logic For SA-110 Microprocessor
ManufacturerIntel Corporation
21285-AB datasheet
 

Specifications of 21285-AB

CaseBGADc99+/00+
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Page 23/159:

X-Bus Selection

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2.7.1

X-Bus Selection

X-Bus (ma[7]=1) is a general-purpose parallel interface port that allows connection of 8- and
16-bit peripheral chips. The address to the peripherals is supplied by A[31:0] (or possibly a
buffered version of this signal depending upon the number of devices). The data for the
peripherals is transmitted on D[31:0], which is connected through transceivers controlled by
xd_wren_l.
Table 2-10
describes the X-Bus signals.
Table 2-10. X-Bus Signals
Signal Name
Type
xd_wren_l
OCZ
xior_l
OCZ
xiow_l
OCZ
xcs_l[2:0]
ICOCZ
21285 Core Logic for SA-110 Datasheet
Description
X-Bus data buffer control. Used as the direction control for a data bus
buffer between the X-Bus and the 21285/SA-110. Asserted during writes
to the X-Bus.
X-Bus read strobe. Asserted by the 21285 to enable the X-Bus
peripheral to drive read data.
X-Bus write strobe. Asserted by the 21285 to enable the X-Bus
peripheral to accept write data.
X-Bus chip selects.
As outputs, xcs_l[2:0] are used as chip selects asserted by the 21285
during writes or reads to X-Bus devices. For information on address
ranges, see
Table
5-1.
As inputs, xcs_l[2:0] can be used as interrupts providing that they are
not used for X-Bus chip selects. The direction is controlled by the
SA-110 control register.
Signal xcs_l[1] is also used as the Power Management event signal
pre_pme_l. To be used in this mode, it must be enabled as a output in
the SA-110 Control Register.
This output is asserted by the 21285 when PMCSR bits [15]
(PME_Status) and [8] (PME_En) are both enabled.
Signal Description
2-9