21285-AB

Manufacturer Part Number21285-AB
DescriptionMicroprocessor, 21285 Core Logic For SA-110 Microprocessor
ManufacturerIntel Corporation
21285-AB datasheet
 

Specifications of 21285-AB

CaseBGADc99+/00+
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Block Diagram

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Transactions
The CSR address space is listed in Tables 7-2, 7-3, and 7-4.
Figure 3-1. 21285 Block Diagram
SA-110
Control
D[31:0]
SA-110
Interface
A[31:0]
SDRAM
Control
3.1.3
SDRAM All-Banks Precharge
An SA-110 read from one of the four SDRAM array mode register regions causes an all-banks
precharge to be issued to the associated SDRAM array. An all-banks precharge must be performed
to each SDRAM array as part of the power-up initialization sequence, prior to a SDRAM mode
register set or any other access to SDRAM.
The SA-110 is stalled while the precharge command is issued to the selected SDRAM array. The
value on the low-order SA-110 address lines is ignored and read data should be ignored. During
the precharge command, ba[1:0] is set to a value of 11 and ma[12:8] is set to a value of 11111.
This ensures that, for any supported SDRAM type, the precharge command is interpreted as an
all-banks precharge.
SDRAM vendors recommend that the dqm signals into the SDRAMs be forced high at reset, and
held high until an all-banks precharge command is issued to the array. The 21285 complies with
this recommendation by forcing the dqm signals high at reset, and holding them high until four
all-bank precharge commands have been issued (the internal logic that counts these commands
increments on all-banks precharge, mode register set, and refresh commands). The programmer
should ensure that one all-banks precharge is issued to each array, even if fewer than four arrays
are present.
3-2
Inbound FIFO
Outbound FIFO
PCI Read FIFO
Interrupt Control
Doorbell,
DMA
Timers,
Channels
Serial Port
Other CSRs
Control and Status Registers
21285 Core Logic for SA-110 Datasheet
PCI
Control
ad[31:0]
PCI
Interface
FM-05672.AI4