MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet
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MC68HC812A4 Data Sheet M68HC12 Microcontrollers MC68HC812A4 Rev. 7 05/2006 freescale.com ...
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...
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... Figure 11-1. PLL Block Diagram — Revised diagram to show correct placement of divide-by-two block 12.11.2 Timer Port Data Direction Register — Descriptive paragraph added for clarity Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2006. All rights reserved. Freescale Semiconductor Description MC68HC812A4 Data Sheet, Rev ...
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... Corrected maximum value for frequency of operation. — Corrected table heading. — Replaced package dimension drawing with the MC68HC812A4 Data Sheet, Rev. 7 Page Number(s) 209 and PW 329 IRQ TIM 334 197 328 Throughout and 102 107 122 131 207 222 226 227 231 237 Freescale Semiconductor ...
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... Chapter 13 Multiple Serial Interface (MSI 143 Chapter 14 Serial Communications Interface Module (SCI .151 Chapter 15 Serial Peripheral Interface (SPI 179 Chapter 16 Analog-to-Digital Converter (ATD .195 Chapter 17 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Chapter 18 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Chapter 19 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Freescale Semiconductor MC68HC812A4 Data Sheet, Rev ...
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... List of Chapters 6 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.2 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.3 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.4.1 Interrupt Control Register 4.4.2 Highest Priority I Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Freescale Semiconductor Chapter 1 General Description Chapter 2 Register Block Chapter 3 Central Processor Unit (CPU12) Chapter 4 Resets and Interrupts MC68HC812A4 Data Sheet, Rev ...
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... Detecting Access Type from External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.2 Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.3 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.4 Port B Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8 Chapter 5 Chapter 6 Bus Control and Input/Output (I/O) MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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... Window Definition Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.4.9 Memory Expansion Assignment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.5 Chip-Selects 8.6 Chip-Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.6.1 Chip-Select Control Register 8.6.2 Chip-Select Control Register 8.6.3 Chip-Select Stretch Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.7 Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Freescale Semiconductor Chapter 7 EEPROM Chapter 8 Memory Expansion and Chip-Select MC68HC812A4 Data Sheet, Rev ...
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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.5 Registers and Reset Initialization 113 11.5.1 Loop Divider Registers 113 11.5.2 Reference Divider Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.5.3 Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10 Chapter 9 Key Wakeups Chapter 10 Clock Module Chapter 11 Phase-Lock Loop (PLL) MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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... Timer Port Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 12.11 Using the Output Compare Function to Generate a Square Wave . . . . . . . . . . . . . . . . . . . . . 141 12.11.1 Sample Calculation to Obtain Period Counts 141 12.11.2 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.11.3 Code Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Freescale Semiconductor Chapter 12 Standard Timer Module MC68HC812A4 Data Sheet, Rev ...
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... SCI Control Register 171 14.6.4 SCI Status Register 172 14.6.5 SCI Status Register 173 14.6.6 SCI Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.7 External Pin Descriptions 175 14.7.1 TXD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.7.2 RXD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 12 Chapter 13 Multiple Serial Interface (MSI) Chapter 14 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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... Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.8.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.9 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 15.10 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 15.11 Synchronous Character Transmission Using the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 15.11.1 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 15.11.2 Code Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Freescale Semiconductor Chapter 15 Serial Peripheral Interface (SPI) MC68HC812A4 Data Sheet, Rev ...
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... Firmware Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 17.4.2 BDM Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 17.4.3 BDM Shift Register 219 17.4.4 BDM Address Register 220 17.4.5 BDM CCR Holding Register 220 17.5 Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 14 Chapter 16 Analog-to-Digital Converter (ATD) Chapter 17 Development Support MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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... EEPROM Characteristics 226 18.11 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 18.12 Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 18.13 Non-Multiplexed Expansion Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 18.14 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 19.2 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Freescale Semiconductor Chapter 18 Electrical Characteristics Chapter 19 Mechanical Specifications MC68HC812A4 Data Sheet, Rev ...
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... Table of Contents 16 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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... All channels configurable as input capture or output compare – Flexible choice of clock source • 16-bit pulse accumulator • Real-time interrupt circuit • Computer operating properly (COP) watchdog • Clock monitor • Phase-locked loop (PLL) Freescale Semiconductor MC68HC812A4 Data Sheet, Rev ...
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... Table 1-1. Ordering Information Temperature Range Designator –40 to +85° +70°C — FREE PACKAGE DESIGNATOR TEMPERATURE RANGE Figure 1-1. Device Numbering System MC68HC812A4 Data Sheet, Rev. 7 Frequency Voltage (MHz) 5.0 8.0 3.3 5.0 Freescale Semiconductor ...
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... PD7 DATA7/KWD7 PD6 DATA6/KWD6 PD5 DATA5/KWD5 PD4 DATA4/KWD4 PD3 DATA3/KWD3 PD2 DATA2/KWD2 PD1 DATA1/KWD1 PD0 DATA0/KWD0 Freescale Semiconductor 1-KBYTE SRAM 4-KBYTE EEPROM CPU12 PERIODIC INTERRUPT COP WATCHDOG CLOCK MONITOR INTERRUPT BLOCK CSP1 CSP0 CSD CS3 CS2 CS1 LIM CS0 LITE INTEGRATION MODULE ...
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... MC68HC812A4 Data Sheet, Rev. 7 Table 1-2. Individual ports 56 ADDR4/PB4 55 ADDR3/PB3 54 ADDR2/PB2 53 ADDR1/PB1 52 ADDR0/PB0 51 ARST/PE7 50 MODB/IPIPE1/PE6 49 MODA/IPIPE0/PE5 48 ECLK/PE4 47 XTAL 46 EXTAL 45 V SSPLL 44 XFC 43 V DDPLL 42 V DDX 41 V SSX 40 RESET 39 LSTRB/TAGLO/PE3 38 R/W/PE2 37 IRQ/V /PE1 PP 36 XIRQ/PE0 35 DATA15/PC7 34 DATA14/PC6 33 DATA13/PC5 32 DATA12/PC4 31 DATA11/PC3 30 DATA10/PC2 29 DATA9/PC1 Freescale Semiconductor ...
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... Key wakeup pins that can generate interrupt requests on any transition KWJ7–KWJ0 Port J General-purpose I/O RxD0 PS0 Receive pin for SCI0 TxD0 PS1 Transmit pin for SCI0 Freescale Semiconductor Table 1-2. Pin Descriptions Description (1) (2) (4) MC68HC812A4 Data Sheet, Rev. 7 Signal Descriptions (3) (5) ...
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... Key wakeup interrupt request can occur when an input goes from high to low. 4. Key wakeup interrupt request can occur when an input goes from high to low or from low to high. 22 Table 1-2. Pin Descriptions (Continued) Description Table 1-3. Port Descriptions (3) (4) MC68HC812A4 Data Sheet, Rev. 7 Function (1) Freescale Semiconductor ...
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... None BKGD Pullup 1. Pullup or pulldown devices for each port J pin can be selected with the PUPSJ register ($002D). After reset, pulldowns are selected for all port J pins but must be enabled with PULEJ register. Freescale Semiconductor Enable Bit Register Reset Bit Name (Address) ...
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... PC5/DATA13 D14 34 PD6/DATA14 D15 35 PC7/DATA15 D[0..15] 68 PF0 PF0/CS0 69 PF1 PF1/CS1 70 PF2 PF2/CS2 71 PF3 PF3/CS3 PF4 72 PF4/CSD 73 PF5 PF5/CSP0 PF6 74 PF6/CSP1 PF[0..7] PH0 75 PH0 76 PH1 PH1 77 PH2 PH2 78 PH3 PH3 PH4 81 PH4 PH5 82 PH5 PH6 83 PH6 84 PH7 PH7 PH[0..7] Freescale Semiconductor ...
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... A[0. . 21] PF6/CSP1 PF[ PE[ Figure 1-4. Expanded Wide Mode SRAM Expansion Schematic (Sheet A[0. . 21] RESET V CC Figure 1-4. Expanded Wide Mode SRAM Expansion Schematic (Sheet Freescale Semiconductor IDT71016 A10 A10 25 A11 A11 D10 24 A12 A12 D11 21 A13 A13 D12 A14 20 A14 D13 ...
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... PC5/DATA13 D14 34 PD6/DATA14 35 D15 PC7/DATA15 D[0..15] 68 PF0 PF0/CS0 69 PF1 PF1/CS1 70 PF2 PF2/CS2 71 PF3 PF3/CS3 PF4 72 PF4/CSD PF5 73 PF5/CSP0 PF6 74 PF6/CSP1 PF[0..7] PH0 75 PH0 76 PH1 PH1 77 PH2 PH2 78 PH3 PH3 81 PH4 PH4 PH5 82 PH5 PH6 83 PH6 84 PH7 PH7 PH[0..7] Freescale Semiconductor ...
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... A[0. . 21] PF[ PE[ Figure 1-5. Expanded Narrow Mode SRAM Expansion Schematic (Sheet D[0. . 15] A[0. . 21] PF[ Figure 1-5. Expanded Narrow Mode SRAM Expansion Schematic (Sheet Freescale Semiconductor AM27F010 A10 A10 25 A11 A11 A12 4 A12 A13 28 A13 A14 29 A14 A15 3 A15 2 A16 A16 PF5/CSP0 ...
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... General Description 28 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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... Port C Data Register $0004 (PORTC) Write: See page 66. Reset: Read: Port D Data Register $0005 (PORTD) Write: See page 67. Reset: Read: Port C Data Direction $0006 Register (DDRC) Write: See page 66. Reset: Freescale Semiconductor Bit PA7 PA6 PA5 PB7 PB6 PB5 DDRA7 DDRA6 DDRA5 DDRA4 ...
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... Bit 4 Bit 3 Bit 2 Bit PD4 PD3 PD2 PD1 DDRE3 DDRE2 DDRE1 LSTRE RDWE ESTR IVIS 0 EMD PUPE PUPD PUC PUPB RDPF RDPE PRPD RDPC RAM11 REG11 EE12 Reserved U = Unaffected R Freescale Semiconductor Bit 0 Bit 0 0 PD0 0 DDRE0 EME 1 PUPA 1 RDPAB EEON ...
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... Register (KWIFD) Write: See page 95. Reset: $0022 Reserved $0023 Reserved Read: Port H Data Register $0024 (PORTH) Write: See page 95. Reset: Read: Port H Data Direction $0025 Register (DDRH) Write: See page 96. Reset: Freescale Semiconductor Bit RTIE RSWAI RSBCK RTIF CME FCME FCM ...
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... KPOLJ3 KPOLJ2 KPOLJ1 PUPSJ3 PUPSJ2 PUPSJ1 PULEJ3 PULEJ2 PULEJ1 PF4 PF3 PF2 PF1 Bit 4 Bit 3 Bit 2 Bit DDRF3 DDRF2 DDRF1 Reserved U = Unaffected R Freescale Semiconductor Bit 0 Bit 0 0 KWIFH0 0 PJ0 0 DDRJ0 0 KWIEJ0 0 KWIFJ0 0 KPOLJ0 0 PUPSJ0 0 PULEJ0 0 R PF0 0 Bit 0 0 DDRF0 0 ...
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... Chip-Select Stretch $003E Register 0 (CSSTR0) Write: See page 91. Reset: Read: Chip-Select Stretch $003F Register 1 (CSSTR1) Write: See page 91. Reset: Read: Loop Divider Register High $0040 (LDVH) Write: See page 113. Reset: Freescale Semiconductor Bit DDRG5 DDRG4 PD19 PD18 PD17 PPA21 PPA20 PPA19 ...
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... Figure 2-1. Register Map (Sheet 6 of 14) MC68HC812A4 Data Sheet, Rev LDV4 LDV3 LDV2 LDV1 RDV11 RDV10 RDV9 RDV4 RDV3 RDV2 RDV1 BCSC BCSB BCSA MCSB ASCIE FRZ1 PRS4 PRS3 PRS2 PRS1 MULT Reserved U = Unaffected R Freescale Semiconductor Bit 0 LDV0 1 RDV8 1 RDV0 MCSA ASCIF 0 FRZ0 0 PRS0 ...
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... See page 206. Reset: $0073 Reserved Read: ATD Result Register 2 $0074 (ADR2H) Write: See page 206. Reset: $0075 Reserved Read: ATD Result Register 3 $0076 (ADR3H) Write: See page 206. Reset: $0077 Reserved Freescale Semiconductor Bit SCF CCF7 CCF6 CCF5 SAR9 SAR8 SAR7 ...
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... ADRxH2 ADRxH1 Indeterminate IOS4 IOS3 IOS2 IOS1 FOC4 FOC3 FOC2 FOC1 OC7M3 OC7M2 OC7M1 OC7D3 OC7D2 OC7D1 Bit 12 Bit 11 Bit 10 Bit Bit 4 Bit 3 Bit 2 Bit Reserved U = Unaffected R Freescale Semiconductor Bit 0 ADRxH0 R ADRxH0 R ADRxH0 R ADRxH0 R IOS0 0 FOC0 0 OC7M0 0 OC7D0 0 Bit 8 0 Bit 0 0 ...
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... High (TC0H) Write: See page 133. Reset: Read: Timer Channel 0 Register $0091 Low (TC0L) Write: See page 133. Reset: Read: Timer Channel 1 Register $0092 High (TC1H) Write: See page 133. Reset: Freescale Semiconductor Bit TEN TSWAI TSBCK TFFCA OM7 OL7 OM6 0 ...
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... Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit Bit 11 Bit 10 Bit 9 Bit Reserved U = Unaffected Freescale Semiconductor ...
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... Read: SCI 0 Baud Rate Register $00C0 High (SC0BDH) Write: See page 168. Reset: Read: SCI 0 Baud Rate Register $00C1 Low (SC0BDL) Write: See page 168. Reset: Figure 2-1. Register Map (Sheet 11 of 14) Freescale Semiconductor Bit Bit 7 Bit 6 Bit 5 Bit PAEN PAMOD ...
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... SBR6 SBR5 SBR4 LOOPS WOMS RSRC TIE TCIE RIE ILIE TDRE TC RDRF IDLE Unimplemented R MC68HC812A4 Data Sheet, Rev Bit 0 WAKE ILT RWU SBK RAF SBR11 SBR10 SBR9 SBR8 SBR3 SBR2 SBR1 SBR0 WAKE ILT RWU SBK RAF Reserved U = Unaffected Freescale Semiconductor ...
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... Reserved ↓ ↓ $00EF Reserved Read: EEPROM Configuration $00F0 Register (EEMCR) Write: See page 74. Reset: Read: EEPROM Block Protect $00F1 Register (EEPROT) Write: See page 75. Reset: Figure 2-1. Register Map (Sheet 13 of 14) Freescale Semiconductor Bit Unaffected by reset Unaffected by reset SPIE SPE ...
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... PORTE and DDRE are not in the map in peripheral mode and expanded modes. • KWIED and KWIFD are not in the map in wide expanded modes and narrow special expanded mode. 42 Bit EEODD EEVEN MARG EECPD BULKP 0 0 BYTE Unimplemented R MC68HC812A4 Data Sheet, Rev Bit 0 EECPRD 0 EECPM ROW ERASE EELAT EEPGM Reserved U = Unaffected Freescale Semiconductor ...
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... The CPU12 also offers an extensive set of indexed addressing capabilities. 3.2 Programming Model CPU12 registers are an integral part of the CPU and are not addressed as if they were memory locations. See Figure 3- Freescale Semiconductor 8-BIT ACCUMULATORS A AND 16-BIT DOUBLE ACCUMULATOR INDEX REGISTER X Y ...
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... Reset Unaffected by reset Figure 3-2. Accumulator A ( Unaffected by reset Figure 3-3. Accumulator B ( D11 D10 D9 (A1) D8 (A0) D7 (B7) D6 (B6) D5 (B5) D4 (B4) D3 (B3) D2 (B2) D1 (B1) D0 (B0) (A3) (A2) Unaffected by reset Figure 3-4. Accumulator D (D) MC68HC812A4 Data Sheet, Rev Bit Bit Freescale Semiconductor 1 Bit 0 ...
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... The program counter contains the address of the next instruction to be executed. The program counter can also serve as an index register in all indexed addressing modes except autoincrement and autodecrement. Bit SP15 SP14 SP13 SP12 Reset: Freescale Semiconductor X11 X10 Unaffected by reset Figure 3-5. Index Register X (X) ...
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... A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consecutive bytes with the most significant byte at the lower value address. There are no special requirements for alignment of instructions or operands MC68HC812A4 Data Sheet, Rev Bit Freescale Semiconductor ...
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... INST oprx16,xysp (16-bit offset) Indexed-indirect INST [oprx16,xysp] (16-bit offset) Indexed-indirect (D accumulator INST [D,xysp] offset) Freescale Semiconductor Table 3-1. Addressing Mode Summary Abbreviation INH Operands (if any) are in CPU registers. Operand is included in instruction stream. or IMM 8- or 16-bit size implied by context Operand is the lower 8 bits of an address in the range DIR $0000– ...
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... Auto pre-decrement/increment or Auto post-decrement/increment; n,+ pre-(0) or post-(1 –8 to – n,r+ rr can specify (pc not a valid choice) Accumulator offset (unsigned 8-bit or 16-bit) aa: (16-bit see accumulator D offset indexed-indirect rr can specify Accumulator D offset indexed-indirect rr can specify MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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... An interrupt that is assigned highest priority is still subject to global masking by the I bit in the CCR or by any associated local bits. Interrupt vectors are not affected by priority assignment. HPRIO can only be written while the I bit is set (interrupts inhibited). order of priority. Freescale Semiconductor Table 4-1 lists interrupt sources and vectors in default MC68HC812A4 Data Sheet, Rev. 7 ...
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... C4I I bit $E6 C5I I bit $E4 C6I I bit $E2 C7I I bit $E0 TOI I bit $DE PAOVI I bit $DC PAI I bit $DA SPI0E I bit $D8 TIE TCIE RIE I bit $D6 RIE ILIE TIE TCIE RIE I bit $D4 RIE ILIE ASCIE I bit $D2 KWIEJ[7–0] I bit $D0 I bit $CE — I bit $80–$CC Freescale Semiconductor ...
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... Figure 4-2. Highest Priority I Interrupt Register (HPRIO) Read: Anytime Write: Only if I mask in CCR = 1 (interrupts inhibited) To give a maskable interrupt source highest priority, write the low byte of the vector address to the HPRIO register. For example, writing $F0 to HPRIO assigns highest maskable interrupt priority to the real-time Freescale Semiconductor ...
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... Other instructions may be executed between these writes. A write of any value other than $55 or $AA or software failing to execute the sequence properly causes a COP reset to occur. 4.5.4 Clock Monitor Reset If clock frequency falls below a predetermined limit when the clock monitor is enabled, a reset occurs. 52 NOTE MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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... Other Resources The timer, serial communications interface (SCI), serial peripheral interface (SPI), and analog-to-digital converter (ATD) are off after reset. Freescale Semiconductor MC68HC812A4 Data Sheet, Rev. 7 Effects of Reset 53 ...
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... Adjusts the stack pointer to point again at the stacked CCR location, SP – 9 • Fetches the vector of the pending interrupt • Begins execution of the interrupt service routine at the location pointed to by the vector 54 Stacked Values RTN SP – – – – – 9 CCR MC68HC812A4 Data Sheet, Rev. 7 Table 4-2 : RTN Freescale Semiconductor ...
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... Normal Operating Modes These modes provide three operating configurations. Background debugging is available in all three modes, but must first be enabled for some operations by means of a BDM command. BDM can then be made active by another BDM command. Freescale Semiconductor Table 5-1. Mode Selection Mode 0 ...
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... BDM and the external master can cause improper operation of both modes. 5.2.3 Background Debug Mode Background debug mode (BDM auxiliary operating mode that is used for system development. BDM is implemented in on-chip hardware and provides a full set of debug operations. Some BDM 56 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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... Program 2. Data 3. One extra page overlay The sizes and locations of the program and data overlay windows are fixed. One of two locations can be selected for the extra page (EPAGE). Freescale Semiconductor shows resource mapping precedence. Table 5-2. Mapping Precedence Resource 1 BDM ROM (if active) ...
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... Visibility is not available when the part is operating in a single-chip mode Internal bus operations are visible on external bus Internal bus operations are not visible on external bus MODB MODA ESTR Figure 5-1. Mode Register (MODE) MC68HC812A4 Data Sheet, Rev Bit 0 IVIS 0 EMD EME Freescale Semiconductor ...
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... REG15 Write: Reset: 0 Figure 5-2. Register Initialization Register (INITRG) Read: Anytime Write: Once in normal modes; anytime in special modes REG15–REG11 — Register Position Bits These bits specify the upper five bits of the 16-bit register address. Freescale Semiconductor REG14 REG13 REG12 REG11 ...
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... EEON — EEPROM On Bit EEON enables the on-chip EEPROM. EEON is forced single-chip modes. Write anytime 1 = EEPROM at address selected by EE15–EE12 0 = EEPROM removed from memory map RAM14 RAM13 RAM12 RAM11 EE14 EE13 EE12 MC68HC812A4 Data Sheet, Rev Bit Bit EEON Freescale Semiconductor ...
Page 61
... Data only goes through port C externally. This allows 8-bit and 16-bit external memory devices to be mixed in a system Makes the register-following chip-select active space act as a full 16-bit data bus. In the narrow (8-bit) mode, NDRC has no effect. Freescale Semiconductor ...
Page 62
... VECTORS SINGLE-CHIP SPECIAL Figure 5-6. Memory Map MC68HC812A4 Data Sheet, Rev. 7 REGISTERS MAPPABLE TO ANY 2-K SPACE RAM MAPPABLE TO ANY 2-K SPACE EEPROM MAPPABLE TO ANY 4-K SPACE $F000 EEPROM BDM SINGLE-CHIP MODES IF ACTIVE $FFFF Freescale Semiconductor ...
Page 63
... In any expanded mode, port A, port B, and port C are used for address and data lines so registers for these ports, as well as the data direction registers for these ports, are removed from the on-chip memory map and become external accesses. Freescale Semiconductor R/W 0 ...
Page 64
... I/O port. DDRA is not in the on-chip map in expanded and peripheral modes Associated pin is an output Associated pin is a high-impedance input PA6 PA5 PA4 ADDR14 ADDR13 ADDR12 DDRA6 DDRA5 DDRA4 DDRA3 MC68HC812A4 Data Sheet, Rev Bit 0 PA3 PA2 PA1 PA0 ADDR11 ADDR10 ADDR9 ADDR8 2 1 Bit 0 DDRA2 DDRA1 DDRA0 Freescale Semiconductor ...
Page 65
... Write: Anytime, if register is in the map This register determines the primary direction for each port B pin when functioning as a general-purpose I/O port. DDRB is not in the on-chip map in expanded and peripheral modes Associated pin is an output Associated pin is a high-impedance input. Freescale Semiconductor PB6 ...
Page 66
... I/O port Associated pin is an output Associated pin is a high-impedance input PC6 PC5 PC4 DATA14 DATA13 DATA12 DDRC6 DDRC5 DDRC4 DDRC3 MC68HC812A4 Data Sheet, Rev Bit 0 PC3 PC2 PC1 PC0 DATA11 DATA10 DATA9 DATA8 DATA9/1 DATA8 Bit 0 DDRC2 DDRC1 DDRC0 Freescale Semiconductor ...
Page 67
... This register is not in the map in wide expanded and peripheral modes. Also, in special narrow expanded mode, the function of this port is determined by the EMD control bit. If EMD is set, this register is not in the on-chip map and port D is used for DATA7–DATA0 of visible internal accesses. If EMD is clear, this port serves as general-purpose I/O or key wakeup signals. Freescale Semiconductor ...
Page 68
... This register is not in the map in peripheral mode and expanded modes while the EME control bit is set PE6 PE5 PE4 PE3 Unaffected by reset MODB or MODA or ECLK LSTRB IPIPE1 IPIPE0 DDRE6 DDRE5 DDRE4 DDRE3 MC68HC812A4 Data Sheet, Rev Bit 0 PE2 PE1 PE0 R/W IRQ XIRQ 2 1 Bit 0 DDRE2 DDRE1 DDRE0 Freescale Semiconductor ...
Page 69
... Normal modes: Write never Special modes: Write anytime except the first time 1 = PE6 is a test signal output from the PLL module (no effect in single-chip or normal expanded modes); PIPOE = 1 overrides this function and forces PE6 pipe status output signal PE6 is general-purpose I/O or pipe output. Freescale Semiconductor ...
Page 70
... PE2 is configured as the R/W pin. In single-chip modes, RDWE has no effect and PE2 is a general-purpose I/O pin PE2 is a general-purpose I/O pin. R/W is used for external writes. After reset in normal expanded mode disabled. If needed, it must be enabled before any external writes. 70 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 71
... This bit has no effect if port B is being used as part of the address bus (the pullups are inactive). PUPA — Pullup Port A Enable Bit 1 = Enable pullup devices for all port A input pins 0 = Port A pullups disabled This bit has no effect if port A is being used as part of the address bus (the pullups are inactive). Freescale Semiconductor ...
Page 72
... Full drive for all port C output pins RDPAB — Reduced Drive of Port A and Port B Bit 1 = Reduced drive for all port A and port B output pins 0 = Full drive for all port A and port B output pins RDPH RDPG RDPF RDPE MC68HC812A4 Data Sheet, Rev Bit 0 PRPD RDPC RDPAB Freescale Semiconductor ...
Page 73
... RC clock (if enabled) is stopped. However, the EEPGM control bit remains set. When stop mode is terminated, the program/erase voltage automatically turns back on if EEPGM is set. At low bus frequencies, the RC clock must be turned on for program/erase. Freescale Semiconductor Figure 7-1). For information on remapping the register block and Chapter 5 Operating Modes and Resource MC68HC812A4 Data Sheet, Rev ...
Page 74
... PROG Write: Anytime 74 BPROT6 2 KBYTES BPROT5 1 KBYTE BPROT4 512 BYTES BPROT3 256 BYTES SINGLE-CHIP BPROT2 VECTORS 128 BYTES BPROT1 RESERVED 64 BYTES BPROT0 VECTORS 64 BYTES MC68HC812A4 Data Sheet, Rev. 7 $FF80 64 BYTES $FFBF $FFC0 64 BYTES $FFFF 2 1 Bit 0 EESWAI PROTLCK EERC Freescale Semiconductor ...
Page 75
... Read: Anytime Write: In special modes only (SMODN = 0) These bits are used for test purposes only. In normal modes, the bits are forced to 0. EEODD — Odd Row Programming Bit 1 = Bulk program/erase all odd rows 0 = Odd row bulk programming/erasing disabled Freescale Semiconductor BPROT5 ...
Page 76
... If BYTE = 1 and test mode is not enabled, only the location specified by the address written to the programming latches is erased. The operation is a byte or an aligned word erase depending on the size of written data. 76 pin BYTE ROW MC68HC812A4 Data Sheet, Rev Bit 0 ERASE EELAT EEPGM Freescale Semiconductor ...
Page 77
... Wait for programming ( t PROG 5. Write EEPGM = 0. 6. Write EELAT = 0. By jumping from step 5 to step possible to program/erase more bytes or words without intermediate EEPROM reads. Freescale Semiconductor Table 7-2. Erase Selection Row Block Size 0 Bulk erase entire EEPROM array 1 Row erase 32 bytes ...
Page 78
... EEPROM 78 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 79
... EWEN = 0 $0400–$07FF EWDIR = EWEN = 1 $0400–$07FF EWDIR = 1, EWEN = EWDIR = x, EWEN = 0 Freescale Semiconductor Table 8-1. Memory Expansion Values A19 A18 A17 A16 A15 1 1 PEA17 PEA16 PEA15 PEA14 PEA13 PEA12 PEA11 PEA10 A15 1 1 PEA17 PEA16 PEA15 PEA14 PEA13 PEA12 PEA11 PEA10 ...
Page 80
... MC68HC812A4 Data Sheet, Rev. 7 (1) (Continued) A14 A13 A12 A11 A14 A13 A12 A11 A11 A14 A13 A12 A11 A13 A12 A11 A14 A13 A12 A11 A14 A13 A12 A11 Table 8-2 Freescale Semiconductor A10 A10 A10 A10 A10 A10 A10 shows ...
Page 81
... The data space will be 1 Mbyte of addressable space with 256 4-Kbyte pages and pages $F0 to $F6 mirrored to the $0000 to $6FFF space. The extra space will be 256 Kbytes of addressable space in 256 1-Kbyte pages. Freescale Semiconductor MC68HC812A4 Data Sheet, Rev. 7 Generation of Chip-Selects ...
Page 82
... Makes CS3 follow EPAGE Puts EPAGE at $0400–$07FF Keeps the translated value of the upper addresses the same as it would have been before translation; not necessary if all external devices use chip-selects MC68HC812A4 Data Sheet, Rev KBYTE 256 BYTES 128 BYTES 128 BYTES Freescale Semiconductor ...
Page 83
... EEPROM $2000 $3000 $4000 $5000 $6000 $7000 $8000 $9000 $A000 $B000 $C000 $D000 $E000 $F000 VECTORS $FFFF Figure 8-2. Memory Expansion and Chip-Select Example Register WINDEF MXAR CSCTL0 CSCTL1 MISC Freescale Semiconductor EXTERNAL SPACE CHIP-SELECT 3: (CS3) $0400 TO $07FF PAGE 3 NOTE ...
Page 84
... ECLK PIN Figure 8-6. Chip-Select with 3-Cycle Stretch 84 8-5, and Figure 8-6 show the waveforms for zero to three cycles of UNSTRETCHED BUS CYCLE Figure 8-3. Chip-Select with No Stretch STRETCHED BY 1 CYCLE STRETCHED BY 2 CYCLES STRETCHED BY 3 CYCLES MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 85
... Six port G pins are associated with memory expansion. Any pin not used for memory expansion can be used as general-purpose I/O. All pins are pulled up when inputs (if pullups are enabled). Enabling a memory expansion address with the memory expansion assignment register overrides the associated data direction bit and port data bit. Freescale Semiconductor ...
Page 86
... ADDR20 and ADDR21 are forced enabled by MXAR. Data chip-select (CSD) must be used in conjunction with this memory expansion window DDRF6 DDRF5 DDRF4 DDRF3 DDRG5 DDRG4 DDRG3 PD18 PD17 PD16 PD15 MC68HC812A4 Data Sheet, Rev Bit 0 DDRF2 DDRF1 DDRF0 Bit 0 DDRG2 DDRG1 DDRG0 Bit 0 PD14 PD13 PD12 Freescale Semiconductor ...
Page 87
... Read: DWEN Write: Reset: 0 Figure 8-14. Window Definition Register (WINDEF) Read: Anytime Write: Anytime DWEN — Data Window Enable Bit 1 = Enables paging of the data space (4 Kbytes: $7000–$7FFF) via the DPAGE register 0 = Disables DPAGE Freescale Semiconductor PPA20 PPA19 PPA18 PPA17 0 0 ...
Page 88
... These register-following chip-selects are available in the 512-byte space next to and higher in address than the 512-byte space which includes the registers. For example, if the registers are located at $0800 to $09FF, then these register-following chip-selects are available in the space from $0A00 to $0BFF A21E A20E A19E MC68HC812A4 Data Sheet, Rev Bit 0 A18E A17E A16E Freescale Semiconductor ...
Page 89
... CS1E — Chip-Select 1 Enable Bit CS2 and CS3 have a higher precedence and can override CS1 for a portion of this space Enables this chip-select which covers a 256-byte space following the register space ($x300–$x3FF or $xB00–$xBFF Disables this chip-select Freescale Semiconductor ...
Page 90
... Chip-select 3 follows accesses to the 1-Kbyte extra page ($0400 to $07FF or $0000 to $03FF). Any accesses to this window cause the chip-select to go active. (EWEN must be set to 1 Chip-select 3 includes only accesses to a 128-byte space following the register space CSPA21 CSDHF CS3EP MC68HC812A4 Data Sheet, Rev Bit Freescale Semiconductor ...
Page 91
... Read: Anytime Write: Anytime Address: $003E Bit 7 Read: 0 Write: Reset Unimplemented Figure 8-18. Chip-Select Stretch Register 0 (CSSTR0) Address: $003F Bit 7 Read: STR3A Write: Reset: 0 Figure 8-19. Chip-Select Stretch Register 1 (CSSTR1) Stretch Bit SxxxA Freescale Semiconductor SRP1A SRP1B SRP0A STR3B STR2A STR2B STR1A Table 8-4 ...
Page 92
... Kbyte at either $0000 to $03FF or $0400 to $07FF; (1) — 512 bytes following the 512-byte register space; may (1) — 16 Kbytes fixed at $8000 to $BFFF; may be used with (1) — 4 Kbytes fixed at $7000 to $7FFF; may be used with (1) CS2 CS1 CS0 CSP0 MC68HC812A4 Data Sheet, Rev. 7 Lowest CSD CSP1 Freescale Semiconductor ...
Page 93
... CPU when stop or wait mode. Key wakeups can be used with the pins configured as inputs or outputs. Key wakeup port D shares a vector and control bit with IRQ. IRQEN must be set for key wakeup interrupts to signal the CPU. Freescale Semiconductor Chapter 5 Operating Modes and Resource 6 5 ...
Page 94
... KWIED7–KWIED0 — Key Wakeup Port D Interrupt Enable Bits 1 = Interrupt for the associated bit is enabled Interrupt for the associated bit is disabled Bit 6 Bit 5 Bit 4 Bit Bit 6 Bit 5 Bit 4 Bit MC68HC812A4 Data Sheet, Rev Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 95
... Alternate pin function: KWH7 Figure 9-5. Port H Data Register (PORTH) Read: Anytime Write: Anytime Port H is associated with key wakeup H. Key wakeups can be used with the pins designated as inputs or outputs. DDRH determines whether each pin is an input or output. Freescale Semiconductor Bit 6 Bit 5 ...
Page 96
... Falling edge on the associated bit has occurred (an interrupt occurs if the associated enable bit is set Falling edge on the associated bit has not occurred DDRH6 DDRH5 DDRH4 DDRH3 KWIEH5 KWIEH4 KWIEH3 KWIFH5 KWIFH4 KWIFH3 MC68HC812A4 Data Sheet, Rev Bit 0 DDRH2 DDRH1 DDRH0 Bit 0 KWIEH2 KWIEH1 KWIEH0 Bit 0 KWIFH2 KWIFH1 KWIFH0 Freescale Semiconductor ...
Page 97
... An interrupt is generated when a bit in the KWIFJ register and its corresponding KWIEJ bit are both set. These bits correspond to the pins of port J. All eight bits/pins share the same interrupt vector. KWIEJ7–KWIEF0 — Key Wakeup Port J Interrupt Enable Bits 1 = Interrupt for the associated bit is enabled Interrupt for the associated bit is disabled. Freescale Semiconductor PJ6 ...
Page 98
... Rising edge on the associated port J pin sets the associated flag bit in the KWIFJ register Falling edge on the associated port J pin sets the associated flag bit in the KWIFJ register KWIFJ6 KWIFJ5 KWIFJ4 KWIFJ3 KPOLJ6 KPOLJ5 KPOLJ4 KPOLJ3 MC68HC812A4 Data Sheet, Rev Bit 0 KWIFJ2 KWIFJ1 KWIFJ0 Bit 0 KPOLJ2 KPOLJ1 KPOLJ0 Freescale Semiconductor ...
Page 99
... Each bit in the register corresponds to a port J pin pin is configured as an input, each bit enables an active pullup or pulldown device. PUPSJ selects whether a pullup or a pulldown is the active device. PULEJ7–PULEJ0 — Key Wakeup Port J Pullup/Pulldown Enable Bits 1 = Selected pullup/pulldown device for the associated port J pin is enabled input Associated port J pin has no pullup/pulldown device. Freescale Semiconductor ...
Page 100
... Key Wakeups 100 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 101
... E-clock — Drives the bus interfaces, BDM, SPI, and ATD 3. P-clock — Drives the bus interfaces, BDM, SPI, and ATD 4. M-clock — Drives on-chip modules such as the timer, SCI, RTI, COP, and restart-from-stop delay time Freescale Semiconductor REGISTER: CLKCTL BITS: BCS[C:B:A] 0:0:0 SYSCLK ÷ ...
Page 102
... Figure 10-3. Clock Function Register Map 102 NOTE Bit RTIE RSWAI RSBCK RTIF CME FCME FCM FCOP Bit 7 Bit 6 Bit 5 Bit Unimplemented MC68HC812A4 Data Sheet, Rev Bit 0 RTBYP RTR2 RTR1 RTR0 DISR CR2 CR1 CR0 Bit 3 Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 103
... Clock monitor is disabled. Slow clocks and STOP instruction may be used. Clock monitor timeouts are shown in 10.4.4 Peripheral Clock Divider Chains Figure 10-4, Figure 10-5, and Figure 10-6 Freescale Semiconductor Table 10-1. Table 10-1. Clock Monitor Timeouts Supply 5 V ± 10 ± 10% 5–100 µs summarize the peripheral clock divider chains ...
Page 104
... TO COP TO RTI REGISTER: PACTL BITS: PAEN:CLK1:CLK0 0:X:X 1:0:0 1:0:1 1:1:0 PACLK 256 1:1:1 PACLK PULSE 65,536 ACCUMULATOR (PAOV) HIGH BYTE COUNTER Freescale Semiconductor TO TIM ...
Page 105
... Write: Reset Unimplemented Figure 10-7. Real-Time Interrupt Control Register (RTICTL) Read: Anytime Write: Varies from bit to bit Freescale Semiconductor ÷ 2 ATD CLOCK ECLK BDM BIT CLOCK BKGD IN Receive: Detect falling edge; count 12 E-clocks; sample input Transmit 1: Detect falling edge; count six E-clocks while output is high impedance ...
Page 106
... Table 10-2. Real-Time Interrupt Rates Real-Time Timeout Period M-Clock Divisor M = 4.0 MHz Off Off 13 2.048 4.096 8.196 16.384 32.768 65.536 131. MC68HC812A4 Data Sheet, Rev 8.0 MHz Off 1.024 ms 2.048 ms 4.096 ms 8.196 ms 16.384 ms 32.768 ms 65.536 ms Freescale Semiconductor ...
Page 107
... FCME forces the clock monitor to be enabled until a reset occurs. When FCME is set, the CME bit has no effect Clock monitor enabled 0 = CME bit enables or disables clock monitor Clear the FCME bit in applications that use the STOP instruction and the clock monitor. Freescale Semiconductor ...
Page 108
... Table 10-3. COP Watchdog Rates COP Timeout Period M-Clock Divisor 0/+2.048 4.0 MHz Off Off 13 2.048 8.1920 32.768 131.072 524.288 1.048 2.097 s 2 MC68HC812A4 Data Sheet, Rev. 7 0/+1.024 8.0 MHz Off 1.024 ms 4.096 ms 16.384 ms 65.536 ms 262.144 ms 524.288 ms 1.048576 s Freescale Semiconductor ...
Page 109
... Figure 10-10. Arm/Reset COP Timer Register (COPRST) To restart the COP timeout period and avoid a COP reset, write $55 and then $AA to this address before the end of the COP timeout period. Other instructions can be executed between these writes. Writing anything other than $55 or $AA causes a COP reset to occur. Freescale Semiconductor ...
Page 110
... Clock Module 110 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 111
... Figure 11-2 provides a register map. 11.2 Block Diagram XTAL PIN OSCILLATOR TO MPU MCLK MODULE CLOCK TO MODULES DIVIDER MCS[B:A] Freescale Semiconductor ) rate assuming an input clock of 16.8 MHz Out Figure 11-1 shows the PLL dividers and a portion of the RDV[11:0] EXTAL PIN f Reference REFERENCE DIVIDER ...
Page 112
... Figure 11-2. PLL Register Map MC68HC812A4 Data Sheet, Rev. 7 Crystal 32,000 64,000 1,000,000 1,500,000 1,800,000 2,000,000 2,500,000 3,000,000 3,500,000 4,000,000 4,900,000 5,000,000 Bit 0 LDV11 LDV10 LDV9 LDV8 LDV3 LDV2 LDV1 LDV0 RDV11 RDV10 RDV9 RDV8 RDV3 RDV2 RDV1 RDV0 BCSB BCSA MCSB MCSA Freescale Semiconductor ...
Page 113
... Figure 11-4. Loop Divider Register Low (LDVL) Read: Anytime Write: Anytime If the PLL is on, the count in the loop divider (LDV) 12-bit register effectively multiplies up from the PLL base frequency. Do not exceed the maximum rated operating frequency for the CPU. Freescale Semiconductor ...
Page 114
... PLL not locked PLLON — PLL On Bit Setting PLLON turns on the PLL PLL PLL off 114 RDV11 RDV6 RDV5 RDV4 RDV3 PLLON PLLS BCSC BCSB MC68HC812A4 Data Sheet, Rev Bit 0 RDV10 RDV9 RDV8 Bit 0 RDV2 RDV1 RDV0 Bit 0 BCSA MCSB MCSA Freescale Semiconductor ...
Page 115
... CPU clock rate without affecting the MCLK rate; timing and baud rates can remain constant as the processor speed is changed to match system requirements. This can save overall system power. Freescale Semiconductor 11-2. SYSCLK and is twice the bus rate. MUXCLK is either the PLL Table 11-2. Base Clock Selection ...
Page 116
... Phase-Lock Loop (PLL) 116 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 117
... This register map shows default addressing after reset. In normal modes, writing to a reserved bit has no effect and reading returns logic 0. In any mode, writing to an unimplemented bit has no effect and reading returns a logic 0. Freescale Semiconductor 12-1. Figure NOTE MC68HC812A4 Data Sheet, Rev. 7 12-2. ...
Page 118
... Figure 12-1. Timer Block Diagram MC68HC812A4 Data Sheet, Rev. 7 INTERRUPT INTERRUPT REQUEST LOGIC CH. 0 CAPTURE PT0 PAD LOGIC CH. 0 COMPARE CH. 1 CAPTURE PT1 PAD LOGIC CH. 1 COMPARE CH. 7 CAPTURE PA INPUT PT7 PAD LOGIC CH. 7 COMPARE EDGE DETECT PAIF MODULE CLOCK Freescale Semiconductor ...
Page 119
... See page 130. Reset: Read: Timer Control $008B Register 4 (TCTL4) Write: See page 130. Reset: Read: Timer Mask Register 1 $008C (TMSK1) Write: See page 130. Reset: Figure 12-2. I/O Register Summary (Sheet Freescale Semiconductor Bit IOS7 IOS6 IOS5 IOS4 FOC7 FOC6 FOC5 FOC4 ...
Page 120
... C7F C6F C5F C4F TOF Bit Bit Bit Bit Bit Bit Bit Bit Bit Unimplemented R MC68HC812A4 Data Sheet, Rev Bit 0 TCRE PR2 PR1 PR0 C3F C2F C1F C0F Bit Bit Bit Bit Bit Bit Bit Bit Bit Reserved Freescale Semiconductor ...
Page 121
... Reset: See page 136. Pulse Accumulator Read: Counter Register Low Write: $00A3 (PACNTL) Reset: See page 136. Read: Timer Test Register $00AD (TIMTST) Write: See page 137. Reset: Figure 12-2. I/O Register Summary (Sheet Freescale Semiconductor Bit Bit Bit ...
Page 122
... The output mode and level bits, OMx and OLx, select set, clear, or toggle on output compare. Clearing both OMx and OLx disconnects the pin from the output logic. 122 Bit PT7 PT6 PT5 PT4 Unaffected by reset Bit Unimplemented R MC68HC812A4 Data Sheet, Rev Bit 0 PT3 PT2 PT1 PT0 Bit Reserved Freescale Semiconductor 0 ...
Page 123
... The PA overflow flag, PAOVF, is set when the PA rolls over from $FFFF to $0000. The PA overflow interrupt enable bit, PAOVI, enables the PAOVF flag to generate interrupt requests. The PA can operate in event counter mode even when the timer enable bit, TE, is clear. Freescale Semiconductor NOTE NOTE MC68HC812A4 Data Sheet, Rev. 7 ...
Page 124
... The timer prescaler generates the divided-by-64 clock. If the timer is not active, there is no divided-by-64 clock. Figure 12-3. Channel 7 Output Compare/Pulse Accumulator Logic 124 NOTE NOTE PULSE ACCUMULATOR CHANNEL 7 OUTPUT COMPARE OM7 OL7 OC7M7 MC68HC812A4 Data Sheet, Rev. 7 PAD Freescale Semiconductor ...
Page 125
... Read: Anytime; always read $00 (1 state is transient) Write: Anytime FOC7–FOC0 — Force Output Compare Bits Setting an FOCx bit causes an immediate output compare on the corresponding channel. Forcing an output compare does not set the output compare flag Force output compare effect Freescale Semiconductor IOS6 IOS5 ...
Page 126
... A successful channel 7 output compare overrides any channel 0–6 compares. For each OC7M bit that is set, the output compare action reflects the corresponding OC7D bit. 126 OC7M6 OC7M5 OC7M4 OC7M3 OC7D6 OC7D5 OC7D4 OC7D3 NOTE MC68HC812A4 Data Sheet, Rev Bit 0 OC7M2 OC7M1 OC7M0 Bit 0 OC7D2 OC7D1 OC7D0 Freescale Semiconductor ...
Page 127
... TEN — Timer Enable Bit TEN enables the timer. Clearing TEN reduces power consumption Timer enabled 0 = Timer and timer counter disabled When the timer is disabled, there is no divided-by-64 clock for the PA since the prescaler generates the M ÷ 64 clock. Freescale Semiconductor Bit 14 ...
Page 128
... When TFFCA is clear, writing logic 1s to the flags clears them Fast flag clearing 0 = Normal flag clearing READ TCx REGISTERS WRITE TCx REGISTERS 128 NOTE NOTE WRITE TFLG1 REGISTER DATA BIT n CnF TFFCA Figure 12-11. Fast Clear Flag Logic MC68HC812A4 Data Sheet, Rev. 7 CLEAR CnF FLAG Freescale Semiconductor ...
Page 129
... Table 12-1. Selection of Output Compare Action OMx:OLx Channel 7 shares a pin with the pulse accumulator input pin. To use the PAI input, clear both the OM7 and OL7 bits and clear the OC7M7 bit in the output compare 7 mask register. Freescale Semiconductor OL7 OM6 OL6 ...
Page 130
... Input capture disabled Input capture on rising edges only Input capture on falling edges only Input capture on any edge (rising or falling C6I C5I C4I C3I MC68HC812A4 Data Sheet, Rev Bit 0 EDG5A EDG4B EDG4A Bit 0 EDG1A EDG0B EDG0A Bit 0 C2I C1I C0I Freescale Semiconductor ...
Page 131
... When the timer channel 7 registers contain $FFFF and TCRE is set, TOF never gets set even though the timer counter registers go from $FFFF to $0000. PR2, PR1, and PR0 — Timer Prescaler Select Bits These bits select the prescaler divisor for the timer counter. Value Freescale Semiconductor PUPT RDPT TCRE 0 1 ...
Page 132
... Unimplemented Figure 12-19. Timer Flag Register 2 (TFLG2) Read: Anytime Write: Anytime; writing 1 clears flag; writing 0 has no effect 132 PR[2:1:0] Prescaler Divisor 101 110 111 NOTE C6F C5F C4F C3F NOTE MC68HC812A4 Data Sheet, Rev Bit 0 C2F C1F C0F Bit Freescale Semiconductor ...
Page 133
... When a channel is configured for input capture (IOSx = 0), the timer channel registers latch the value of the free-running counter when a defined transition occurs on the corresponding input capture pin. When a channel is configured for output compare (IOSx = 1), the timer channel registers contain the output compare value. Freescale Semiconductor NOTE NOTE 6 ...
Page 134
... To operate in gated time accumulation mode: 1. Apply logic 0 to the RESET pin. 2. Initialize registers for pulse accumulator mode test. 3. Apply appropriate level on PAI pin. 4. Enable the timer. 134 PAEN PAMOD PEDGE CLK1 NOTE NOTE MC68HC812A4 Data Sheet, Rev Bit 0 CLK0 PAOVI PAI Freescale Semiconductor ...
Page 135
... PAOVF — Pulse Accumulator Overflow Flag PAOVF is set when the 16-bit pulse accumulator overflows from $FFFF to $0000. Clear PAOVF by writing to the pulse accumulator flag register with PAOVF set Pulse accumulator overflow pulse accumulator overflow Freescale Semiconductor Table 12-4. Clock Selection CLK[1:0] Timer Counter Clock 00 ...
Page 136
... PAI pin may miss the last count since the input has to be synchronized with the bus clock first. 136 NOTE Bit 14 Bit 13 Bit 12 Bit Bit 6 Bit 5 Bit 4 Bit Registers (PACNTH/L) NOTE MC68HC812A4 Data Sheet, Rev Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 137
... The timer port data direction register does not affect the data direction of an output compare pin. The output compare function overrides the data direction register but does not affect the state of the data direction register. Freescale Semiconductor ...
Page 138
... Setting TSWAI does not affect the state of the timer enable bit, TEN, or the pulse accumulator enable bit, PAEN. 12.8.3 Stop Mode The STOP instruction disables the timer for reduced power consumption. 138 NOTE NOTE MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 139
... Reading an input (data direction bit = 0) reads the pin state; reading an output (data direction bit = 1) reads the latch. Writing to a pin configured as a timer output does not change the pin state. Freescale Semiconductor Table 12-5. Timer Interrupt Sources Local Flag ...
Page 140
... Table 12-6. TIMPORT I/O Function Output Compare Reading Action at Data Bus 0 Pin 1 Pin 1 Port data register 0 Port data register NOTE MC68HC812A4 Data Sheet, Rev. 7 Out Reading at Pin Pin Output compare action Output compare action Port data register 2 1 Bit Bit Freescale Semiconductor ...
Page 141
... For this exercise, use the M68HC812A4EVB emulation board. 12.11.3 Code Listing A comment line is delimited by a semicolon. If there is no code before comment, a semicolon (;) must be placed in the first column to avoid assembly errors. Freescale Semiconductor Using the Output Compare Function to Generate a Square Wave 1 ms NUMBER OF CLOCKS = THEREFORE, # CLOCKS = (2 MHz ...
Page 142
... To clear OC2 Flag, first it must be read, ; then a "1" must be written Loads value of compare from TC2 Reg. ; Add hex value of 500us High Time ; Set-up next transition time in 500 us ; Continuously add 500 us, branch to CLEARFLAG ; return from Subroutine ; End of program MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 143
... Receiver overrun – Idle receiver input • Receiver noise error detection • Receiver framing error detection • Receiver parity error detection For additional information, refer to Freescale Semiconductor NOTE Ports. Chapter 14 Serial Communications Interface Module MC68HC812A4 Data Sheet, Rev. 7 (SCI). 143 ...
Page 144
... MSI Block Diagram MSI Figure 13-1. Multiple Serial Interface Block Diagram 144 Chapter 15 Serial Peripheral Interface (SPI) RxD0 SCI0 TxD0 RxD1 SCI1 TxD1 MOSI/MOMI MISO/SISO SPI0 SCK CS/SS MC68HC812A4 Data Sheet, Rev. 7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 Freescale Semiconductor ...
Page 145
... Low (SC1BDL) Write: See page 168. Reset: Read: SCI 1 Control Register 1 $00CA (SC1CR1) Write: See page 169. Reset: Read: SCI 1 Control Register 2 $00CB (SC1CR2) Write: See page 171. Reset: Freescale Semiconductor Bit BTST BSPL BRLD SBR12 SBR7 SBR6 SBR5 SBR4 0 0 ...
Page 146
... Unaffected by reset DDRS7 DDRS6 DDRS5 DDRS4 Unimplemented Chapter 14 Serial Communications Interface Module (SCI) (SPI). MC68HC812A4 Data Sheet, Rev Bit RAF CPOL CPHA SSOE LSBF PUPS RDS SPC0 SPR2 SPR1 SPR0 PS3 PS2 PS1 PS0 DDRS3 DDRS2 DDRS1 DDRS0 and Freescale Semiconductor ...
Page 147
... A write to a port S bit is stored in an internal latch. The latch drives the pin only when the corresponding data direction bit is set. Writes do not change the pin state when the pin is configured for SCI output. Freescale Semiconductor ...
Page 148
... Setting PUPS enables internal pullup devices on all port S input pins pin is programmed as output, the pullup device becomes inactive Pullups enabled 0 = Pullups disabled 148 DDRS6 DDRS5 DDRS4 DDRS3 NOTE PUPS MC68HC812A4 Data Sheet, Rev Bit 0 DDRS2 DDRS1 DDRS0 Bit 0 0 RDS SPC0 Freescale Semiconductor ...
Page 149
... SPC0 — See Chapter 14 Serial Communications Interface Module 13.6.4 Port S Wired-OR Mode Control Table 13-2. Port S Wired-OR Mode Enable Register SPI control register 1 (SP0CR1) SCI0 control register 1 (SC0CR1) SCI1 control register 1 (SC1CR1) Freescale Semiconductor Pullups Control Pins Reset Bit Affected State PUPS PS7– ...
Page 150
... Multiple Serial Interface (MSI) 150 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 151
... Five flags with interrupt-generation capability: – Transmitter empty – Transmission complete – Receiver full – Receiver overrun – Idle receiver input • Receiver noise error detection • Receiver framing error detection • Receiver parity error detection Freescale Semiconductor MC68HC812A4 Data Sheet, Rev. 7 151 ...
Page 152
... PORT S DATA DIRECTION REGISTER PORT S DATA REISTER RXD0 TXD0 RXD1 TXD1 Figure 14-1. SCI Block Diagram MC68HC812A4 Data Sheet, Rev SCI RAF ILIE INTERRUPT IDLE REQUEST RDRF SCI INTERRUPT OR REQUEST RIE SCI TIE INTERRUPT TDRE REQUEST SCI TC INTERRUPT TCIE REQUEST Freescale Semiconductor ...
Page 153
... Write: See page 174. Reset: Read: SCI 0 Data Register Low $00C7 (SC0DRL) Write: See page 174. Reset: Read: SCI 1 Baud Rate Register $00C8 High (SC1BDH) Write: See page 168. Reset: Freescale Semiconductor NOTE Bit BTST BSPL BRLD SBR12 SBR7 SBR6 SBR5 ...
Page 154
... Figure 14-2. SCI Register Map (Continued) 154 Bit SBR7 SBR6 SBR5 SBR4 LOOPS WOMS RSRC TIE TCIE RIE ILIE TDRE TC RDRF IDLE Unaffected by reset Unaffected by reset = Unimplemented MC68HC812A4 Data Sheet, Rev Bit 0 SBR3 SBR2 SBR1 SBR0 WAKE ILT RWU SBK RAF Freescale Semiconductor ...
Page 155
... A frame with nine data bits has a total of 11 bits. Start Bit The address bit identifies the frame as an address character. See Receiver Freescale Semiconductor 8-BIT DATA FORMAT BIT M IN SCCR1 CLEAR BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 9-BIT DATA FORMAT ...
Page 156
... Figure 14-4. MC68HC812A4 Data Sheet, Rev. 7 Target Error (%) (3) Baud Rate 38,400 2.3 19,200 0.62 9600 0.62 4800 0.14 2400 0.14 1200 0.11 600 0.05 300 0.00 150 0.00 110 0.00 Freescale Semiconductor ...
Page 157
... The transmit data register empty flag, TDRE, in SCI status register 1 (SCSR1) becomes set when the SCI data register transfers a byte to the transmit shift register. The TDRE flag indicates that the SCI data Freescale Semiconductor INTERNAL BUS ³ 16 ...
Page 158
... If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the frame currently being transmitted. 158 1) MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 159
... The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCCR1) determines the length of data characters. When receiving 9-bit data, bit R8 in SCI data register high (SCDRH) is the ninth bit (bit 8). Freescale Semiconductor NOTE Figure 14-5 ...
Page 160
... START BIT START BIT START BIT QUALIFICATION VERIFICATION SAMPLING Figure 14-6. Receiver Data Sampling Table 14-4. Start Bit Verification Start Bit Verification Yes Yes Yes No Yes MC68HC812A4 Data Sheet, Rev. 7 Figure 14- DATA Noise Flag Freescale Semiconductor LSB Table ...
Page 161
... The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found. Freescale Semiconductor Table 14-5. Data Bit Recovery Data Bit Determination ...
Page 162
... Figure 14-7. Start Bit Search Example 1 PERCEIVED START BIT ACTUAL START BIT Figure 14-8. Start Bit Search Example 2 PERCEIVED START BIT ACTUAL START BIT Figure 14-9. Start Bit Search Example 3 MC68HC812A4 Data Sheet, Rev. 7 START BIT Freescale Semiconductor LSB LSB LSB ...
Page 163
... RT clock. In start bits only, the RT8, RT9, and RT10 data samples are ignored. RXD SAMPLES CLOCK RT CLOCK COUNT RESET RT CLOCK Figure 14-12. Start Bit Search Example 6 Freescale Semiconductor PERCEIVED AND ACTUAL START BIT ...
Page 164
... Figure 14-13. Slow Data Figure 14-13, the receiver counts 154 RT cycles at the point when 154 147 – × 100 = 4.54% ------------------------- - 154 Figure 14-13, the receiver counts 170 RT cycles at the point when 170 163 – × 100 = 4.12% ------------------------- - 170 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 165
... Idle input line wakeup (WAKE = 0) — In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which Freescale Semiconductor STOP IDLE OR NEXT FRAME ...
Page 166
... TXD as the input for received data. DDRS BIT = 1 DDRS BIT = 0 Figure 14-15. Single-Wire Operation (LOOPS = 1 and RSRC = 1) 166 NOTE TRANSMITTER WOMS RECEIVER TRANSMITTER NC RECEIVER MC68HC812A4 Data Sheet, Rev. 7 TXD GENERAL- RXD PURPOSE I/O TXD GENERAL- RXD PURPOSE I/O Freescale Semiconductor ...
Page 167
... Both the transmitter and receiver must be enabled ( and RE = 1). The wired-OR mode select bit, WOMS, configures the TXD pin for full CMOS drive or for open-drain drive. WOMS controls the TXD pin in both normal operation and in loop operation. Freescale Semiconductor TRANSMITTER WOMS RECEIVER ...
Page 168
... The baud rate generator is disabled until the TE bit or the RE bit is set for the first time after reset. The baud rate generator is disabled when 168 BRLD SBR12 SBR11 SBR5 SBR4 SBR3 MCLK SCI baud rate = -------------------- - × NOTE MC68HC812A4 Data Sheet, Rev Bit 0 SBR10 SBR9 SBR8 Bit 0 SBR2 SBR1 SBR0 Freescale Semiconductor ...
Page 169
... When LOOPS = 1, the RSRC bit determines the internal feedback path for the receiver Receiver input connected to TXD pin 0 = Receiver input internally connected to transmitter output (1) LOOPS RSRC DDRSx Freescale Semiconductor RSRC M WAKE Table 14-7. Table 14-7. Loop Mode Functions WOMS X Normal operation Loop mode; transmitter output connected to receiver input ...
Page 170
... WOMS Function of TXD Pin Single-wire mode; transmitter output disconnected x TXD is high-impedance receiver input 0 Single-wire mode; TXD pin connected to receiver input Single wire mode; TXD pin connected to receiver input 1 TXD is open-drain for receiving and transmitting MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 171
... RE enables the SCI receiver Receiver enabled 0 = Receiver disabled RWU — Receiver Wakeup Bit 1 = Standby state 0 = Normal operation RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. Freescale Semiconductor TCIE RIE ILIE ...
Page 172
... Receiver input is either active now or has never become active since the IDLE flag was last cleared When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag. 172 RDRF IDLE NOTE MC68HC812A4 Data Sheet, Rev Bit Freescale Semiconductor ...
Page 173
... RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects false start bits (usually from noise or baud rate mismatch) or when the receiver detects an idle character Reception in progress reception in progress Freescale Semiconductor ...
Page 174
... In 8-bit data format, only SCI data register low (SCDRL) needs to be accessed. When transmitting in 9-bit data format and using 8-bit write instructions, write first to SCI data register high (SCDRH). 174 Unaffected by reset Unaffected by reset NOTE MC68HC812A4 Data Sheet, Rev Bit Bit Freescale Semiconductor ...
Page 175
... For reduced power consumption, the SCI is inactive in stop mode. The STOP instruction does not affect SCI register states. SCI operation resumes after an external interrupt. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI. Freescale Semiconductor MC68HC812A4 Data Sheet, Rev. 7 External Pin Descriptions ...
Page 176
... For this exercise, use the M68HC812A4EVB emulation board. 176 Table 14-8. SCI Interrupt Sources Local Flag Enable TDRE TIE TC TCIE RDRF RIE OR IDLE ILIE MC68HC812A4 Data Sheet, Rev. 7 Vector CCR Address Mask SCI0 SCI1 I bit I bit $FFD6, $FFD4, $FFD7 $FFD5 I bit I bit Chapter 13 Multiple Serial Freescale Semiconductor ...
Page 177
... DC.B 'Scottsdale, Arizona' DC.B $0D,$0A EOT: DC.B $04 END Freescale Semiconductor NOTE ; Equates for registers ; 16K On-Board RAM, User code data area, ; start main program at $4000 ; Subroutine to Initialize SCI0 registers ; Subroutine to start transmission ; Always branch to DONE, convenient for breakpoint ; Transfer CCR to A accumulator ...
Page 178
... Serial Communications Interface Module (SCI) 178 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 179
... Transmission complete – Mode fault • Write collision detection • Read data buffer • Serial clock with programmable polarity and phase • Reduced drive control for lower power consumption • Programmable open-drain output option Freescale Semiconductor MC68HC812A4 Data Sheet, Rev. 7 179 ...
Page 180
... SPIF INTERRUPT REQUEST SPIE Figure 15-1. SPI Block Diagram MC68HC812A4 Data Sheet, Rev. 7 SPI DATA REGISTER (WRITE) SHIFT REGISTER SPI DATA REGISTER (READ) LSBF PIN CONTROL LOGIC PORT S DATA DIRECTION REGISTER PORT S DATA REGISTER MISO OR SISO MOSI OR MOMI SCK SS Freescale Semiconductor ...
Page 181
... SPI Data Register $00D5 (SP0DR) Write: See page 190. Reset: Read: Port S Data Register $00D6 (PORTS) Write: See page 147. Reset: Read: Port S Data Direction $00D7 Register (DDRS) Write: See page 148. Reset: Freescale Semiconductor NOTE Bit SPIE SPE SWOM MSTR ...
Page 182
... As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register. On the eighth serial clock cycle, the transmission ends and sets the SPI flag, SPIF. At the same time that SPIF 182 NOTE MISO MISO MOSI MOSI SCK SCK NOTE MC68HC812A4 Data Sheet, Rev. 7 SLAVE MCU SHIFT REGISTER Freescale Semiconductor ...
Page 183
... FROM SLAVE SS TO SLAVE CAPTURE STROBE MSB FIRST (LSBF = 0) MSB LSB FIRST (LSBF = 1) LSB MINIMUM and t = 1/2 SCK CYCLE Figure 15-4. Transmission Format 0 (CPHA = 0) Freescale Semiconductor NOTE BIT 6 BIT 5 BIT 4 BIT 3 BIT 1 BIT 2 BIT 3 BIT 4 MC68HC812A4 Data Sheet, Rev. 7 Functional Description ...
Page 184
... Figure 15-6. Transmission Format 1 (CPHA = 1) MISO/MOSI MASTER SS SLAVE SS CPHA = 1 184 BYTE 1 BYTE 2 NOTE BIT 6 BIT 5 BIT 4 BIT 3 BIT 1 BIT 2 BIT 3 BIT 4 BYTE 1 BYTE 2 Figure 15-7. Slave SS When CPHA = 1 MC68HC812A4 Data Sheet, Rev. 7 BYTE 3 END t T TRANSFER BIT 2 BIT 1 LSB BIT 5 BIT 6 MSB BYTE 3 Freescale Semiconductor ...
Page 185
... Setting serial pin control bit 0, SPC0, configures the SPI for single-wire operation. The direction of the single-wire pin depends on its data direction bit. MASTER MODE SLAVE MODE Figure 15-8. Single-Wire Operation (SPC0 = 1) Freescale Semiconductor Table 15-1. SS Pin Configurations SS Pin Function Master Mode Slave-select input with mode-fault detection ...
Page 186
... CPHA determines whether transmission begins on the falling edge of the SS pin or on the first edge of the serial clock. See Figure 15 Transmission at first SCK edge 0 = Transmission at falling SS edge 186 SPE SWOM MSTR CPOL NOTE and Figure 15-6. MC68HC812A4 Data Sheet, Rev Bit 0 CPHA SSOE LSBF Figure 15-4 Freescale Semiconductor and ...
Page 187
... Setting RDS lowers the drive capability of all port S output pins for lower power consumption and less noise Reduced drive 0 = Normal drive SPC0 — Serial Pin Control Bit 0 SPC0 enables single-wire operation of the MOSI and MISO pins. Control Bits SPC0 MSTR Freescale Semiconductor SPI Register Descriptions and Reset Initialization PUPS 0 0 ...
Page 188
... MC68HC812A4 Data Sheet, Rev Bit 0 SPR2 SPR1 SPR0 15-3. Reset clears SPR2–SPR0, Baud Rate (E-Clock = 8 MHz) 4.0 MHz 2.0 MHz 1.0 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.3 kHz Freescale Semiconductor ...
Page 189
... DDR7 = 0). Clear MODF by reading the SPI status register with MODF set and then writing to SPI control register Mode fault mode fault MODF is inhibited when the PS7 pin is configured as: • The SS output, DDRS7 = 1 and SSOE = 1, or • A general-purpose output, DDRS7 = 1 and SSOE = 0 Freescale Semiconductor SPI Register Descriptions and Reset Initialization WCOL ...
Page 190
... SCK pin is the clock output to the slave slave MCU, the SCK pin is the clock input from the master. 190 Unaffected by reset 2 C) capability (requiring software support master peripherals, MOSI becomes an open-drain output 2 C communication, the MOSI and MISO pins are 2 C peripheral and through a pullup resistor to V MC68HC812A4 Data Sheet, Rev Bit Bit Freescale Semiconductor ...
Page 191
... For reduced power consumption, the SPI is inactive in stop mode. The STOP instruction does not affect SPI register states. SPI operation resumes after an external interrupt. Exiting stop mode by reset aborts any transmission in progress and resets the SPI. Entering stop mode during a transmission results in invalid data. Freescale Semiconductor MC68HC812A4 Data Sheet, Rev. 7 Low-Power Options 191 ...
Page 192
... On-Board RAM, User code data area, ; start main program at $7000 ; Subroutine to initialize SPI registers ; Subroutine to start transmission ; Finished transmitting all DATA MC68HC812A4 Data Sheet, Rev. 7 CCR Vector Mask Address I bit $FFD8, $FFD9 Chapter 13 Multiple Serial Freescale Semiconductor ...
Page 193
... DC.B $0D,$0A EOT: DC.B $00 END Freescale Semiconductor Synchronous Character Transmission Using the SPI ; SET SS Line High to prevent glitch ; Configure PORT S input/ouput levels ; MOSI, SCK, SS* = ouput, MISO=Input ; Select serial clock baud rate < 100 KHz ; Configure SPI(SP0CR1): No SPI interrupts, ; MSTR=1, CPOL=0, CPHA=0 ...
Page 194
... Serial Peripheral Interface (SPI) 194 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 195
... Features Features of the ATD module include: • Eight multiplexed input channels • Multiplexed-input successive approximation • 8-bit resolution • Single or continuous conversion • Conversion complete flag with CPU interrupt request • Selectable ATD clock Freescale Semiconductor MC68HC812A4 Data Sheet, Rev. 7 195 ...
Page 196
... CHANNEL 0 SAMPLE BUFFER AMP CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 CLOCK SELECT/PRESCALE Figure 16-1. ATD Block Diagram MC68HC812A4 Data Sheet, Rev DDA V SSA AN7/PAD7 AN6/PAD6 AN5/PAD5 ANALOG MUX AND AN4/PAD4 AN3/PAD3 AN2/PAD2 AN1/PAD1 AN0/PAD0 PORT AD DATA INPUT REGISTER Freescale Semiconductor ...
Page 197
... Reset: Read: ATD Status Register 2 $0067 (ATDSTAT2) Write: See page 204. Reset: Read: ATD Test Register 1 $0068 (ATDTEST1) Write: See page 205. Reset: Read: ATD Test Register 2 $0069 (ATDTEST2) Write: See page 205. Reset: Freescale Semiconductor NOTE Bit ADPU AFFC AWAI 0 0 ...
Page 198
... MC68HC812A4 Data Sheet, Rev Bit 0 PAD3 PAD2 PAD1 PAD0 ADRxH3 ADRxH2 ADRxH1 ADRxH0 ADRxH3 ADRxH2 ADRxH1 ADRxH0 ADRxH3 ADRxH2 ADRxH1 ADRxH0 ADRxH3 ADRxH2 ADRxH1 ADRxH0 ADRxH3 ADRxH2 ADRxH1 ADRxH0 ADRxH3 ADRxH2 ADRxH1 ADRxH0 ADRxH3 ADRxH2 ADRxH1 ADRxH0 ADRxH3 ADRxH2 ADRxH1 ADRxH0 Freescale Semiconductor ...
Page 199
... ATD Control Register 0 Address: $0060 Bit 7 Read: 0 Write: Reset: 0 Figure 16-3. ATD Control Register 0 (ATDCTL0) Writing to this register aborts the current conversion sequence. 16.6.2 ATD Control Register 1 Address: $0061 Bit 7 Read: 0 Write: Reset Unimplemented Figure 16-4. ATD Control Register 1 (ATDCTL1) Freescale Semiconductor NOTE ...
Page 200
... Conversion sequence complete 0 = Conversion sequence not complete The ASCIF flag is set only when a conversion sequence is completed and ASCIE = 1 or interrupts on the analog-to-digital converter (ATD) module are enabled. 200 AFFC AWAI NOTE NOTE NOTE MC68HC812A4 Data Sheet, Rev Bit 0 0 ASCIF ASCIE Freescale Semiconductor ...