MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 173

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

OR — Overrun Flag
NF — Noise Flag
FE — Framing Error Flag
PF — Parity Error Flag
14.6.5 SCI Status Register 2
Read: Anytime
Write: Has no meaning or effect
RAF — Receiver Active Flag
Freescale Semiconductor
OR is set when software fails to read the SCI data register before the receive shift register receives
the next frame. The data in the shift register is lost, but the data already in the SCI data registers is not
affected. Clear OR by reading SCI status register 1 with OR set and then reading the low byte of the
SCI data register.
NF is set when the SCI detects noise on the receiver input. NF is set during the same cycle as the
RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1
and then reading the low byte of the SCI data register.
FE is set when a logic 0 is accepted as the stop bit. FE is set during the same cycle as the RDRF flag
but does not get set in the case of an overrun. FE inhibits further data reception until it is cleared. Clear
FE by reading SCI status register 1 with FE set and then reading the low byte of the SCI data register.
PF is set when the parity enable bit, PE, is set and the parity of the received data does not match its
parity bit. Clear PF by reading SCI status register 1 and then reading the low byte of the SCI data
register.
RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF
is cleared when the receiver detects false start bits (usually from noise or baud rate mismatch) or when
the receiver detects an idle character.
1 = Overrun
0 = No overrun
1 = Noise
0 = No noise
1 = Framing error
0 = No framing error
1 = Parity error
0 = No parity error
1 = Reception in progress
0 = No reception in progress
Reset:
Read:
Write:
SCI0: $00C5
SCI1: $00CD
Figure 14-22. SCI Status Register 2 (SC0SR2 or SC1SR2)
Bit 7
0
0
= Unimplemented
6
0
0
MC68HC812A4 Data Sheet, Rev. 7
5
0
0
4
0
0
3
0
0
Register Descriptions and Reset Initialization
2
0
0
1
0
0
Bit 0
RAF
0
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