MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 131

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.5.10 Timer Mask Register 2
Read: Anytime
Write: Anytime
TOI — Timer Overflow Interrupt Enable Bit
PUPT — Port T Pullup Enable Bit
RDPT — Port T Reduced Drive Bit
TCRE — Timer Counter Reset Enable Bit
PR2, PR1, and PR0 — Timer Prescaler Select Bits
Freescale Semiconductor
TOI enables interrupt requests generated by the TOF flag.
PUPT enables pullup resistors on the timer port pins when the pins are configured as inputs.
RDPT reduces the output driver size for lower current and less noise.
TCRE allows the counter to be reset by a channel 7 output compare.
These bits select the prescaler divisor for the timer counter.
1 = TOF interrupt requests enabled
0 = TOF interrupt requests disabled
1 = Pullup resistors enabled
0 = Pullup resistors disabled
1 = Output drive reduction enabled
0 = Output drive reduction disabled
1 = Counter reset enabled
0 = Counter reset disabled
Address: $008D
When the timer channel 7 registers contain $0000 and TCRE is set, the
timer counter registers remain at $0000 all the time.
When the timer channel 7 registers contain $FFFF and TCRE is set, TOF
never gets set even though the timer counter registers go from $FFFF to
$0000.
Reset:
Read:
Write:
Bit 7
TOI
0
Value
0
1
2
3
4
Figure 12-17. Timer Mask 2 Register (TMSK2)
= Unimplemented
6
0
0
Table 12-3. Prescaler Selection
MC68HC812A4 Data Sheet, Rev. 7
PR[2:1:0]
PUPT
000
001
010
011
100
5
1
NOTE
RDPT
4
0
TCRE
Prescaler Divisor
3
0
16
1
2
4
8
PR2
2
0
Registers and Reset Initialization
PR1
1
0
Bit 0
PR0
0
131